CN103633722B - The quick non-overshoot control switching circuit of maximum charging and discharging currents and control method thereof - Google Patents

Abstract

The invention belongs to electric and electronic technical field, be specifically related to a kind of quick non-overshoot control switching circuit of maximum charging and discharging currents for secondary cell test and control method thereof.The quick non-overshoot control switching circuit of maximum charging and discharging currents, main circuit anode is linked together by a current-limiting resistance and front end direct current positive source, current-limiting resistance by-pass switch in parallel, the other end of current-limiting resistance connects the leakage level that the positive pole of a capacitor and comprise the device for power switching of anti-paralleled diode, the wherein negative pole of capacitor and the negative pole of front end power supply and DC bus-be connected, the source class of device for power switching connects the one end of leakage level peace ripple inductance that another comprises the device for power switching of anti-paralleled diode.The control method that the maximum charging and discharging currents that the invention provides a kind of highly effective and safe switches fast, except possess fast current handling capability and except, the rising of electric current almost non-overshoot when charging and discharging state switches can also be realized.

Description

The quick non-overshoot control switching circuit of maximum charging and discharging currents and control method thereof

Technical field

The invention belongs to electric and electronic technical field, be specifically related to a kind of quick non-overshoot control switching circuit of maximum charging and discharging currents for secondary cell test and control method thereof.

Background technology

In storage battery production industry, various test need be carried out, as continuous battery pack endurance test, product enter OQC, design verification research, battery pack production on-line study and test etc. to the storage battery produced.Wherein from maximum charging current to maximum discharge current or with it reverse fast handover procedures is an important test to accumulator property examination.Stable I is reached to switching to of charging and discharging state _{charge_max}(maximum charging current) or I _{discharge_max}the time requirement of (maximum discharge current) is very of short duration, such as <0.01s(10ms).The current handling capability of this operating mode to accumulator testing equipment has very high requirement.Require the rapidity controlled on the one hand, require on the other hand to ensure big current (such as I _max>100A) reliability controlled and fail safe, Current Control overshoot wants little in order to avoid excessive current overshoot damages tested battery or testing equipment.

Summary of the invention

The object of the present invention is to provide a kind of quick non-overshoot control switching circuit of maximum charging and discharging currents switched for the quick non-overshoot of maximum charging and discharging currents of secondary cell test.The present invention also aims to provide a kind of maximum charging and discharging currents control method that quick non-overshoot switches.

The object of the present invention is achieved like this:

The quick non-overshoot control switching circuit of maximum charging and discharging currents, main circuit anode is by a current-limiting resistance and front end direct current positive source and DC bus+link together, current-limiting resistance by-pass switch K in parallel, the other end of current-limiting resistance connects the leakage level that the positive pole of a capacitor C and comprise the device for power switching VT1 of anti-paralleled diode D1, the wherein negative pole of capacitor C and the negative pole of front end power supply and DC bus-be connected, the source class of device for power switching VT1 connects the one end of the leakage level peace ripple inductance L that another comprises the device for power switching VT2 of anti-paralleled diode D2, wherein the negative pole of device for power switching VT2 is connected with the negative pole of front end direct current power supply, the other end of flat ripple inductance connects one end of fast acting fuse FUSE, the other end of fast acting fuse FUSE connects the positive pole of secondary accumulator battery to be measured, the negative pole of secondary accumulator battery is connected with the negative pole be connected with front end direct current power supply.

Main circuit is also provided with three transducers, comprises the Hall voltage transducer HV1 being connected in parallel on capacitor C two ends, measures DC bus-bar voltage v _bus; Be connected in parallel on the Hall voltage transducer HV2 at storage battery two ends, measure secondary accumulator battery terminal voltage v _bat; The Hall current sensor HC on inductance L lead-out wire is enclosed within, for detecting inductive current i by central through hole _l.

Circuit also comprises control system, and control system is by A/D change-over circuit sampling DC bus-bar voltage v _bus, secondary accumulator battery terminal voltage v _batwith inductive current i _l; The break-make of by-pass switch K is controlled by I/O interface circuit; The control signal that control system produces forms PWM1 and PWM2 pulse signal, for controlling the break-make of device for power switching VT1 or VT2 after drive circuit amplifies.

The control method that the quick non-overshoot of maximum charging and discharging currents switches:

(1) keep PWM2 signal to be low level, block device for power switching VT2, according to switch periods T _sat the end of sampling inductive current i _l, DC bus-bar voltage v _bus, cell voltage v _bat, the charging current expected of next switch periods and main circuit inductance value L calculate the duty ratio D of next switch periods _chargeand the comparison value COMP_CHARGE of corresponding switch periods digital quantity, COMP_CHARGE=D _charge× SW_PERIOD, T _scorresponding Timer Digital amount is SW_PERIOD, is assigned to the timer passage of CPU corresponding device for power switching VT1 driving pulse PWM1;

(2) I is not being reached _{charge_max}before, repeated execution of steps (1), if reach I _{charge_max}, then this current value is kept to continue preset time T _{charge_hold};

(3) T is arrived _{charge_hold}after, pulse signal PWM1 is set to low level, blocks device for power switching VT1, detect inductive current i in each switch periods afterwards _l, i during this period _lbe in afterflow attenuation state, work as i _lwhen being zero, remove the blockade to device for power switching VT2;

(4) according to the sampling inductive current i at the end of current switch period _l, DC bus-bar voltage v _bus, cell voltage v _bat, the discharging current expected of next switch periods and main circuit inductance value L calculate the duty ratio D of next switch periods _discharge, and the comparison value COMP_DISCHARGE of corresponding switch periods digital quantity, COMP_DISCHARGE=D _discharge× SW_PERIOD, and timer passage value being assigned to CPU corresponding device for power switching VT2 driving pulse PWM2;

(5) I is not being reached _{discharge_max}, repeat (4), if reach I before _{discharge_max}, then this current value is kept to continue preset time T _{discharge_hold};

(6) T is arrived _{discharge_hold}after, pulse signal PWM2 is set to low level, and block device for power switching VT2, if DC bus-bar voltage is higher than battery tension, then inductive current iL is by Natural Attenuation to zero, and a charge and discharge process terminates.

Beneficial effect of the present invention is: the control method that the maximum charging and discharging currents that the invention provides a kind of highly effective and safe switches fast, except possess fast current handling capability and except, the rising of electric current almost non-overshoot when charging and discharging state switches can also be realized.Particularly for control of discharge process, due at electric discharge device, system main circuit is operated in Boost pressure-increasning state, there is the Right-half-plant zero that makes system non-minimum phase in its circuit transfer function model, this, respective frequencies was lower and produce 90 ° of delayed phase at zero point, therefore stable in order to what ensure to control, by with the bandwidth of sacrificing control system for cost, and adopt the control method designed by this patent can avoid the limitation of conventional control linear regulator in control bandwidth.And according to the designed capacity of control system and main circuit, the time adopting the method for this patent that charge and discharge control pattern can be made to switch to current stabilization can adjust flexibly.

Accompanying drawing explanation

Fig. 1 is the system configuration and the typical applications thereof that can be used for realizing this patent charge and discharge control.

Fig. 2 is main circuit structure and the current path of charging stage.

Fig. 3 is main circuit structure and the current path of discharge regime.

Fig. 4 is that several selectable exemplary inductor current arranges curve.

The charging and discharging currents checking waveform that Fig. 5 obtains for method described in sampling this patent.

Embodiment

Below in conjunction with accompanying drawing, the present invention is described further

The present invention is to provide the control method that quick (such as the switching to stable time <10ms) non-overshoot of a kind of maximum charging and discharging currents for secondary cell test switches.Comprise the control strategy based on the Single switch periodic adjustment of inductive current and the given value of current method that coordinates with it.

1 be described by reference to the accompanying drawings.Realize the main circuit anode that the quick non-overshoot of maximum charging and discharging currents switches to be linked together by the current-limiting resistance of a by-pass switch K in parallel and front end direct current positive source (DC bus+), the other end of resistance connects the leakage level that the positive pole of a capacitor C and comprise the device for power switching (VT1) of anti-paralleled diode (D1), wherein the negative pole of capacitor C is connected (DC bus-) with the negative pole of front end power supply, the source class of VT1 connects one end of the leakage level peace ripple inductance L of another device for power switching comprising anti-paralleled diode (D2) (VT2), wherein the negative pole of VT2 is connected with the negative pole of front end direct current power supply, the other end of flat ripple inductance connects one end of fast acting fuse (FUSE), the other end of FUSE connects the positive pole of secondary accumulator battery to be measured, the negative pole of secondary accumulator battery is connected with the negative pole be connected with front end direct current power supply.

In order to make the control of control system realization to electric current, be provided with three transducers at main circuit, comprise the Hall voltage transducer HV1 being connected in parallel on capacitor C two ends, this voltage sensor is for measuring DC bus-bar voltage v _bus; Be connected in parallel on the Hall voltage transducer HV2 at storage battery two ends, this voltage sensor is for measuring secondary accumulator battery terminal voltage v _bat; Be enclosed within the Hall current sensor HC on inductance L lead-out wire by central through hole, this current sensor is for detecting inductive current i _l.

Control system is by A/D change-over circuit sampling DC bus-bar voltage v _bus, secondary accumulator battery terminal voltage v _batwith inductive current i _l; The break-make of by-pass switch K is controlled by I/O interface circuit; The control signal that control system produces forms PWM1 and PWM1 pulse signal, for controlling the break-make of device for power switching VT1 or VT2 after drive circuit amplifies.

When being in charged state, electric energy flows to storage battery by DC bus, now only PWM1 pulse signal is effective, device for power switching VT1 is on off operating mode, and PWM2 signal is always low level, make device for power switching VT2 be in blocked styate, diode D2 antiparallel with it is used for the inductive current afterflow when VT1 turns off, as shown in Figure 2; When system works is in discharge condition, electric energy flows to DC bus by storage battery, now only PWM2 pulse signal is effective, device for power switching VT2 is on off operating mode, and PWM2 signal is always low level, make device for power switching VT1 be in blocked styate, when VT2 turns off, inductive energy storage one direction is discharged into DC bus by its antiparallel diode D1, as shown in Figure 3.

From charging current inductive current i _lbe zero to I _{charge_max}(maximum charging current), then arrives I _{discharge_max}(maximum discharge current) arrive again inductive current be zero process be such:

(1) keep PWM2 signal to be low level, block VT2.According to current switch period (T _s, corresponding Timer Digital amount is SW_PERIOD) at the end of sampling inductive current i _l, DC bus-bar voltage v _bus, cell voltage v _bat, the charging current expected of next switch periods and main circuit inductance value L calculate the duty ratio D of next switch periods _charge, and the comparison value COMP_CHARGE(COMP_CHARGE=D of corresponding switch periods digital quantity _charge× SW_PERIOD), and this value is assigned to the timer passage of corresponding VT1 driving pulse (PWM1) of CPU;

(2) I is not being reached _{charge_max}before, repeat (1), if reach I _{charge_max}, then by controlling to keep this current value to continue preset time T _{charge_hold};

(3) T is arrived _{charge_hold}after, PWM1 is set to low level, blocks VT1, detect inductive current i in each switch periods afterwards _l, i during this period _lbe in afterflow attenuation state, work as i _lwhen being zero, remove the blockade to VT2;

(4) according to the sampling inductive current i at the end of current switch period _l, DC bus-bar voltage v _bus, cell voltage v _bat, the discharging current expected of next switch periods and main circuit inductance value L calculate the duty ratio D of next switch periods _discharge, and the comparison value COMP_DISCHARGE(COMP_DISCHARGE=D of corresponding switch periods digital quantity _discharge× SW_PERIOD), and this value is assigned to the timer passage of corresponding VT2 driving pulse (PWM2) of CPU;

(5) I is not being reached _{discharge_max}before, repeat (4), if reach I _{discharge_max}, then by controlling to keep this current value to continue preset time T _{discharge_hold};

(6) T is arrived _{discharge_hold}after, PWM2 is set to low level, and block VT2, if DC bus-bar voltage is higher than battery tension, then inductive current iL is by Natural Attenuation to zero, and a charge and discharge process terminates.

In the typical apply shown in accompanying drawing 1, the DC power supply of front end can be diode rectification power supply, silicon con trolled rectifier power supply or PWM high-frequency rectification power supply etc.DC bus in parallelly can overlap the device identical with module 1 more, as required, keeping can connecting N cover under the stable prerequisite of DC bus-bar voltage.If front end direct current power supply irreversible (as diode rectification power supply), then need configuring direct current chopping device on DC bus, when the electric energy that some discharge module is released can not be received by charging module completely and cause DC bus-bar voltage to raise, by chopping device by power consumption in resistive load.If front end direct current power supply reversible (PWM high-frequency rectification etc.), then discharge energy is except can for except charging module, also can feedback grid.

Accompanying drawing 1 dotted box portion, for adopting a hardware configuration schematic diagram of control strategy described in patent, is designated module 1.In fact by device for power switching VT1(containing D1), VT2(is containing D2), the main circuit that forms of capacitor C peace ripple inductance is a Buck/Boost buck two-way DC converter structure of not isolating, and DC bus power flow storage battery (now main circuit is operated in Buck decompression mode) can be controlled as required, or control storage battery power flow DC bus (now main circuit is operated in Boost boost mode).

As shown in Figure 1, during owing to being operated in Buck pattern, namely PWM1 drive singal is effective, and VT1 is in running order, and PWM2 is low level, and VT2 is blocked.With DC bus negative pole for reference point position, when VT1 conducting, A point electromotive force is v _bus, when VT1 turns off, due to the clamping action of diode D2, A point electromotive force is " 0 ", and namely A point electromotive force is floating, therefore the drive singal reference point of VT1, namely PWM1 signal " " not should with DC bus negative pole equipotential.

And when circuit working is in Boost pattern, namely PWM2 drive singal is effective, VT2 is in running order, and PWM1 is low level, and VT1 is blocked, and there is not the problem of potential fluctuation, VT2 drive singal PWM2 " " be DC bus negative pole.

Therefore, PWM1 and PWM2 is the drive circuit output signal of two-way isolation.

When main circuit initially powers on (DC bus connection), control system passes through S _wsignal-controlled switch K is in disconnection, and DC bus is via current limliting R to electric capacity C current-limiting charge, and prevent excessive capacitance charging current infringement capacitor or cause other fault, control K closes bypass current-limiting resistance R afterwards.

Fast acting fuse FUSE, for providing a kind of safeguard measure to overcurrent, improves the one protection to main circuit and storage battery when controlling malfunctioning.

In conjunction with Figure of abstract, with from charging current inductive current i _lbe zero to I _{charge_max}(maximum charging current), then arrives I _{discharge_max}(maximum discharge current) arrive again inductive current be zero process be example illustrate implement control detailed process.

(1) charging current by zero to I _{charge_max}control

Now main circuit is operated in Buck decompression mode, and electric energy flows to storage battery by DC bus, as shown in Figure 2.

When VT1 conducting, current path is as shown in dotted line 1, charge in batteries energy storage.If switch periods is T _s, the inductive current of VT1 conduction period is i _l1, VT1 conducting duty ratio is D _charge, then have during VT1 conducting then the inductive current increment of VT1 conduction period is:

${\mathrm{\&Delta;i}}_{L1}=\frac{(v_{\mathrm{bus}}-v_{\mathrm{bat}})D_{\mathrm{ch}\arg e}{T}_s}{L}---\left(1\right)$

When VT1 turns off, current path is as shown in the dotted line 2 of accompanying drawing 2, and inductive current is in freewheeling state, if inductive current is now i _l2, have then the inductive current increment of freewheeling period is:

${\mathrm{\&Delta;i}}_{L2}=\frac{-v_{\mathrm{bat}}(1-D_{\mathrm{ch}\arg e})T_s}{L}---\left(2\right)$

By formula (1) and formula (2) can the inductive current increment in a switch periods be then:

${\mathrm{\&Delta;i}}_L={\mathrm{\&Delta;i}}_{L1}+{\mathrm{\&Delta;i}}_{L2}=\frac{v_{\mathrm{bus}}{D}_{\mathrm{ch}\arg e}{T}_s-v_{\mathrm{bat}}{T}_s}{L}---\left(3\right)$

If current time inductive current is i _k, expectation electric current during next end cycle is i _k+1, then can obtain the PWM duty ratio in next cycle according to formula (3) should be set to:

$D_{\mathrm{ch}\arg e}=\frac{(i_{k+1}-i_k)L}{v_{\mathrm{bus}}{T}_s}+\frac{v_{\mathrm{bat}}}{v_{\mathrm{bus}}}---\left(4\right)$

In each switch periods finish time, all by the inductive current i of A/D sampling circuit samples current time _k, DC bus-bar voltage v _buswith battery tension v _bat, the duty ratio D of next switch periods is calculated according to formula (4) _chargeif, switch periods T _sdigital quantity corresponding in CPU timer is SW_PERIOD, then duty ratio D _chargecorresponding comparison value COMP_CHARGE=D _charge× SW_PERIOD, is assigned to the timer passage of corresponding VT1 driving pulse (PWM1) of CPU by this value.In theory, at the end of next switch periods, charging inductance electric current will reach the i of expectation _k+1.

At the inductive current i of A/D sampling _ldo not arrive I _{charge_max}(i before _lwith I _{charge_max}difference be greater than default deviation delta i _charge), all according to said process to duty ratio D _chargeimplement to control

(2) charging current I is kept _{charge_max}continue T _{charge_hold}time

Work as i _lwith I _{charge_max}difference be less than default deviation delta i _charge, namely think inductive current i _lalmost arrive I _{charge_max}, then in each switch periods finish time according to the following formula to D _chargeregulate.

$D_{\mathrm{ch}\arg e}=\frac{(i_{\mathrm{ch}\arg e\_\max }-i_k)L}{v_{\mathrm{bus}}{T}_s}+\frac{v_{\mathrm{bat}}}{v_{\mathrm{bus}}}---\left(5\right)$

(3) charging current I _{charge_max}decay to zero

The time of carrying out charging duty cycle adjustment according to formula (5) is kept to be default duration T _{charge_hold}, afterwards PWM1 is set to low level, blocks VT1, detect inductive current i in each switch periods afterwards _l, inductive current i during this period _lbe in afterflow attenuation state, time of afterflow is t _fw=I _{charge_max}l/v _bat, with I _{charge_max}=120A, L=1mH, v _bat=400V be example can obtain inductive current free damping be zero time of afterflow be t _fw=300 μ s, time of afterflow of short duration as seen can not cause appreciable impact to controlling fast.

When sampling i _lwhen being zero (and i _lpreset value is less than with the deviation of 0), remove the blockade to VT2, system will enter electric discharge operating state.

(4) discharging current by zero to I _{discharge_max}control

Now main circuit is operated in Boost boost mode, and electric energy flows to DC bus by storage battery, as shown in Figure 3.

When VT2 turns off, current path is as shown in dotted line 1, and storage battery discharges to DC bus.If switch periods is T _s, the inductive current of VT2 blocking interval is i _l1, the duty ratio of VT2 conducting is D _discharge, have then the inductive current increment of VT2 blocking interval is:

${\mathrm{\&Delta;i}}_{L1}=\frac{(v_{\mathrm{bat}}-v_{\mathrm{bus}})(1-D_{\mathrm{disch}\arg e})T_s}{L}---\left(6\right)$

When VT2 conducting, current path is as shown in such as dotted line 2, and inductance is in energy storage state, if inductive current is now i _l2, have then the current increment in inductive energy storage stage is:

${\mathrm{\&Delta;i}}_{L2}=\frac{v_{\mathrm{bat}}{D}_{\mathrm{disch}\arg e}{T}_s}{L}---\left(7\right)$

When can be discharged by formula (6) and formula (7), the inductive current increment in a switch periods is:

${\mathrm{\&Delta;i}}_L={\mathrm{\&Delta;i}}_{L1}+{\mathrm{\&Delta;i}}_{L2}=\frac{v_{\mathrm{bat}}{T}_s+v_{\mathrm{bus}}(D_{\mathrm{disch}\arg e}-1)T_s}{L}---\left(8\right)$

If current time inductive current is i _k, expectation electric current during next end cycle is i _k+1, then can obtain the PWM duty ratio in next cycle according to formula (8) should be set to:

$D_{\mathrm{disch}\arg e}=\frac{(i_{k+1}-i_k)L}{v_{\mathrm{bus}}{T}_s}+\frac{v_{\mathrm{bus}}-v_{\mathrm{bat}}}{v_{\mathrm{bus}}}---\left(9\right)$

In each switch periods finish time, all by the inductive current i of A/D sampling circuit samples current time _k, DC bus-bar voltage v _buswith battery tension v _bat, the duty ratio D of next switch periods is calculated according to formula (9) _dischargeif, switch periods T _sdigital quantity corresponding in CPU timer is SW_PERIOD, then duty ratio D _dischargecorresponding comparison value COMP_DISCHARGE=D _discharge× SW_PERIOD, is assigned to the timer passage of corresponding VT2 driving pulse (PWM2) of CPU by this value.In theory, at the end of next switch periods, charging inductance electric current will reach the i of expectation _k+1.

At the inductive current i of A/D sampling _ldo not arrive I _{discharge_max}(i before _lwith I _{discharge_max}difference be greater than default deviation delta i _discharge), all according to said process to duty ratio D _dischargeimplement to control.

(5) discharging current I is kept _{discharge_max}continue T _{discharge_hold}time

Work as i _lwith I _{discharge_max}difference be less than default deviation delta i _discharge, namely think inductive current i _lalmost arrive I _{discharge_max}, then in each switch periods finish time according to the following formula to D _dischargeregulate.

$D_{\mathrm{disch}\arg e}=\frac{(i_{\mathrm{disch}\arg e\_\max }-i_k)L}{v_{\mathrm{bus}}{T}_s}+\frac{v_{\mathrm{bat}}}{v_{\mathrm{bus}}}---\left(10\right)$

(6) discharging current I _{discharge_max}decay to zero

The time of carrying out electric discharge duty cycle adjustment according to formula (10) is kept to be default duration T _{discharge_hold}, afterwards PWM2 is set to low level, blocks VT2, due to DC bus-bar voltage v _bushigher than battery tension v _bat, inductive current i _lafterflow is decayed to zero, and the afterflow duration is t _fw=I _{discharge_max}l/(v _bat-v _bat), with I _{discharge_max}=120A, L=1mH, v _bat=400V, v _bus=600V be example can obtain inductive current free damping be zero time of afterflow be t _fw=600 μ s, time of afterflow of short duration as seen can not cause appreciable impact to controlling fast.

Discharging current i _lby zero to I _{discharge_max}(maximum discharge current), then arrives I _{charge_max}(maximum charging current) arrive again inductive current be zero process be the inverse process of said process, repeat no more.

Next switch periods typical of several available use expects inductor current value i _k+1curve is set as shown in Figure 4.Under duty cycle adjustment rule described in employing this patent, as long as arrive given value of current value final value I _{discharge_max}or I _{charge_max}time be less than (equaling) preset time t _maxthe requirement that electric current is controlled fast can be met.

For accompanying drawing 4(a) shown in linear increment rate, if switch periods is T _s, inductive current by zero to I _{discharge_max}or I _{charge_max}time be t _max=NT _s, then correspond to each switch periods, meet t _maxthe current increment of time restriction is Δ I>=I _{discharge_max}/ N or Δ I>=I _{charge_max}/ N, therefore, the inductive current desired value arranging next switch periods at the end of each switch periods is i _k+1=ik+1+ Δ I.Such as, if I _{charge_max=}120A, t _max=5ms, T _s=0.2ms, then N=25, Δ I>=4.8A.

In order to realize the quick control to inductive current in charging and discharging transfer process, except calculate according to formula (4) or formula (9) and upgrade duty ratio and except, the appropriate design of inductance value L is also a key, should meet following constraint requirements:

(1) inductance L should have the ability of bearing current peak in working range, namely still keeps keeping linear by inductance during peak current, does not occur saturated;

(2) at switching frequency T _swhen certain, for the v determining excursion _bus∈ [v _{bus_min}, v _{bus_max}] and v _bat∈ [v _{bat_min}, v _{bat_max}], be less than or equal to maximum duty cycle D _{charge_max}or D _{discharge_max}under condition, the inductance value L that can realize Δ I increment in a switch periods should meet following coboundary constraints respectively:

$L_{\mathrm{ch}\arg e}\&le;\frac{v_{\mathrm{bus}\_\min }{D}_{\mathrm{ch}\arg e\_\max }{T}_s-v_{\mathrm{bat}\_\max }{T}_s}{\mathrm{\&Delta;I}}---\left(11\right)$

$L_{\mathrm{disch}\arg e}\&le;\frac{v_{\mathrm{bat}\_\min }{T}_s+v_{\mathrm{bus}\_\max }(D_{\mathrm{disch}\arg e\_\max }-1)T_s}{\mathrm{\&Delta;T}}---\left(12\right)$

Because inductance is operated in the handoff procedure of charging and discharging, inductance L primary election value should meet L ₁=min(L _charge, L _discharge), the little value namely in modus ponens (11) and formula (12).

But for maximum induction current wave momentum Δ I under suppression limit _{s_max}requirement, under continuous current mode condition, inductance value should meet following lower boundary constraints:

$L_{\mathrm{ch}\arg e}\&GreaterEqual;\frac{v_{\mathrm{bus}\_\max }{D}_{\mathrm{ch}\arg e}(1-D_{\mathrm{ch}\arg e})T_s}{\mathrm{\&Delta;}{I}_{s\_\max }}---\left(13\right)$

For discharge regime, under continuous current mode condition, inductance value should meet following lower boundary constraints respectively:

$L_{\mathrm{disch}\arg e}\&GreaterEqual;\frac{v_{\mathrm{bat}\_\max }{D}_{\mathrm{disch}\arg e}{T}_s}{{\mathrm{\&Delta;I}}_{S\_\max }}---\left(14\right)$

Because inductance is operated in the handoff procedure of charging and discharging, inductance L value should meet L with this understanding ₂=max(L _charge, L _discharge), the large value namely in modus ponens (13) and formula (14).

To sum up, inductance L value should meet: L ₂<L<L ₁.

(6) the result

Proposed carrying out is verified, wherein L=4mH, switching frequency 5kHz, DC bus-bar voltage 400V, battery tension 200V, control charging and discharging currents respectively and arrive 100A at 5ms non-overshoot.Steady-state current fluctuation is less than 5A, and result as shown in Figure 5.

Claims (1)

1. the control method of the quick non-overshoot switching of maximum charging and discharging currents, comprise: main circuit anode is by a current-limiting resistance and front end direct current positive source and DC bus+link together, current-limiting resistance by-pass switch K in parallel, the other end of current-limiting resistance connects the leakage level that the positive pole of a capacitor C and comprise the device for power switching VT1 of anti-paralleled diode D1, the wherein negative pole of capacitor C and the negative pole of front end power supply and DC bus-be connected, the source class of device for power switching VT1 connects the one end of the leakage level peace ripple inductance L that another comprises the device for power switching VT2 of anti-paralleled diode D2, wherein the negative pole of device for power switching VT2 is connected with the negative pole of front end direct current power supply, the other end of flat ripple inductance connects one end of fast acting fuse FUSE, the other end of fast acting fuse FUSE connects the positive pole of secondary accumulator battery to be measured, the negative pole of secondary accumulator battery is connected with the negative pole be connected with front end direct current power supply, described main circuit is also provided with three transducers, comprises the Hall voltage transducer HV1 being connected in parallel on capacitor C two ends, measures DC bus-bar voltage v _bus, be connected in parallel on the Hall voltage transducer HV2 at storage battery two ends, measure secondary accumulator battery terminal voltage v _bat, the Hall current sensor HC on inductance L lead-out wire is enclosed within, for detecting inductive current i by central through hole _l, described circuit also comprises control system, and control system is by A/D change-over circuit sampling DC bus-bar voltage v _bus, secondary accumulator battery terminal voltage v _batwith inductive current i _l, the break-make of by-pass switch K is controlled by I/O interface circuit, the control signal that control system produces forms PWM1 and PWM2 pulse signal after drive circuit amplifies, and for controlling the break-make of device for power switching VT1 or VT2, it is characterized in that:

(1) keep PWM2 signal to be low level, block device for power switching VT2, according to switch periods T _sat the end of sampling inductive current i _l, DC bus-bar voltage v _bus, cell voltage v _bat, the charging current expected of next switch periods and main circuit inductance value L calculate the duty ratio D of next switch periods _chargeand the comparison value COMP_CHARGE of corresponding switch periods digital quantity, COMP_CHARGE=D _charge× SW_PERIOD, T _scorresponding Timer Digital amount is SW_PERIOD, is assigned to the timer passage of CPU corresponding device for power switching VT1 driving pulse PWM1;

(2) I is not being reached _{charge_max}before, repeated execution of steps (1), if reach I _{charge_max}, then this current value is kept to continue preset time T _{charge_hold};

(3) T is arrived _{charge_hold}after, pulse signal PWM1 is set to low level, blocks device for power switching VT1, detect inductive current i in each switch periods afterwards _l, i during this period _lbe in afterflow attenuation state, work as i _lwhen being zero, remove the blockade to device for power switching VT2;

(4) according to the sampling inductive current i at the end of current switch period _l, DC bus-bar voltage v _bus, cell voltage v _bat, the discharging current expected of next switch periods and main circuit inductance value L calculate the duty ratio D of next switch periods _discharge, and the comparison value COMP_DISCHARGE of corresponding switch periods digital quantity, COMP_DISCHARGE=D _discharge× SW_PERIOD, and timer passage value being assigned to CPU corresponding device for power switching VT2 driving pulse PWM2;

(5) I is not being reached _{discharge_max}, repeat (4), if reach I before _{discharge_max}, then this current value is kept to continue preset time T _{discharge_hold};

(6) T is arrived _{discharge_hold}after, pulse signal PWM2 is set to low level, blocks device for power switching VT2, if DC bus-bar voltage is higher than battery tension, then inductive current i _lby Natural Attenuation to zero, a charge and discharge process terminates.