CN103632975A - Pmos transistor and manufacturing method thereof - Google Patents
Pmos transistor and manufacturing method thereof Download PDFInfo
- Publication number
- CN103632975A CN103632975A CN201210312944.3A CN201210312944A CN103632975A CN 103632975 A CN103632975 A CN 103632975A CN 201210312944 A CN201210312944 A CN 201210312944A CN 103632975 A CN103632975 A CN 103632975A
- Authority
- CN
- China
- Prior art keywords
- material layer
- silicon germanium
- germanium material
- star
- sigma connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 124
- 239000000463 material Substances 0.000 claims abstract description 116
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 112
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 30
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims description 40
- 230000015572 biosynthetic process Effects 0.000 claims description 19
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 18
- 238000011065 in-situ storage Methods 0.000 claims description 15
- 239000000243 solution Substances 0.000 claims description 14
- 239000012670 alkaline solution Substances 0.000 claims description 9
- 239000002019 doping agent Substances 0.000 claims description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 8
- 229910052796 boron Inorganic materials 0.000 claims description 8
- 238000012545 processing Methods 0.000 claims description 8
- 235000011114 ammonium hydroxide Nutrition 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 description 24
- 238000000576 coating method Methods 0.000 description 24
- 230000006835 compression Effects 0.000 description 10
- 238000007906 compression Methods 0.000 description 10
- 238000000151 deposition Methods 0.000 description 10
- 239000002184 metal Substances 0.000 description 8
- 230000008021 deposition Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- 230000007547 defect Effects 0.000 description 5
- 238000002513 implantation Methods 0.000 description 5
- 238000002360 preparation method Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000013459 approach Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000010129 solution processing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
Abstract
Provided is a manufacturing method of a PMOS transistor. The manufacturing method comprises that: a substrate is provided, and a sigma-shaped groove is formed in a region which is predetermined to form a source region and a drain region in the substrate; a first silicon germanium material layer is filled in the sigma-shaped groove, and the sigma-shaped groove is not completely filled with the first silicon germanium material layer; partial thickness of the first silicon germanium material layer arranged on the bottom part of the sigma-shaped groove is removed; and a second silicon germanium material layer is filled in the sigma-shaped groove untill the sigma-shaped groove is completely filled, wherein the content of germanium in the second silicon germanium material layer is higher than the content of germanium in the first silicon germanium material layer. Besides, the invention also provides the PMOS transistor manufactured via the aforementioned manufacturing method. With application of the technical scheme of the invention, carrier mobility of the PMOS transistor can be enhanced.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of PMOS transistor and preparation method thereof.
Background technology
In existing semiconductor device fabrication process, because stress can change energy gap and the carrier mobility of silicon materials, the performance that therefore improves MOS transistor by stress becomes more and more conventional means.Particularly, by suitable proof stress, can improve charge carrier (electronics in nmos pass transistor, the hole in PMOS transistor) mobility, and then improve drive current, with this, greatly improve the performance of MOS transistor.For PMOS transistor, can adopt embedded SiGe technology (Embedded SiGe Technology) to produce compression at transistorized channel region, and then improve carrier mobility.So-called embedded SiGe technology refers to embedding silicon germanium material in the region that need to form source region and drain region of Semiconductor substrate, utilizes the lattice mismatch between silicon and SiGe (SiGe) to produce compression to channel region.
Fig. 1 is a kind of transistorized cutaway view of PMOS that has adopted embedded SiGe technology, as shown in Figure 1, PMOS transistor comprises the gate insulator 11 and the grid 12 that are formed on successively on substrate 10, is formed on the side wall 13 of gate insulator 11 and grid 12 both sides and is respectively formed at gate insulator 11 and the source electrode 14 of grid 12 both sides, drain 15, wherein, source electrode 14 and to drain 15 be to consist of the silicon germanium material that is filled in sigma connected in star 16.Sigma connected in star 16, its shape and symbol ∑ approach, and have flute tips 161, and silicon germanium material produces compression just by realizing forming upper surface 1611, the lower surface 1612 generation pressure of this flute tips 161 to channel region.For avoiding the interior silicon germanium material of groove 16 that lattice mismatch large between SiGe and silicon the causes poor problem of growing, generally first form a resilient coating that Ge content is lower sigma connected in star 16 is interior, on resilient coating, adopt again afterwards the silicon germanium material that Ge content is higher to fill.
Yet the inventor, when the PMOS transistor of the embedded SiGe of research, finds the poor effect of the PMOS transistor raising carrier mobility that said method forms.
Summary of the invention
The object that the present invention realizes is to provide a kind of new PMOS transistor and preparation method thereof, to improve its carrier mobility.
For achieving the above object, the transistorized manufacture method of PMOS provided by the invention, comprising:
Monocrystalline substrate is provided, and in described substrate, the predetermined region that forms source region and drain region is formed with sigma connected in star;
In described sigma connected in star, fill the first silicon germanium material layer, described the first silicon germanium material layer does not fill up described sigma connected in star;
Remove the first silicon germanium material layer of the segment thickness of described sigma connected in star bottom;
To filling the second silicon germanium material layer in described sigma connected in star, to filling up, stop, the content of the germanium of described the second silicon germanium material layer is higher than the content of the germanium of described the first silicon germanium material layer.
Alternatively, the first silicon germanium material layer of removing the segment thickness of described sigma connected in star bottom is processed realization by alkaline solution.
Alternatively, described alkaline solution is TMAH solution or ammoniacal liquor.
Alternatively, the temperature of described processing is 20 ~ 100 ℃, and the processing time is 5 ~ 100s.
Alternatively, the atomicity percentage to the germanium of the first silicon germanium material layer of filling in described sigma connected in star is 5 ~ 30%.
Alternatively, when filling the first silicon germanium material layer in described sigma connected in star, carry out in-situ doped P type element.
Alternatively, the doped chemical during the P type element that carries out when filling the first silicon germanium material layer in described sigma connected in star is in-situ doped is boron, and dopant dose is 0.1 ~ 5E20/cm
3.
Alternatively, the thickness to the first silicon germanium material layer of filling in described sigma connected in star is 2 ~ 5nm.
Alternatively, the atomicity percentage to the germanium of the second silicon germanium material layer of filling in described sigma connected in star is 20 ~ 60%
Alternatively, when filling the second silicon germanium material layer in described sigma connected in star, carry out in-situ doped P type element.
Alternatively, the doped chemical during the P type element that carries out when filling the second silicon germanium material layer in described sigma connected in star is in-situ doped is boron, and dopant dose is 0.1 ~ 5E20/cm
3.
Alternatively, the thickness to the second silicon germanium material layer of filling in described sigma connected in star is 3 ~ 10nm.
Alternatively, to filling the second silicon germanium material layer in described sigma connected in star to after filling up and stopping, also at least on described the second silicon germanium material layer, form the 3rd silicon germanium material layer, the content of the germanium of described the 3rd silicon germanium material layer is lower than the content of the germanium of described the second silicon germanium material layer.
Alternatively, the atomicity percentage of the germanium of the 3rd silicon germanium material layer of formation is less than 30%
Alternatively, while forming the 3rd silicon germanium material layer, carry out in-situ doped P type element.
Alternatively, the doped chemical during the P type element that carries out while forming the 3rd silicon germanium material layer is in-situ doped is boron, and dopant dose is 0.1 ~ 5E20/cm
3.
Alternatively, the thickness of the 3rd silicon germanium material layer of formation is less than 5nm.
Alternatively, the formation method of described sigma connected in star is: on described substrate, form grid structure, in described grid structure both sides, form side wall, take described grid structure and side wall as mask, in described substrate, the predetermined region that forms source region and drain region forms sigma connected in star.
In addition, the present invention also provides a kind of PMOS transistor of making according to above-mentioned either method.
Compared with prior art, the present invention has the following advantages:
1) shortcoming of the transistorized scheme of the embedded SiGe PMOS of existing formation is: resilient coating (the silicon germanium material layer that Ge content is lower, be equivalent to ground floor silicon germanium material layer) in lower surface (111 crystallographic systems of the corresponding silicon germanium material) deposition rate that forms flute tips, be slower than the deposition rate of bottom portion of groove (100 crystallographic systems of corresponding silicon germanium material), thereby cause the ground floor silicon germanium material layer that germanium concentration is low to account for the more space of having stayed sigma connected in star, limited the amount of inserting of the high second layer silicon germanium material of germanium concentration layer, therefore limited the stress that raceway groove is applied, in other words, inadequate to raceway groove applied pressure.Be different from such scheme, the present invention adopts after forming resilient coating, removes the resilient coating of part sigma connected in star bottom, adopts afterwards packed layer (being second layer silicon germanium material layer) to fill again.So, improved the volume of the silicon germanium material layer of high-load germanium in groove, increased the stress to raceway groove, this programme provides the embedded SiGe PMOS transistor that raceway groove is applied to uniform compression, raceway groove is applied to enough compression and can make the transistorized carrier mobility of this PMOS better.
2), in possibility, remove resilient coating and realize by TMAH solution-treated, utilized TMAH solution to the corrosion rate of 100 crystallographic systems of silicon germanium material higher than the corrosion rate to 111 crystallographic systems, and this TMAH solution environmentally safe.
3) in possibility, forming the transistorized source region of PMOS and drain region has two schemes: the first: forming resilient coating and adopting after packed layer filling groove, adopting the material of filling in Implantation normal direction groove to mix P type element; The second, forming resilient coating and adopting in the process of packed layer filling groove, adopts in-situ doped formation P trap, and this is in-situ doped is limit depositing silicon germanium material, and limit doping has avoided first method easily in the source region forming and drain region, to produce the shortcoming of defect.
4) in possibility, to filling the second silicon germanium material layer in sigma connected in star to after filling up and stopping, also on the second silicon germanium material layer, form the 3rd silicon germanium material layer (cap layer), the content of the germanium of the 3rd silicon germanium material layer is lower than the content of the germanium of the second silicon germanium material layer.Benefit is: to filling in sigma connected in star, fill the second silicon germanium material layer after the first thinner silicon germanium material layer and stop to filling up, object is to form source region and drain region, this source region and drain region are in order to realize and being electrically connected to of other device, after on it, extended meeting forms metal interconnect structure, such as conductive plunger etc., the silicone content of the 3rd silicon germanium material layer, due to higher, is easy to form metal silicide to reduce the contact resistance between source region, drain region and conductive plunger.
Accompanying drawing explanation
Fig. 1 is the transistorized schematic cross-section of existing embedded SiGe PMOS;
Fig. 2 has shown the defect of structure shown in Fig. 1;
Fig. 3 is the speed of growth schematic diagram of each crystallographic system of silicon germanium material;
Fig. 4 is the transistorized manufacture method flow chart of the PMOS of the embodiment of the present invention one;
Fig. 5 to Fig. 7 is the transistorized intermediate structure schematic diagram of PMOS forming according to Fig. 4 flow process;
Fig. 8 is the transistorized final structure schematic diagram of PMOS forming according to Fig. 4 flow process;
Fig. 9 is the transistorized cross section structure schematic diagram of the PMOS in embodiment tri-.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail, owing to focusing on that principle of the present invention is described, so do not draw to scale.
As previously mentioned, shown in Fig. 2, the transistorized scheme of the embedded SiGe PMOS of existing formation, for first to form a resilient coating 171 that Ge content is lower in sigma connected in star, adopts the silicon germanium material 172 that Ge content is higher to fill afterwards on resilient coating 171 again.The lattice structure of silicon germanium material is diamond lattic structure, has the crystallographic systems such as 100,111,110.
For the deposition rate of corresponding each crystallographic systems of shows buffer layer 171, take its deposition rate in crystallographic system 111 is benchmark, and the deposition rate of the crystallographic systems such as corresponding 100,110 as shown in Figure 3.Shown in Fig. 2 and Fig. 3, be formed on 111 crystallographic systems of the corresponding silicon germanium material of upper and lower surface 1611,1612(of flute tips 161) on deposition rate be slower than the deposition rate of groove 16 bottoms (100 crystallographic systems of corresponding silicon germanium material), this easily causes and has formed after resilient coating 171, there is distortion in sigma connected in star 16 spaces of filling for the higher silicon germanium material 172 of Ge content, thereby cause the compression that raceway groove is applied inadequate, especially too small near the compression on groove 16 bottom sections at the lower surface 1612 that forms sigma connected in star tip 161.
For the problems referred to above, below provide three kinds of transistorized manufacture methods of PMOS to solve.
Embodiment mono-
In conjunction with the flow chart of Fig. 4 and the schematic cross-section shown in Fig. 5, first perform step S11, monocrystalline substrate 20 is provided, in substrate 20, predetermined 24Ji drain region, the source region 25(that forms is with reference to shown in Fig. 8) region be formed with sigma connected in star 26.
Particularly, shown in Fig. 5, the method that forms sigma connected in star 26 is: on substrate 20, form grid structure, in grid structure both sides, form side wall 23, take grid structure and side wall 23 carries out etching as mask, and in substrate, the predetermined region that forms 24Ji drain region, source region 25 forms sigma connected in star 26.In the present embodiment, this grid structure comprises the grid oxic horizon 21 being formed on substrate 20, the grid 22 on grid oxic horizon 21.The formation method of sigma connected in star 26 also can be with reference to existing other technique.
This sigma connected in star 26, its shape and existing sigma connected in star approach, and also have flute tips 261, and this flute tips 261 is comprised of upper surface 2611, lower surface 2612.
Then, execution step S12, does not fill up sigma connected in star 26 to interior filling the first silicon germanium material layer 271, the first silicon germanium material layer 271 of sigma connected in star 26.
The content of the germanium of the first silicon germanium material layer 271 is lower, can play and prevent that the interface of silicon in silicon germanium material that follow-up formation Ge content is higher and substrate 20 from causing larger lattice mismatch, avoids causing the latter's growth result poor.Be understandable that, this first silicon germanium material layer 271 has played cushioning effect, thereby also claims resilient coating.Based on this, if adopt chemical formula Si
1-xge
xthe material that represents the first silicon germanium material layer 271, the scope of x is 5 ~ 30%, in other words, the atomicity percentage of the germanium of resilient coating 271 is 5 ~ 30%.The function of the first silicon germanium material layer 271 based on buffering, the blocked up electron mobility that easily causes of its thickness is improved poor effect, its thickness is excessively thin is difficult to the lattice mismatch issue of avoiding large, the inventor finds, when these resilient coating 271 thickness ranges are 2 ~ 5nm, can avoid the above-mentioned blocked up raw problem of small property of crossing.
After this step executes, the structural section schematic diagram of formation as shown in Figure 6.
Then, execution step S13, shown in Fig. 7, removes the first silicon germanium material layer 271 of the segment thickness of sigma connected in star 26 bottoms.
Defect analysis based on above-mentioned prior art, in this step, about the preferred plan of the removal amount of the segment thickness of groove 26 bottoms is: after realizing resilient coating 271 and filling, the remaining space of sigma connected in star 26 still keeps the shape of former sigma connected in star 26.But nonetheless, remove the resilient coating 271 of the segment thickness of groove 26 bottoms, still can improve the shape that resilient coating 271 is filled the remaining space of rear sigma connected in star 26, make it approach the shape of former sigma connected in star 26.
In the present embodiment, for achieving the above object, it is to process realization by alkaline solution that this step is removed the segment thickness of the resilient coating 271 of groove 26 bottoms.Alkaline solution has the removal speed of 100 crystallographic systems of silicon germanium material is greater than to the character to the removal speed of 111 crystallographic systems.The plane of the bottom of this 100 crystallographic system respective slot 26, the corresponding plane separately that forms upper surface 2611 with the lower surface 2612 of flute tips 261 of 111 crystallographic systems.
During concrete enforcement, this alkaline solution can be selected multiple, and such as TMAH solution (tetramethyl ammonium hydroxide solution), KOH solution, ammoniacal liquor etc., but object based on not introducing impurity, preferably adopt TMAH solution and ammoniacal liquor.
No matter adopt which kind of alkaline solution, processing time length can cause the difference of removal amount, and the inventor finds that 5 ~ 100s can realize the blocked up amount that resilient coating 271 thickness ranges are the groove 26 bottoms appearance of 2 ~ 5nm generation.In addition, the inventor also finds in above-mentioned alkaline solution processing procedure, the temperature of processing also can have minor impact to removal amount, but be non-linear relation with removal amount, the removal of the blocked up amount that groove 26 bottoms that are 2 ~ 5nm generation to resilient coating 271 thickness ranges based on realization occur, temperature range is 20 ~ 100 ℃ and can meets the demands.For example, adopt 70.9 ℃, mass percent is 34% KOH solution, in the same processing time, removal thickness to 100 crystallographic systems (respective slot bottom) is 0.629 μ m, removal thickness to 111 crystallographic systems (corresponding upper and lower surface 2611,2612) is 0.009 μ m, and both remove speed ratio and are approximately 151:1.Adopt 79.8 ℃, mass percent is 20% TMAH solution, in the same processing time, removal thickness to 100 crystallographic systems (respective slot bottom) is 0.603 μ m, removal thickness to 111 crystallographic systems (corresponding upper and lower surface 2611,2612) is 0.017 μ m, and both remove speed ratio and are approximately 68:1.
In the present embodiment, after this step executes, as shown in Figure 7, the new resilient coating of formation adopts 271 ' to indicate to the structural section schematic diagram of formation.
Afterwards, execution step S14, as shown in Figure 8, stops to filling up to interior filling the second silicon germanium material layer 272 of sigma connected in star 26, and the content of the germanium of the second silicon germanium material layer 272 is higher than the content of the germanium of the first silicon germanium material layer 271.
In this step, the object of this second silicon germanium material layer 272 is that groove 26 and each border of substrate 20 are applied to compression, be understandable that, and the effect that applies compression that this second silicon germanium material layer 272 has mainly played, thereby also claim packed layer.Based on this, if adopt chemical formula Si
1-yge
ythe material that represents the second silicon germanium material layer 272, the scope of y is 20 ~ 60%, in other words, the atomicity percentage of the germanium of packed layer 272 is 20 ~ 60%; Preferably, the scope of y is 40 ~ 60%, and the atomicity percentage of the germanium of packed layer 272 is 40 ~ 60%.The function of the second silicon germanium material layer 272 based on mainly applying compression, its thickness range is 3 ~ 10nm preferably.
After above-mentioned steps completes, as shown in Figure 8, sigma connected in star 26 has been filled.Then,, according to the needs in 24Yu drain region, source region 25, in the silicon germanium material of sigma connected in star 26 interior fillings, carry out P type Implantation.
Embodiment bis-
PMOS transistor that the present embodiment two provides and preparation method thereof is roughly identical with embodiment mono-.Difference is that the P type Implantation in 24Yu drain region, source region 25 is different opportunity.Be mainly reflected in following 2 points.
1) in step S12 implementation, the final part-structure that forms 24He drain region, source region 25 of this resilient coating 271, thereby, in order to form PMOS transistor, this step, when forming the step of resilient coating 271, can also adopt in-situ doped formation P trap, and this is in-situ doped is limit depositing silicon germanium material, limit doping, has avoided 24Ji drain region, source region 25 after formation, to carry out this doping way of Implantation P type element easily in the interior generation defect in 24Ji drain region, this source region 25.
Particularly, this P type element can be boron, inventor's discovery, and its dopant dose is such as but not limited to 0.1 ~ 5E20/cm
3time, can meet the transistorized performance of PMOS.
2) in step S14 implementation, this packed layer 272 has finally also formed the part-structure in 24He drain region, source region 25, thereby, in order to form PMOS transistor, this step, when forming the step of packed layer 272, can also adopt in-situ doped formation P trap, and this is in-situ doped is limit depositing silicon germanium material, limit doping, has avoided 24Ji drain region, source region 25 after formation, to carry out this doping way of Implantation P type element easily in the interior generation defect in 24Ji drain region, this source region 25.
Particularly, this P type element can be boron, inventor's discovery, and its dopant dose is such as but not limited to 0.1 ~ 5E20/cm
3time, can meet the transistorized performance of PMOS.
Embodiment tri-
PMOS transistor that the present embodiment three provides and preparation method thereof is roughly identical with embodiment mono-.Difference is, as shown in Figure 9, step S13 is to interior filling the second silicon germanium material layer 272 of sigma connected in star 26 to after filling up and stopping executing, also on substrate 20 surfaces between adjacent side wall 23, form the content of germanium of the 3rd silicon germanium material layer 273, the three silicon germanium material layer 273 lower than the content of the germanium of the second silicon germanium material layer 272.The 3rd silicon germanium material layer 273 object are formed in 24Ji drain region, source region 25, but at least need to cover the second silicon germanium material layer 272.
The PMOS transistor of making in embodiment mono-, two, in some cases, after on 24Yu drain region, its source region 25, extended meeting forms metal interconnect structure (such as conductive plunger etc.) and is electrically connected to realize with other device, in order to reduce the contact resistance between 24Yu drain region 25, this source region and the conductive plunger of metal interconnect structure, can utilize silication technique for metal to form metal silicide at the 3rd silicon germanium material layer 273, to reduce contact resistance.
Based on above-mentioned purpose, the 3rd silicon germanium material layer 273 also claims cap layer, if adopt chemical formula Si
1-zge
zthe material that represents the 3rd silicon germanium material layer 273, the scope of z is for being less than 30%, and in other words, the atomicity percentage of the germanium of cap layer 273 is that the atomicity percentage in it is less than 30%.
It should be noted that, because metal silicide is in forming process, may not use the 3rd layer of silicon germanium material layer 273 of full depth completely, the 3rd layer of silicon germanium material layer 273 also may have segment thickness to act as formation 24Yu drain region, source region 25, thereby preferably the 3rd layer of silicon germanium material layer 273 carried out to P type ion doping, this dopant species is preferably identical with kind and the concentration of resilient coating 271, packed layer 272 with concentration.In addition, the inventor finds to be also conducive to the stable of metal silicide after doping.The doping of the 3rd layer of silicon germanium material layer 273 opportunity can be identical with embodiment mono-, also can adopt growth limit, the limit doped scheme of embodiment bis-.
Each embodiment in this specification all adopts the mode of going forward one by one to describe, between each embodiment identical similar part mutually referring to, what each example stressed is the difference routine with other.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (19)
1. the transistorized manufacture method of PMOS, is characterized in that, comprising:
Substrate is provided, and in described substrate, the predetermined region that forms source region and drain region is formed with sigma connected in star;
In described sigma connected in star, fill the first silicon germanium material layer, described the first silicon germanium material layer does not fill up described sigma connected in star;
Remove the first silicon germanium material layer of the segment thickness of described sigma connected in star bottom;
To filling the second silicon germanium material layer in described sigma connected in star, to filling up, stop, the content of the germanium of described the second silicon germanium material layer is higher than the content of the germanium of described the first silicon germanium material layer.
2. method according to claim 1, is characterized in that, removes the first silicon germanium material layer of the segment thickness of described sigma connected in star bottom and processes realization by alkaline solution.
3. method according to claim 2, is characterized in that, described alkaline solution is TMAH solution or ammoniacal liquor.
4. method according to claim 2, is characterized in that, the temperature of described processing is 20 ~ 100 ℃, and the processing time is 5 ~ 100s.
5. method according to claim 1, is characterized in that, to the atomicity percentage of the germanium of the first silicon germanium material layer of filling in described sigma connected in star, is 5 ~ 30%.
6. method according to claim 1, is characterized in that, when filling the first silicon germanium material layer in described sigma connected in star, carries out in-situ doped P type element.
7. method according to claim 6, is characterized in that, described P type element is boron, and dopant dose is 0.1 ~ 5E20/cm
3.
8. method according to claim 1, is characterized in that, to the thickness of the first silicon germanium material layer of filling in described sigma connected in star, is 2 ~ 5nm.
9. method according to claim 1, is characterized in that, to the atomicity percentage of the germanium of the second silicon germanium material layer of filling in described sigma connected in star, is 20 ~ 60%.
10. method according to claim 1, is characterized in that, when filling the second silicon germanium material layer in described sigma connected in star, carries out in-situ doped P type element.
11. methods according to claim 10, is characterized in that, described P type element is boron, and dopant dose is 0.1 ~ 5E20/cm
3.
12. methods according to claim 1, is characterized in that, to the thickness of the second silicon germanium material layer of filling in described sigma connected in star, are 3 ~ 10nm.
13. methods according to claim 1, it is characterized in that, to filling the second silicon germanium material layer in described sigma connected in star to after filling up and stopping, also on described the second silicon germanium material layer, form the 3rd silicon germanium material layer, the content of the germanium of described the 3rd silicon germanium material layer is lower than the content of the germanium of described the second silicon germanium material layer.
14. methods according to claim 13, is characterized in that, the atomicity percentage of the germanium of the 3rd silicon germanium material layer of formation is less than 30%.
15. methods according to claim 13, is characterized in that, while forming the 3rd silicon germanium material layer, carry out in-situ doped P type element.
16. methods according to claim 15, is characterized in that, described P type element is boron, and dopant dose is 0.1 ~ 5E20/cm
3.
17. methods according to claim 13, is characterized in that, the thickness of the 3rd silicon germanium material layer of formation is less than 5nm.
18. methods according to claim 1, it is characterized in that, the formation method of described sigma connected in star is: on described substrate, form grid structure, in described grid structure both sides, form side wall, take described grid structure and side wall as mask, and in described substrate, the predetermined region that forms source region and drain region forms sigma connected in star.
19. 1 kinds of PMOS transistors of making according to the method described in any one in the claims 1 to 18.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210312944.3A CN103632975B (en) | 2012-08-29 | 2012-08-29 | PMOS transistor and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210312944.3A CN103632975B (en) | 2012-08-29 | 2012-08-29 | PMOS transistor and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103632975A true CN103632975A (en) | 2014-03-12 |
| CN103632975B CN103632975B (en) | 2017-03-29 |
Family
ID=50213873
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210312944.3A Active CN103632975B (en) | 2012-08-29 | 2012-08-29 | PMOS transistor and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103632975B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104392996A (en) * | 2014-11-26 | 2015-03-04 | 上海华力微电子有限公司 | Intercalated germanium-silicon device and preparation method thereof |
| CN105097437A (en) * | 2014-05-22 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Method for forming strain silicon layer, manufacturing method for PMOS device and semiconductor device |
| CN105206530A (en) * | 2014-06-27 | 2015-12-30 | 中芯国际集成电路制造(上海)有限公司 | Formation method of PMOS transistor |
| CN105336776A (en) * | 2014-07-09 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | PMOS (P-channel metal oxide semiconductor) transistor and forming method thereof |
| CN109524306A (en) * | 2017-09-18 | 2019-03-26 | 中芯国际集成电路制造(上海)有限公司 | The forming method of transistor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101087002A (en) * | 2006-06-09 | 2007-12-12 | 国际商业机器公司 | Semiconductor structure with stressor channel and its forming method |
| US20090108308A1 (en) * | 2007-10-31 | 2009-04-30 | Jusung Engineering Co., Ltd | Transistor and method of fabricating the same |
| US20110117732A1 (en) * | 2009-11-17 | 2011-05-19 | Asm America, Inc. | Cyclical epitaxial deposition and etch |
| CN102610637A (en) * | 2011-01-19 | 2012-07-25 | 台湾积体电路制造股份有限公司 | Method of manufacturing strained source/drain structures |
-
2012
- 2012-08-29 CN CN201210312944.3A patent/CN103632975B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101087002A (en) * | 2006-06-09 | 2007-12-12 | 国际商业机器公司 | Semiconductor structure with stressor channel and its forming method |
| US20090108308A1 (en) * | 2007-10-31 | 2009-04-30 | Jusung Engineering Co., Ltd | Transistor and method of fabricating the same |
| CN101425534A (en) * | 2007-10-31 | 2009-05-06 | 周星工程股份有限公司 | Transistor and method of fabricating the same |
| US20110117732A1 (en) * | 2009-11-17 | 2011-05-19 | Asm America, Inc. | Cyclical epitaxial deposition and etch |
| CN102610637A (en) * | 2011-01-19 | 2012-07-25 | 台湾积体电路制造股份有限公司 | Method of manufacturing strained source/drain structures |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105097437A (en) * | 2014-05-22 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Method for forming strain silicon layer, manufacturing method for PMOS device and semiconductor device |
| CN105206530A (en) * | 2014-06-27 | 2015-12-30 | 中芯国际集成电路制造(上海)有限公司 | Formation method of PMOS transistor |
| CN105336776A (en) * | 2014-07-09 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | PMOS (P-channel metal oxide semiconductor) transistor and forming method thereof |
| CN104392996A (en) * | 2014-11-26 | 2015-03-04 | 上海华力微电子有限公司 | Intercalated germanium-silicon device and preparation method thereof |
| CN109524306A (en) * | 2017-09-18 | 2019-03-26 | 中芯国际集成电路制造(上海)有限公司 | The forming method of transistor |
| CN109524306B (en) * | 2017-09-18 | 2022-03-25 | 中芯国际集成电路制造(上海)有限公司 | Method for forming transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103632975B (en) | 2017-03-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101632488B1 (en) | Mos devices having epitaxy regions with reduced facets | |
| CN104377199B (en) | It is embedded in the germanium block piece in MOS device | |
| CN104217953A (en) | PMOS (P-channel metal oxide semiconductor) transistor and manufacture method thereof | |
| CN104347688B (en) | Adjust the germanium percentage in MOS device | |
| CN103632975A (en) | Pmos transistor and manufacturing method thereof | |
| US8476169B2 (en) | Method of making strained silicon channel semiconductor structure | |
| KR101522792B1 (en) | Source and drain stressors with recessed top surfaces | |
| CN103383962B (en) | Semiconductor structure and manufacture method thereof | |
| US8431460B2 (en) | Method for fabricating semiconductor device | |
| CN104733389B (en) | The forming method of transistor | |
| CN103515430A (en) | Fin field effect transistor and manufacturing method thereof | |
| CN105529265A (en) | MOS transistor and MOS transistor manufacturing method | |
| CN104241355B (en) | Semiconductor devices and forming method thereof | |
| CN103779218B (en) | Semiconductor devices and its manufacture method | |
| CN105632928A (en) | MOS transistor forming method | |
| CN105448723A (en) | Semiconductor device and forming method thereof | |
| CN104752352A (en) | Semiconductor device and manufacture method thereof | |
| KR102174333B1 (en) | Dram selector element and manufacturing method thereof | |
| CN103681345B (en) | Transistor and forming method thereof | |
| CN105448982A (en) | MOS transistor and manufacturing method therefor | |
| CN102412306B (en) | Trench gate junction field effect transistor and manufacturing method thereof | |
| CN104425379A (en) | Forming method of semiconductor device | |
| CN104217956A (en) | PMOS (P-channel metal oxide semiconductor) transistor and manufacture method thereof | |
| CN102969247B (en) | Semiconductor structure and forming method thereof, transistor and transistor forming method | |
| CN106257646B (en) | It is embedded in the CMOS production method of PIP capacitor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |