CN103617992A

CN103617992A - Lead frame capacitor and capacitive coupling isolator circuit

Info

Publication number: CN103617992A
Application number: CN201310615922.9A
Authority: CN
Inventors: 不公告发明人
Original assignee: Suzhou Baker Microelectronics Co Ltd
Current assignee: Suzhou Baker Microelectronics Co Ltd
Priority date: 2013-11-27
Filing date: 2013-11-27
Publication date: 2014-03-05

Abstract

The invention discloses a lead frame capacitor and a capacitive coupling isolator circuit. The lead frame capacitor comprises a first electrode and a second electrode, wherein the first electrode and the second electrode are formed in a part of a lead frame structure which is used for traditional integrated circuit package, the electrodes are packaged with insulation model materials, and the insulation model materials provide insulation nodes between the electrodes. The invention further provides the low-power capacitive coupling digital isolator circuit. A pair of the lead frame capacitors is adopted by the low-power capacitive coupling digital isolator circuit. The low-power capacitive coupling digital isolator circuit comprises a differential actuator and a receiving circuit. A receiver comprises a selectable filter which can filter out noise and obstacles.

Description

A kind of lead frame capacitor and capacitive coupling isolator circuit

Technical field:

The present invention relates to electric capacity and capacity coupled isolator circuit, in integrated antenna package, be used to provide ground reference potential isolation.

Background technology:

Isolator is commonly used to signal coupling to have between the circuit of Different Ground reference potential.In some cases, can there be difference on ground separately under the current potential up to several kilovolts.In general, there are three methods that isolation is provided between the circuit with Different Ground reference potential: photoelectron coupling isolation, transformer coupled isolation, capacitive coupling isolation.Photoelectron coupling and the technological deficiency of transformer coupled isolation are that the device that is coupled is all relative huge and can not well in integrated circuit, use.Less also can being integrated on a semiconductor dies that electric capacity can be done on the other hand.

Yet past trial provides a capacity coupled buffer circuit to run into a difficult problem on single semiconductor dies, as the constraint of reliability, from infringement and the overvoltage collapse of static discharge.Particularly, it has been found to be difficult to provide take the capacitor that silicon dioxide is substrate and can bear high pressure difference, and this problem runs in the buffer circuit of being everlasting.

Another solution had previously been described, and at one, formed isolating capacitor, the input and output level that this capacitor comprises buffer circuit between two semiconductor dies on being configured in by the ceramic substrate of the integrated antenna package of plastic seal.Yet such mixed structure requires isolating capacitor to be manufactured in advance on independent substrate except plastic packets.

In view of above-mentioned, the electric capacity that can bear high pressure difference should be provided, can realize like this in the situation that do not have extra substrate in integrated antenna package as an isolation capacitance.

Also need to provide one and can in single integrated encapsulation, obtain the isolation capacitance of manufacturing.

Summary of the invention:

The object of this invention is to provide the electric capacity that can bear high pressure difference, can realize like this in the situation that do not have extra substrate in integrated antenna package as an isolation capacitance.

Another object of the present invention is to provide one can obtain the isolation capacitance of manufacturing in single integrated encapsulation.

Technical solution of the present invention:

According to these objects of the present invention and other objects, an electric capacity should be provided, this electric capacity comprises and is formed at the electrode that adapts to the part be used in the lead frame structure in traditional integrated circuit, and it adopts traditional integrated circuit packaging material as the node material of electric capacity.

A buffer circuit is also provided, and wherein the capacitor of a pair of above-mentioned lead frame is all to provide isolation between the circuit for having each self-reference ground at two.This buffer circuit is provided in single integrated circuit encapsulation, utilizes the assembling of traditional integrated circuit and the packing technique can be manufactured.

This buffer circuit comprises a low-power digital buffer circuit, and having one, in traditional integrated circuit (IC) design, to be coupling in differential receiver be transmitter.Selectable noise filter in this digital isolator circuit can be used for preventing from breaking down at output.In addition, external oscillator can be for being arranged to data output and external clock synchronously.

Contrast patent documentation: CN202087927U chip tantalum capacitance group installation 201120157070.X

Accompanying drawing explanation:

Above-mentioned purpose of the present invention and other objects will show more obviously in description below and figure, in these figure:

Fig. 1 is one, and the electric capacity that shows of simplification is provided is the schematic diagram of making in conjunction with criterion of the present invention;

Fig. 2 A is an incomplete perspective view, and this figure has represented the lead frame capacitor for forming in conjunction with criterion of the present invention;

Fig. 2 B is the cutaway view of Fig. 2 A lead frame;

Fig. 3 is the perspective view that Fig. 2 A-B encloses semiconductor and electric wire;

Fig. 4 A is that Fig. 3 is at the imperfect perspective view that carries out the lead frame of insulating material encapsulation;

Fig. 4 B is the cutaway view of Fig. 4 A;

Fig. 5 be buffer circuit according to criterion of the present invention the theory diagram in conjunction with pair of lead frames electric capacity;

Fig. 6 is according to the detailed block diagram of the low-power digital isolator circuit of criterion construction of the present invention;

Fig. 7 has represented the various signal waveforms of above-mentioned Fig. 6 numeral buffer circuit;

Fig. 8 is the plane graph of the lead frame of Fig. 6 low-power digital buffer circuit.

Embodiment:

Fig. 1 is one, and the electric capacity that shows of simplification is provided is the schematic diagram of making in conjunction with criterion of the present invention.Electric capacity 10 comprise be embedded into but be insulated the

electrode

12 and 14 that medium 16 separates.Electrode 12 and 14 is to be all formed at a part that is used in the lead frame structure in traditional integrated circuit configuration.Dielectric material 16 is to be made by the cast material for encapsulating in traditional integrated circuit Plastic Package.In a typical isolator circuit application,

electrode

12 and 14 is electrically connected to the wire bonding by traditional on the difference integrated circuit that is operated in Different Ground reference potential.

Fig. 2-4 illustrate has in all its bearings embodied capacitor 10.Fig. 2 A is an incomplete perspective view, and this figure has represented according to principle of the present invention provides an electric capacity by lead frame structure 30.As shown in Figure 2 A, lead frame structure 30 comprises

capacitance electrode

12 and 14 and chip soldering fishplate bar 32 and 42.Electrode 14 comprises

electrode strip

14A and 14B, these parallel both sides that are placed on independent electrode strip 12 of two electrode strips.When connecting

electrode

12,14 and pad, 30A plays temporary supporting effect.Lead frame structure 30,

electrode

12 and 14 and pad 32 and 34 can also make (as punching press or corrosion) by traditional manufacturing process.

Once be encapsulated in plastic encapsulant,

electrode

12 and 14 will form a coplanar and cross capacitance, and wherein fringe field provides electric capacity between

electrode strip

12 and 14A and 14B.A factor that determines the electric capacity of capacitor 10 is two distances between pole plate.As shown in Figure 2 B, Fig. 2 B has shown the cutaway view of lead frame structure to this distance, and

electrode strip

14A and 14B are separated by distance " ES " by electrode 12.This distance " ES " is relevant with the size shape of electric capacity 10 with other physical quantitys, and when change 30 obtains different capacitances and meet specific size restrictions tradition integrated antenna package, these variablees are easy to controlled.

Fig. 3 is the perspective view that Fig. 2 A-B encloses semiconductor and electric wire.As shown in Figure 3, semiconductor chip 34 and 44 is linked respectively on pad 32 and 42.According to traditional integrated antenna package technology, an epoxy can be used for providing conductive attachment between chip and pad.Semiconductor chip 34 and 44 comprises pad 36 and 46 separately.With bonding wire 38, respectively semiconductor chip 34,44 and

electrode

12,14 are welded.Therefore,, after encapsulation and eliminate supporting 30A, semiconductor chip 34 and 44 will be by together with

electrode

12,14 capacitive coupling.Will discuss below, electrode edge length is " FL " (see and be marked on " FL " on dotted line) as shown in Figure 3, contributes to like this to determine the capacitance of lead frame capacitor.

Fig. 4 A is that Fig. 3 is at the imperfect perspective view (passing through jet molding method) that carries out the lead frame of insulating material 40 encapsulation.Fig. 4 B is the cutaway view of Fig. 3 lead frame.According to the present invention, as Fig. 4 A and 4B,

electrode

12 and 14 is encapsulated by insulating material 40 completely.

If Fig. 4 A is after encapsulation, lead frame supports 30A and is excluded by dotted line 30B.

Therefore, Fig. 2-4 have illustrated the structure of lead frame capacitor of the present invention, and wherein electrode is coplanar intersection.In this structure, the capacitor being formed by electrode is commonly called " fringe capacitor ", by fringe field, provides electric capacity.Obviously, the capacitance of electric capacity 10 is determined by the distance between two-plate " ES ", pole plate length " FL " and dielectric dielectric constant.

The length of pole plate " FL " is the same with distance " ES " between pole plate to be easy to control and to obtain different capacitances.As everyone knows, such as increasing " FL " and dielectric constant, can increase capacitance, and the distance increasing between pole plate can make capacitance reduce.

Said use electrode shape in Fig. 2-4, the scope that can be easy to accomplish lead frame capacitance in the dual inline type bag (a long 6mm of the about 23mm of bag is wide) of 18 lead-in wire plastics of a tradition is at least from about 0.1 farad to 0.2 farad.Certainly, the shape of capacitor plate rather than as in Figure 2-4 those can form according to the present invention.

The puncture voltage of lead frame electric capacity of the present invention is to be determined by the distance between pole plate " ES " and dielectric constant.Such as the distance increasing between pole plate, puncture voltage can increase (although capacitance can reduce).In addition,, along with the increase of breakdown strength, puncture voltage also can increase thereupon.

With traditional material, the present invention can be used for realizing isolation voltage over 1000 volts.For example, one is novolac epoxy resin for the conventional plastic material that encapsulates.Novolaks are a kind of thermoplasticity water soluble phenol resins.For polar plate spacing, be approximately the electric capacity (making of above-mentioned material) of 0.5mm, puncture voltage is over 100 volts.

Lead frame structure 30 is made by conventional lead frame frame material.Such as, the about 0.245mm of a kind of iron-nickel alloy is thick successfully to be used, although other materials can be used.Equally, although electrode material of the present invention can be a kind of traditional design material (dielectric constant that novolac epoxy resin serves as medium is approximately 4) being used on integrated antenna package, other materials also can be used.Preferably such material just has high puncture voltage, high-k and low-loss.

Fig. 2-4 explanation, can be according to the following steps in order to manufacture lead frame capacitor of the present invention.Capacitor plate is that first is made with blaster fuse frame material.Next with the electrical equipment that method is produced between pole plate and integrated circuit in succession that goes between, connect.Finally, between pole plate, with dielectric, encapsulate.

A characteristic of lead frame electric capacity of the present invention is that above-mentioned each step is to carry out during traditional integrated circuit is manufactured.Therefore, lead frame electric capacity of the present invention is not having additional configuration and encapsulation to make an integrated circuit with small amount cost.

Fig. 5 be buffer circuit according to criterion of the present invention the theory diagram in conjunction with pair of lead frames electric capacity.Buffer circuit 50 comprises that circuit 62(has 62A, 62B and tri-ports of 63C), circuit 64(has 64A, 64B and tri-ports of 64C).Circuit 50 also comprises the

lead frame capacitor

52 and 54 that is insulated

material package.Port

62A and 64A are coupled by electric capacity 52, and

port

62B and 64B are to provide, electric capacity 54 is coupled.

Port

62C and 64C are connected in respectively on the ground that reference potential is GND1 and GND2.

Circuit

62 and 64 has all kinds.Such as, circuit 62 can make a drive circuit be used for producing the signal of telecommunication.Circuit 64 can be receiving circuit, is used for receiving such signal.The characteristic of this part of the present invention is that the GND1 of driver 62 can be different with the GND2 of receiving circuit 64.Therefore, such circuit can provide isolation in circuit separately.

Second example,

circuit

62 and 64 each can be transceiver circuit, can transmit the signal of telecommunication of self-

capacitance

52 and 54 also can receive such signal.According to such structure, the GND1 of transceiver 62 can be different with the GND2 of transceiver 64.

Circuit

62 and 64 as shown in Figure 5 also comprises

port

63 and 65, and this circuit that is used for being coupled respectively (does not show) to another circuit.According to the present invention, no matter circuit 62 is a reflector, transceiver or other circuit typess, and input signal (such as being provided by RS232 bus or light-operated switch) can be provided port 63 provides a serial bit stream to be coupled on circuit 64 through

electric capacity

52 and 54 by circuit 62 codings subsequently.The serial bit stream of circuit 64 decodings provides an output signal through

electric capacity

52 and 54 at port 65.Another kind, port 63 can replace to receive parallel input signal by a plurality of terminals.These parallel signal terminals can be used to provide operating power to circuit 62.Equally, port 65 also can substitute to provide parallel output signal by a plurality of terminals.

Fig. 6 is according to the detailed block diagram of the low-power digital isolator circuit 100 of criterion construction of the present invention.Fig. 7 has shown the various signal waveforms of Fig. 6 numeral buffer circuit.

According to the present invention, buffer circuit 100 can utilize manufacturing process manufacture in single integrated bag.

Buffer circuit 100 comprises can be in the situation that do not need extra input power to obtain the reflector 110 of power from single TTL digital input end.110 reference ground is GND1.Buffer circuit also comprises receiver 120, can provide corresponding TTL digital output signal to carry out track digital input signal, but 120 reference ground is GND2.Separation is provided by pair of lead frames electric capacity (105 and 115), and these two electric capacity and reflector 110 and receiver 120 are shared a lead frame structure.Isolation surpasses 1000 volts can obtain higher bit stream and low-power consumption.The working method of buffer circuit 100 is as follows.

Reflector 110 comprises thresholding oscillator 112 and driver 114,116.For induced current, by numeral, input 118 and offer thresholding oscillator 112 and driver 114,116.When numeral input (DIN) 118 surpasses predetermined voltage (3 volts), the square wave (4HZ) that a fixed frequency was opened and provided to thresholding oscillator 112 is inputted 114A and 116A respectively to driver 114 and 116 by driving.Driver 114 and 116

output

114B and 116B are anti-phase under the fixed frequency of same thresholding oscillator 112.(waveform 118,114B and 116B have as shown in Figure 7 represented respectively the output waveform of Fig. 6 middle port 118,114B and 116.）

If necessary, thresholding oscillator 112 can comprise that Schmidt trigger (not showing) prevents oscillator drives

electric capacity

105 and 115, until DIN rises to sufficiently high level, provides one not have noisy square wave to driving 114 and 116.

Driver 114 and 116 is coupled from the fixed frequency square-wave signal of thresholding oscillator 112 by lead frame

electric capacity

105 and 115, and forms differential signals at the

input

131 and 132 of comparator 130.(

waveform

131 and 132 has as shown in Figure 7 represented respectively comparator in Fig. 6 and inputted 131 and 132 output waveform) comparator 130 is hysteresis comparators, prevents from changing input/output state until have difference on 131 and 132 voltages.

Comparator output terminal 133 is high level, as long as the output 114B of driver 114 is that high level and DIN are high level.When DIN is high level, the voltage (waveform that compares 144B and 133 in Fig. 7) of the output 114B of driver 114 is followed in comparator output 133.

133 are used for driving the input 134A of monostable circuit 134.The state changing in order to respond comparator output 133, monostable output 134B becomes high level by TTL buffer 135.(

waveform

133 and 135A have as shown in Figure 7 represented respectively the output waveform of Fig. 6

middle port

133 and 135A.) time constant of monostable circuit 134 is configured to a plurality of oscillator cycle of oscillation.So output signal 135A will keep high level the same with cycle of oscillation long.When numeral input, DIN becomes low level, and the thresholding oscillator 112 of reflector 110 can cut out and monostable output signal 135A can be reset as low level.

Therefore, monostable output signal 135A is the same with the current potential of DIN substantially, no matter whether GND1 is the same with GND2.Lead frame

electric capacity

105 and 115 provides an isolation barrier in 100 li, circuit.

In order to avoid noise and glitch, receiver to add an optional filter 136 in circuit 100.Filter 136 is binary counters, can by external oscillator, input 148 by internal oscillator 140 and external oscillator and be coupled on buffer circuit 100.Clock detector circuit 145 is internal oscillator 140 decoupling be coupled on external oscillator (respectively by switch 146 and 147) from filter 136, such as, externally continuous three pulses in oscillator input 148.

The frequency of internal oscillator 140 preferably and the frequency of the thresholding oscillator of reflector 110 match (although not being synchronous).For numeral, export DOUT138A(by TTL buffer 138) become high level, filter 136 must be counted predetermined quantity when monostable circuit output 134B keeps high level.Equally, for numeral, export DOUT138A(by TTL buffer 138) become low level, filter 136 must be counted predetermined quantity when monostable circuit output 134B keeps low level.As shown in Figure 7, after 4 clock cycle, how 138A is low level (shadow region among waveform 138A is because oscillator 112 does not have to keep synchronous with the concussion input 136A of filter 136) from hypermutation to the waveform of DOUT138A.

If necessary, external oscillator be coupled to outside concussion input 148 can be for synchronously exporting with external clock.

Therefore, filter 136 tails off the noise of buffer circuit and fault.As the example that can reduce noise and fault, low level while supposing numeral input DIN, thresholding oscillator 112 cuts out, and has the normal mode signal of a rapid growth on the DIN on ground GND1110A with about receiver 120 ground GND2.Anyly lead frame

electric capacity

105 and 115 li, unmatchedly will on the input at comparator 130 131 and 132, general signal be converted to difference fault.

The output 133 of comparator 130 will trigger and the output 134B of monostable circuit 134 can become high level accordingly.Yet, filter 136 will only can be counted the number (because the signal of rapid growth is assumed to produce a corresponding difference fault on comparator 130 on GND1 and DIN) in first clock cycle before monostable circuit 134 is reset, so data output 138A will keep low level.As long as the monostable time constant of period ratio of general signal is large, filter 136 just can work.

The another one function of digital buffer circuit is as shown in Figure 6 can manufacture it by traditional manufacturing process.Lead frame capacitor provides circuit isolation, in the situation that do not have too high increase production cost can be incorporated to integrated circuit.Fig. 8 is the plane graph of the lead frame of Fig. 6 low-power digital buffer circuit.

The size of 18 lead-in wire DIP of the size of lead frame 150 and tradition encapsulation (approximately the long 6mm of 23mm is wide) is corresponding, except it only has 10 (there be not 5, limit) lead-in wire, to lead frame electric capacity, provides space.

As shown in Figure 8, reflector 110 is made on report note chip.Equally, receiver 120 is made on report note chip 152.Lead frame 150 also comprises interlaced

finger

156A, 156B and 157, is used for forming lead frame electric capacity 105, and interlaced

finger

166A, 166B and 167 are used for forming electric capacity 115.Lead frame 150 is also included in whole buffer circuit with the region 165 that can remove after insulating material sealing so that 170 electrically isolated from one.150 also comprise lockhole 160 to allow insulating material can firmly hold 170 during user processes.

Preferably,

lead frame finger

156A, 156B, 157,166A, 166B and 167 distance " EW " between each is approximately 0.5mm.For the lead frame structure shown in Fig. 8,

electric capacity

105 and 115 capacitance are approximately all 1pf, and this electric capacity is used dielectric constant to be approximately 4 material to serve as medium.

Therefore, the most handy capacitor cheaply of this circuit is in conjunction with traditional integrated antenna package.Use traditional insulating material, circuit is exported to the isolation voltage of TTL digital signal generation up to 100 volts from being input to.Input circuit is low to moderate 60 to 600 microamperes, can be used for respectively processing the signal up to 20 to 200kps.

Although the present invention embodies by concrete example, above-mentioned example just should not limit the present invention for the present invention is described.It should be pointed out that as long as no departing from essence of the present invention and meeting the definition in claim, on above-mentioned example, make suitable modification and still belong to category of the present invention.

Claims

1. lead frame capacitor and a capacitive coupling isolator circuit, is characterized in that: an isolator comprises: first circuit that is connected to first ground; Be connected to second circuit on second ground; Therebetween, the electrode that these capacitors have is formed at lead frame structure to the isolator that one or more capacitor-coupled provide band coupling between first circuit and second circuit.

2. a kind of lead frame capacitor according to claim 1 and capacitive coupling isolator circuit, it is characterized in that: wherein one or more lead frame capacitors comprise: first being separated by a region and second capacitor, above-mentioned first and second part that comprises blaster fuse frame material; Above-mentioned zone is insulating material.

3. a kind of lead frame capacitor according to claim 2 and capacitive coupling isolator circuit, is characterized in that: first and second electrode are coplanar substantially; First and second electrode intersect; First electrode comprises first and second finger, and the 3rd finger that above-mentioned second electrode comprises is between first and second finger; One and second electrode are formed at an individual layer of blaster fuse frame material.

4. a kind of lead frame capacitor according to claim 3 and capacitive coupling isolator circuit, is characterized in that: first in integrated antenna package and second circuit are placed on lead frame.

5. a kind of lead frame capacitor according to claim 3 and capacitive coupling isolator circuit, is characterized in that: during drive circuit, difference channel comprises an oscillator that can produce signal, and wherein receiving circuit is also difference channel; Receiver comprises a comparator, thereby is used for driving monostable circuit to produce a continuous signal; Wherein drive circuit comprises that a plurality of inputs are brought in and receives parallel input signal, and this input is commonly used to provide operating power to drive circuit; Wherein receiving circuit comprises that a plurality of output is brought in provides parallel output signal.

6. a kind of lead frame capacitor according to claim 5 and capacitive coupling isolator circuit, is characterized in that: first and second circuit all comprise transceiver circuit.