CN103617319A - Method for directly extracting small-signal model parameters of III-V group MOSFET (metal-oxide-semiconductor field effect transistor) - Google Patents

Abstract

The invention discloses a method for directly extracting small-signal model parameters of a III-V group MOSFET (metal-oxide-semiconductor field effect transistor), belonging to the technical field of microelectronic integrated circuits. According to the method, de-embedding is carried out through a bonding pad and a metal interconnection line, proper bias conditions during extraction of parasitic resistance of a transistor are determined by using direct current transfer characteristics and cold state S parameters of the transistor, then channel resistance influence is removed under the bias conditions, parasitic resistance parameters are extracted through linear fitting, the parasitic resistance is finally de-embedded, and intrinsic parameters are extracted through a small signal model equivalent circuit and curve fitting of a III-V group MOSFET. The small signal parameter direct extraction process provided by the invention completely accords with the physical significance of devices, provides a necessary basis for the application of integrated circuit technology, and has a good reference function for extracting small signal model parameters of other types of devices such as new materials, new structures and the like.

Description

A Direct Extraction Method of Small Signal Model Parameters of III-V MOSFET

technical field

The present invention relates to the technical field of microelectronic integrated circuits, in particular to a method for directly extracting small-signal model parameters of III-V MOSFETs, which can be used to effectively extract small-signal parameter results of III-V MOSFET type devices for use in device technology Optimization and circuit simulation design.

Background technique

At the 11nm technology node and beyond, due to the limitations of the physical properties of silicon materials, silicon-based CMOS technology will face enormous challenges, and high-mobility "non-silicon" materials will be gradually introduced into CMOS technology. III-V compound semiconductor materials have the advantages of high electron mobility, short intrinsic delay time, good radio frequency performance, small gate leakage, low static power consumption, etc., and have become a research hotspot in the current international MOSFET technology. Accurate extraction of small-signal model parameters is of great significance for guiding process steps, detecting process accuracy, improving device structure, studying the influence of process parameters on high-frequency performance of devices, and integrated circuit applications. Therefore, the study of III-V MOSFET small-signal The model has good research value and practical value.

The small-signal model can reflect the physical structure characteristics of the device and the high-frequency characteristics at a specific bias point, which has important guiding significance for the reproduction and extrapolation of the high-frequency small-signal performance of the device, and the accuracy of the model parameter extraction directly It is related to the accuracy of the small signal model. Gilles Dambrine et al. described in detail the direct extraction method of GaAs HEMT small signal model parameters in the literature "A new method for determining the FET small signal equivalent circuit" (IEEE Transaction on Microwave Theory and Techniques, July 1988), in which the parasitic resistance parameter The extraction is that the device is in a cold state, fully consider the channel resistance under the gate and the equivalent impedance of the Schottky barrier, and use the Z parameter fitting results under three different gate current conditions as an additional relationship condition to obtain the parasitic resistance parameter, However, for MOSFET structure devices, due to the insulation of the oxide layer under the gate, such a method is no longer applicable; the intrinsic parameters are calculated by the analytical method to obtain the functional relationship of the intrinsic parameters with respect to frequency, and then the parameters are obtained in the frequency flat region value, the results obtained in this way will have certain deviations when fitting in certain frequency regions.

In addition, in the literature "AlN-GaN MOS-HEMTs with thermally grown Al2O3 passivation" (IEEE Transaction on Electron Devices, May 2011), Sanna Taking et al. extracted the parasitic parameters of the MOS-HEMT structure device, and the source/drain parasitic resistance passed the TLM test and the device The geometric size is calculated, and the parasitic resistance of the gate is calculated by the resistivity and size parameters of the gate metal. The disadvantage of this method is that the theoretical contribution of the resistance is considered separately in the process of extracting the parameters, and the possible parasitic resistance during the device manufacturing process is ignored. Changes that occur; the overall optimization is performed after extracting the intrinsic parameters to eliminate the randomness of the process, and then the optimized parameter results may deviate from the physical meaning of the device itself.

Contents of the invention

(1) Technical problems to be solved

In order to accurately extract the parasitic resistance and intrinsic parameters of the III-V MOSFET device, the invention provides a method for directly extracting small signal model parameters suitable for the III-V MOSFET structure.

(2) Technical solutions

In order to achieve the above object, the present invention provides a method for directly extracting small-signal model parameters of III-V MOSFETs. The method is to de-embed through pads and metal interconnection lines, and use transistor DC transfer characteristics and cold-state S parameters to determine the extraction method. Appropriate bias conditions for the parasitic resistance of the transistor, and then remove the influence of the channel resistance under this bias condition, linear fitting to extract the parasitic resistance parameters, and finally de-embed the parasitic resistance, using the equivalent circuit of the small signal model of the III-V MOSFET and curve fitting to extract the intrinsic parameters.

In the above scheme, the method specifically includes the following steps: Step 1: Use the on-chip structure to de-embed the parasitic parameters introduced by the test pad and the metal interconnection; Step 2: According to the DC transfer characteristics of the transistor, the small-signal equivalent of the cold-state transistor The cold state S parameters of the circuit and different gate voltages determine the appropriate bias conditions for the transistor when extracting the parasitic resistance; Step 3: Under the above bias conditions, remove the influence of the channel resistance and extract the parasitic resistance parameters; Step 4: De-embedding The parasitic resistance is used to obtain the intrinsic Y parameters of the transistor; Step 5: Extract the intrinsic parameters according to the analytical formula and curve fitting of the small-signal model equivalent circuit of the III-V MOSFET.

In the above scheme, the small-signal model equivalent circuit of the described III-V MOSFET includes five resistors, three capacitors and a voltage-controlled current source, wherein: the gate resistance (R _g ) is related to the contact material of the oxide layer on the gate , is composed of the distributed loss effect of the gate metal; the source/drain resistance (R _s , R _d ) is composed of two parts: the metal-semiconductor contact resistance and the semiconductor body resistance; the gate-source capacitance (C _gs ) and the gate-drain capacitance (C _gd ) The table pointer corresponds to the discharge and charging process of the area, which includes the edge effect between the gate and the source/drain, the grid-to-drain resistance (R _gs ) and the non-quasi-state effect of the grid-to-drain capacitance charging and discharging process; the channel resistance (R _ds ) It comes from the fact that the drain-source current does not really saturate with the drain voltage. C _ds represents the capacitive effect between the source and drain under electrostatic conditions; the intrinsic transconductance (g _m ) represents the modulation or control ability of the gate voltage on the channel current, and the parameter τ refers to time delay factor.

In the above solution, the small-signal equivalent circuit of the cold-state transistor described in step 2 includes four resistors and three capacitors, and the cold state refers to the bias state in which the device is in a source-drain without voltage drop, that is, V _ds =0V; under cold state conditions, the channel current of the transistor is negligible, and it is approximately considered that the gate voltage has no ability to modulate or control the channel. The small signal equivalent circuit of the cold state transistor is the same as that of the non-cold state transistor. The difference is that there is no voltage-controlled current source part, and the corresponding Z parameter can be written as the following expression:

${\mathrm{<span\; class="notranslate">\; <figure-callout\; id="11"\; label="Zc"\; filenames="HDA0000423066960000031.png,HDA0000423066960000041.png"\; state="\{\{state\}\}">Zc</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 11</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; ds</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; j\&omega;</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; ds</span>}}<span\; class="notranslate">\; )</span>}{<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; Yc</span>}<span\; class="notranslate">\; |</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}$

${\mathrm{<span\; class="notranslate">\; <figure-callout\; id="12"\; label="Zc"\; filenames="HDA0000423066960000022.png,HDA0000423066960000023.png"\; state="\{\{state\}\}">Zc</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 12</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; j\&omega;</span>}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}}{<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; Yc</span>}<span\; class="notranslate">\; |</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}$

${\mathrm{<span\; class="notranslate">\; Zc</span>}}_{\mathrm{<span\; class="notranslate">\; twenty\; one</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; j\&omega;</span>}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}}{<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; Yc</span>}<span\; class="notranslate">\; |</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}$

${\mathrm{<span\; class="notranslate">\; Zc</span>}}_{\mathrm{<span\; class="notranslate">\; twenty\; two</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; j\&omega;</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gs</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}<span\; class="notranslate">\; )</span>}{<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; Yc</span>}<span\; class="notranslate">\; |</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; d</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}$

Among them: the Zc parameter represents the Z parameter matrix of the cold state transistor, and the Yc parameter represents the Y parameter matrix of the cold state transistor

g _ds =1/R _ds ; |Yc|=jωg _ds (C _gs +C _gd )−ω ² (C _gs C _gd +C _gs C _ds +C _gd C _ds ).

In the above scheme, determining the appropriate bias condition of the transistor when extracting the parasitic resistance described in step 2 includes the following steps:

Step 21: Under a certain drain voltage bias condition, scan the gate voltage to obtain the DC transfer characteristics, and obtain the threshold voltage V _th by using the linear region extrapolation method;

Step 22: Under cold condition V _ds = 0V, scan with frequency as the first variable and gate voltage as the second variable, the range of gate voltage can be V _th -2V<V _gs <V _th +0.5V, and get A set of cold-state S-parameter results under different grid voltages;

Step 23: According to the cold-state S-parameter results, de-embed the parasitic parameters introduced by the test pads and metal interconnection lines, and then convert them into Y parameters to obtain a set of real part results of Yc ₂₂ under different gate voltages. When the frequency is low enough, the intrinsic capacitance and channel resistance show a large impedance value. At this time, the influence of the parasitic resistance on the Y parameter can be ignored, and it is obtained:

其中：|Zc|＝Zc₁₁·Zc₂₂-Zc₁₂·Zc₂₁

Where: |Zc|＝Zc ₁₁ ·Zc ₂₂ -Zc ₁₂ ·Zc ₂₁

Record the value of the real part of Yc ₂₂ at the low frequency Freq=1GHz, and draw the relationship curve of the real part of Yc ₂₂ with respect to the gate voltage. The larger the gate voltage is, the channel resistance becomes smaller due to the modulation of the gate voltage. In this way, the cold state Z parameter is used The error of extracting the parasitic resistance becomes larger, so the area below the gate voltage where the real part of Yc ₂₂ begins to rise is the appropriate bias area for extracting the parasitic resistance of the transistor, and the gate voltage value when the real part of Yc ₂₂ begins to rise is determined to be Vh;

Step 24: Obtain the bias conditions for extracting the parasitic resistance of the transistor as follows: V _ds =0V and V _gs =Vh-Vo, where Vo represents the introduced engineering margin.

In the above scheme, the extraction of parasitic resistance parameters described in step 3 includes the following steps:

Step 31: According to the obtained bias conditions for extracting the parasitic resistance of the transistor, use the S parameters under the bias conditions to de-embed the parasitic parameters introduced by the test pad and metal interconnection lines, and then convert them into Y parameters, and use the S parameters of the Y parameters The imaginary part extracts C _gs , C _gd , and C _ds of the cold transistor, and the real part of Yc ₂₂ low frequency is used to extract g _ds . The specific fitting formula is as follows:

a)-imag((Yc ₁₂ +Yc ₂₁ )/2)=ω×C _gd

b) imag(Yc ₁₁ )-ω·C _gd =ω×C _gs

c)imag(Yc ₂₂ )-ω·C _gd =ω×C _ds

d)real(Yc22)·ω＝ω×gds| _ω→0

Step 32: Remove the influence of the channel resistance on the cold-state Zc parameter, through the following matrix transformation formula:

$\left[\begin{array}{cc}{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="11"\; label="Zr"\; filenames="HDA0000423066960000031.png,HDA0000423066960000041.png"\; state="\{\{state\}\}">Zr</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 11</span>}}& {\mathrm{<span\; class="notranslate">\; <figure-callout\; id="12"\; label="Zr"\; filenames="HDA0000423066960000022.png,HDA0000423066960000023.png"\; state="\{\{state\}\}">Zr</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 12</span>}}\\ {\mathrm{<span\; class="notranslate">\; Zr</span>}}_{\mathrm{<span\; class="notranslate">\; twenty\; one</span>}}& {\mathrm{<span\; class="notranslate">\; Zr</span>}}_{\mathrm{<span\; class="notranslate">\; twenty\; two</span>}}\end{array}\right]<span\; class="notranslate">\; =</span>\left[\begin{array}{cc}{\mathrm{<span\; class="notranslate">\; Zc</span>}}_{\mathrm{<span\; class="notranslate">\; 11</span>}}<span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; ds</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; j\&omega;</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; ds</span>}}<span\; class="notranslate">\; )</span>}{<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; Yc</span>}<span\; class="notranslate">\; |</span>}& {\mathrm{<span\; class="notranslate">\; Zc</span>}}_{\mathrm{<span\; class="notranslate">\; 12</span>}}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; j\&omega;</span>}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}}{<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; Yc</span>}<span\; class="notranslate">\; |</span>}\\ {\mathrm{<span\; class="notranslate">\; Zc</span>}}_{\mathrm{<span\; class="notranslate">\; twenty\; one</span>}}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; j\&omega;</span>}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}}{<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; Yc</span>}<span\; class="notranslate">\; |</span>}& {\mathrm{<span\; class="notranslate">\; Zc</span>}}_{\mathrm{<span\; class="notranslate">\; twenty\; two</span>}}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; j\&omega;</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gs</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}<span\; class="notranslate">\; )</span>}{<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; Yc</span>}<span\; class="notranslate">\; |</span>}\end{array}\right]$

Among them: the Zr parameter represents the Z parameter matrix after removing the channel resistance.

Step 33: Use the real part of the Zr parameter to linearly fit to obtain the value of the parasitic resistance. The specific fitting formula is as follows:

a)real((Zr ₁₂ +Zr ₂₁ )/2)·ω ² =ω ² ×R _s

b)real(Zr ₁₁ )·ω ² =ω ² ×(R _g +R _s )

c)real(Zr ₂₂ )·ω ² =ω ² ×(R _d +R _s )

In the above scheme, de-embedding the parasitic resistance described in step 4 to obtain the intrinsic Y parameter of the transistor is realized by the following matrix transformation formula:

$\left[\begin{array}{cc}{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="11"\; label="Zin"\; filenames="HDA0000423066960000031.png,HDA0000423066960000041.png"\; state="\{\{state\}\}">Zin</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 11</span>}}& {\mathrm{<span\; class="notranslate">\; <figure-callout\; id="12"\; label="Zin"\; filenames="HDA0000423066960000022.png,HDA0000423066960000023.png"\; state="\{\{state\}\}">Zin</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 12</span>}}\\ {\mathrm{<span\; class="notranslate">\; Zin</span>}}_{\mathrm{<span\; class="notranslate">\; twenty\; one</span>}}& {\mathrm{<span\; class="notranslate">\; Zin</span>}}_{\mathrm{<span\; class="notranslate">\; twenty\; two</span>}}\end{array}\right]<span\; class="notranslate">\; =</span>\left[\begin{array}{cc}{\mathrm{<span\; class="notranslate">\; Zr</span>}}_{\mathrm{<span\; class="notranslate">\; 11</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}& {\mathrm{<span\; class="notranslate">\; Zr</span>}}_{\mathrm{<span\; class="notranslate">\; 12</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}\\ {\mathrm{<span\; class="notranslate">\; Zr</span>}}_{\mathrm{<span\; class="notranslate">\; twenty\; one</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}& {\mathrm{<span\; class="notranslate">\; Zr</span>}}_{\mathrm{<span\; class="notranslate">\; twenty\; two</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; d</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}\end{array}\right]$

Where: the Zin parameter represents the intrinsic Z parameter matrix after de-embedding the parasitic resistance.

In the above scheme, the extraction of the intrinsic parameters according to the analytical formula and curve fitting of the small-signal model equivalent circuit of the III-V MOSFET described in step 5 is based on the Y parameter analytical formula of the intrinsic π-type network, including The specific fitting formula is as follows:

a)-imag(Yin ₁₂ )=ω×C _gd

$\mathrm{<span\; class="notranslate">\; b</span>}<span\; class="notranslate">\; )</span>\frac{\mathrm{<span\; class="notranslate">\; imag</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="11"\; label="Yin"\; filenames="HDA0000423066960000031.png,HDA0000423066960000041.png"\; state="\{\{state\}\}">Yin</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 11</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; Yin</span>}}_{\mathrm{<span\; class="notranslate">\; 12</span>}}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; real</span>}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="11"\; label="Yin"\; filenames="HDA0000423066960000031.png,HDA0000423066960000041.png"\; state="\{\{state\}\}">Yin</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 11</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; Yin</span>}}_{\mathrm{<span\; class="notranslate">\; 12</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; imag</span>}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="11"\; label="Yin"\; filenames="HDA0000423066960000031.png,HDA0000423066960000041.png"\; state="\{\{state\}\}">Yin</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 11</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; Yin</span>}}_{\mathrm{<span\; class="notranslate">\; 12</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; \&omega;</span>}<span\; class="notranslate">\; \&times;</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gs</span>}}$

$\mathrm{<span\; class="notranslate">\; c</span>}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; real</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="11"\; label="Yin"\; filenames="HDA0000423066960000031.png,HDA0000423066960000041.png"\; state="\{\{state\}\}">Yin</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 11</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; Yin</span>}}_{\mathrm{<span\; class="notranslate">\; 12</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; \&omega;</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="C\; gs"\; filenames="HDA0000423066960000023.png"\; state="\{\{state\}\}">C</figure-callout></span><figure-callout\; id="2"\; label="C\; gs"\; filenames="HDA0000423066960000023.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}^{\mathrm{<span\; class="notranslate">gs</span>}}<span\; class="notranslate">\; \&times;</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; gs</span>}}$

d)(Yin ₂₁ -Yin ₁₂ )·(1+j·ω·C _gs ·R _gs )＝g _m ×e ^-j·ω·τ

e)imag(Yin ₂₂ +Yin ₁₂ )＝ω×C _ds

f)real(Yin ₂₂ +Yin ₁₂ )·ω＝ω×1/R _ds

Among them: the Yin parameter represents the intrinsic Y parameter matrix after de-embedding the parasitic resistance;

The gate-to-drain capacitance C _gd is obtained by fitting the linear relationship between the imaginary part of Yin ₁₂ (imag(Yin ₁₂ )) and the angular velocity (ω); it is extracted according to the linear relationship between the real part of Yin ₁₁ + Yin ₁₂ and ω ² ×C _gs ² The gate-source resistance R _gs , extract the gate-source capacitance C _gs according to the linear relationship between Yin ₁₁ + Yin ₁₂ virtual real part and ω; then obtain the transconductance g _m and time delay by optimizing the nonlinear relationship between Yin ₂₁ -Yin ₁₂ and ω factor τ; finally, use Yin ₂₂ +Yin ₁₂ and the linear relationship between the real part and imaginary part and ω to fit and extract the channel resistance R _ds and the drain-source capacitance C _ds .

(3) Beneficial effects

Compared with the prior art, the above-mentioned technical solution has the following advantages:

1) Starting from the physical level of the device, the equivalent topological structure of the small signal model is established, and a direct parameter extraction method suitable for III-V MOSFET type devices is proposed, which provides new materials and new structure devices for small signal modeling and parameter extraction. appropriate reference;

2) Based on the DC transfer characteristics, through the research of the output Y parameters, the method of extracting the appropriate bias point of the transistor when the parasitic resistance is obtained, avoiding the error introduced by blindly selecting the cold state bias condition;

3) When extracting parasitic resistance parameters, the influence of channel resistance is removed, and the accuracy of parasitic resistance parameter results is improved, thereby improving the reliability of intrinsic parameters;

4) Use the idea of curve fitting to directly fit the Y parameter to obtain a more accurate parameter value. Compared with the method of analytical calculation in the prior art, the above-mentioned technical solution can obtain the determined intrinsic parameter value instead of the same as In addition, this extraction method does not need to be optimized again, so that the obtained parameter values are more in line with the physical meaning of the device itself.

Description of drawings

1 is a schematic diagram of a III-V MOSFET device structure and a small signal model according to an embodiment of the present invention;

2 is a flow chart of direct extraction of parameters of a III-V MOSFET small-signal model according to an embodiment of the present invention;

3 is an equivalent circuit of a III-V MOSFET device in a cold state according to an embodiment of the present invention;

Fig. 4a is a curve of the real part of Yc ₂₂ with respect to frequency under different gate voltages according to an embodiment of the present invention;

Fig. 4b is the relationship curve of the real part of Yc ₂₂ at a low frequency of 1 GHz with respect to grid voltage according to an embodiment of the present invention;

FIG. 5 is a fitting effect of extracting parasitic resistance parameters under cold conditions according to an embodiment of the present invention;

Fig. 6a is a fitting effect diagram of the real part of the intrinsic Y parameter of a transistor according to an embodiment of the present invention;

Fig. 6b is a fitting effect diagram of the imaginary part of the intrinsic Y parameter of a transistor according to an embodiment of the present invention;

7a and 7b are S-parameter fitting effect diagrams of transistors according to embodiments of the present invention, wherein the smooth solid line represents the equivalent circuit simulation results.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

The method for directly extracting small-signal model parameters of this III-V family MOSFET provided by the present invention is to de-embed through pads and metal interconnection lines, and use transistor DC transfer characteristics and cold-state S parameters to determine the appropriate bias when extracting transistor parasitic resistance. Under this bias condition, the influence of the channel resistance is removed, the parasitic resistance parameters are extracted by linear fitting, and finally the parasitic resistance is de-embedded, and the small-signal model equivalent circuit and curve fitting of the III-V MOSFET are used to extract the characteristic parameters, the method specifically includes the following steps:

Step 1: Use the on-chip structure to de-embed the parasitic parameters introduced by the test pad and metal interconnection lines;

Step 2: According to the DC transfer characteristics of the transistor, the small-signal equivalent circuit of the cold-state transistor, and the cold-state S-parameters of different gate voltages, determine the appropriate bias conditions for the transistor when extracting the parasitic resistance;

Step 3: Under the above bias conditions, remove the influence of channel resistance and extract parasitic resistance parameters;

Step 4: De-embed the parasitic resistance to obtain the intrinsic Y parameter of the transistor;

Step 5: Extract the intrinsic parameters according to the analytical formula and curve fitting of the small-signal model equivalent circuit of the III-V MOSFET.

Wherein, the small-signal model equivalent circuit of the described III-V family MOSFET includes five resistors, three capacitors and a voltage-controlled current source, wherein: the gate resistance (R _g ) is related to the contact material of the oxide layer on the gate, and is determined by The distribution loss effect of the gate metal; the source/drain resistance (R _s , R _d ) is composed of two parts: the metal-semiconductor contact resistance and the semiconductor body resistance; the gate-source capacitance (C _gs ) and the gate-drain capacitance (C _gd ) are for The discharge and charge process of the response area, which includes the edge effect between the gate and the source/drain, the gate-to-drain resistance (R _gs ) indicates the non-quasi-state effect of the gate-to-drain capacitance charge and discharge process; the channel resistance (R _ds ) comes from The drain-source current does not really saturate with the drain voltage, C _ds represents the capacitive effect between the source and drain under electrostatic conditions; the intrinsic transconductance (g _m ) represents the modulation or control ability of the gate voltage on the channel current, and the parameter τ refers to the time delay factor.

The small-signal equivalent circuit of the cold-state transistor described in step 2 includes four resistors and three capacitors. The cold state refers to the device being in a biased state with no source-drain voltage drop, that is, V _ds =0V; Under cold state conditions, the channel current of the transistor can be ignored, and it is approximately considered that the gate voltage has no ability to modulate or control the channel. The difference between the small-signal equivalent circuit of a cold-state transistor and the non-cold-state transistor is that there is no The voltage controlled current source part, the corresponding Z parameter can be written as the following expression:

${\mathrm{<span\; class="notranslate">\; <figure-callout\; id="11"\; label="Zc"\; filenames="HDA0000423066960000031.png,HDA0000423066960000041.png"\; state="\{\{state\}\}">Zc</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 11</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; ds</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; j\&omega;</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; ds</span>}}<span\; class="notranslate">\; )</span>}{<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; Yc</span>}<span\; class="notranslate">\; |</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}$

${\mathrm{<span\; class="notranslate">\; <figure-callout\; id="12"\; label="Zc"\; filenames="HDA0000423066960000022.png,HDA0000423066960000023.png"\; state="\{\{state\}\}">Zc</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 12</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; j\&omega;</span>}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}}{<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; Yc</span>}<span\; class="notranslate">\; |</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}$

${\mathrm{<span\; class="notranslate">\; Zc</span>}}_{\mathrm{<span\; class="notranslate">\; twenty\; one</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; j\&omega;</span>}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}}{<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; Yc</span>}<span\; class="notranslate">\; |</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}$

${\mathrm{<span\; class="notranslate">\; Zc</span>}}_{\mathrm{<span\; class="notranslate">\; twenty\; two</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; j\&omega;</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gs</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}<span\; class="notranslate">\; )</span>}{<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; Yc</span>}<span\; class="notranslate">\; |</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; d</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}$

Among them: the Zc parameter represents the Z parameter matrix of the cold state transistor, and the Yc parameter represents the Y parameter matrix of the cold state transistor

g _ds =1/R _ds ; |Yc|=jωg _ds (C _gs +C _gd )−ω ² (C _gs C _gd +C _gs C _ds +C _gd C _ds ).

Determining suitable biasing conditions for transistors when extracting parasitic resistances as described in Step 2 includes the following steps:

Step 21: Under a certain drain voltage bias condition, scan the gate voltage to obtain the DC transfer characteristics, and obtain the threshold voltage V _th by using the linear region extrapolation method;

Step 22: Under cold condition V _ds = 0V, scan with frequency as the first variable and gate voltage as the second variable, the range of gate voltage can be V _th -2V<V _gs <V _th +0.5V, and get A group of cold-state S parameter results under different grid voltages; as shown in Figure 3, Figure 3 is the equivalent circuit of the III-V group MOSFET device of the present invention under cold-state conditions;

Step 23: According to the cold-state S-parameter results, de-embed the parasitic parameters introduced by the test pads and metal interconnection lines, and then convert them into Y parameters to obtain a set of real part results of Yc ₂₂ under different gate voltages. When the frequency is low enough, the intrinsic capacitance and channel resistance show a large impedance value. At this time, the influence of the parasitic resistance on the Y parameter can be ignored, and it is obtained:

其中：|Zc|＝Zc₁₁·Zc₂₂-Zc₁₂·Zc₂₁

Where: |Zc|＝Zc ₁₁ ·Zc ₂₂ -Zc ₁₂ ·Zc ₂₁

Record the value of the real part of Yc ₂₂ at the low frequency Freq=1GHz, and draw the relationship curve of the real part of Yc ₂₂ with respect to the gate voltage. The larger the gate voltage is, the channel resistance becomes smaller due to the modulation of the gate voltage. In this way, the cold state Z parameter is used The error of extracting the parasitic resistance becomes larger, so the area below the gate voltage where the real part of Yc ₂₂ begins to rise is the appropriate bias area for extracting the parasitic resistance of the transistor, and the gate voltage value when the real part of Yc ₂₂ begins to rise is determined to be Vh;

Step 24: Obtain the bias conditions for extracting the parasitic resistance of the transistor as follows: V _ds =0V and V _gs =Vh-Vo, where Vo represents the introduced engineering margin.

The extraction of parasitic resistance parameters described in step 3 includes the following steps:

Step 31: According to the obtained bias conditions for extracting the parasitic resistance of the transistor, use the S parameters under the bias conditions to de-embed the parasitic parameters introduced by the test pad and metal interconnection lines, and then convert them into Y parameters, and use the S parameters of the Y parameters The imaginary part extracts C _gs , C _gd , and C _ds of the cold transistor, and the real part of Yc ₂₂ low frequency is used to extract g _ds . The specific fitting formula is as follows:

a)-imag((Yc ₁₂ +Yc ₂₁ )/2)=ω×C _gd

b) imag(Yc ₁₁ )-ω·C _gd =ω×C _gs

c)imag(Yc ₂₂ )-ω·C _gd =ω×C _ds

d)real(Yc22)·ω＝ω×gds| _ω→0

Step 32: Remove the influence of the channel resistance on the cold-state Zc parameter, through the following matrix transformation formula:

$\left[\begin{array}{cc}{\mathrm{<span\; class="notranslate">\; Zr</span>}}_{\mathrm{<span\; class="notranslate">\; 11</span>}}& {\mathrm{<span\; class="notranslate">\; <figure-callout\; id="12"\; label="Zr"\; filenames="HDA0000423066960000022.png,HDA0000423066960000023.png"\; state="\{\{state\}\}">Zr</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 12</span>}}\\ {\mathrm{<span\; class="notranslate">\; Zr</span>}}_{\mathrm{<span\; class="notranslate">\; twenty\; one</span>}}& {\mathrm{<span\; class="notranslate">\; Zr</span>}}_{\mathrm{<span\; class="notranslate">\; twenty\; two</span>}}\end{array}\right]<span\; class="notranslate">\; =</span>\left[\begin{array}{cc}{\mathrm{<span\; class="notranslate">\; Zc</span>}}_{\mathrm{<span\; class="notranslate">\; 11</span>}}<span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; ds</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; j\&omega;</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; ds</span>}}<span\; class="notranslate">\; )</span>}{<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; Yc</span>}<span\; class="notranslate">\; |</span>}& {\mathrm{<span\; class="notranslate">\; Zc</span>}}_{\mathrm{<span\; class="notranslate">\; 12</span>}}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; j\&omega;</span>}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}}{<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; Yc</span>}<span\; class="notranslate">\; |</span>}\\ {\mathrm{<span\; class="notranslate">\; Zc</span>}}_{\mathrm{<span\; class="notranslate">\; twenty\; one</span>}}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; j\&omega;</span>}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}}{<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; Yc</span>}<span\; class="notranslate">\; |</span>}& {\mathrm{<span\; class="notranslate">\; Zc</span>}}_{\mathrm{<span\; class="notranslate">\; twenty\; two</span>}}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; j\&omega;</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gs</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}<span\; class="notranslate">\; )</span>}{<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; Yc</span>}<span\; class="notranslate">\; |</span>}\end{array}\right]$

Among them: the Zr parameter represents the Z parameter matrix after removing the channel resistance.

Step 33: Use the real part of the Zr parameter to linearly fit to obtain the value of the parasitic resistance. The specific fitting formula is as follows:

a)real((Zr ₁₂ +Zr ₂₁ )/2)·ω ² =ω ² ×R _s

b)real(Zr ₁₁ )·ω ² =ω ² ×(R _g +R _s )

c)real(Zr ₂₂ )·ω ² =ω ² ×(R _d +R _s )

The de-embedded parasitic resistance described in step 4 to obtain the intrinsic Y parameters of the transistor is realized by the following matrix transformation formula:

$\left[\begin{array}{cc}{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="11"\; label="Zin"\; filenames="HDA0000423066960000031.png,HDA0000423066960000041.png"\; state="\{\{state\}\}">Zin</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 11</span>}}& {\mathrm{<span\; class="notranslate">\; <figure-callout\; id="12"\; label="Zin"\; filenames="HDA0000423066960000022.png,HDA0000423066960000023.png"\; state="\{\{state\}\}">Zin</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 12</span>}}\\ {\mathrm{<span\; class="notranslate">\; Zin</span>}}_{\mathrm{<span\; class="notranslate">\; twenty\; one</span>}}& {\mathrm{<span\; class="notranslate">\; Zin</span>}}_{\mathrm{<span\; class="notranslate">\; twenty\; two</span>}}\end{array}\right]<span\; class="notranslate">\; =</span>\left[\begin{array}{cc}{\mathrm{<span\; class="notranslate">\; Zr</span>}}_{\mathrm{<span\; class="notranslate">\; 11</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}& {\mathrm{<span\; class="notranslate">\; Zr</span>}}_{\mathrm{<span\; class="notranslate">\; 12</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}\\ {\mathrm{<span\; class="notranslate">\; Zr</span>}}_{\mathrm{<span\; class="notranslate">\; twenty\; one</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}& {\mathrm{<span\; class="notranslate">\; Zr</span>}}_{\mathrm{<span\; class="notranslate">\; twenty\; two</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; d</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}\end{array}\right]$

Where: the Zin parameter represents the intrinsic Z parameter matrix after de-embedding the parasitic resistance.

The extraction of intrinsic parameters according to the analytical formula and curve fitting of the small-signal model equivalent circuit of the III-V MOSFET described in step 5 is based on the analytical formula of the Y parameter of the intrinsic π-type network, including the following specific fitting formula:

a)-imag(Yin ₁₂ )=ω×C _gd

$\mathrm{<span\; class="notranslate">\; b</span>}<span\; class="notranslate">\; )</span>\frac{\mathrm{<span\; class="notranslate">\; imag</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="11"\; label="Yin"\; filenames="HDA0000423066960000031.png,HDA0000423066960000041.png"\; state="\{\{state\}\}">Yin</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 11</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; Yin</span>}}_{\mathrm{<span\; class="notranslate">\; 12</span>}}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; real</span>}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="11"\; label="Yin"\; filenames="HDA0000423066960000031.png,HDA0000423066960000041.png"\; state="\{\{state\}\}">Yin</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 11</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; Yin</span>}}_{\mathrm{<span\; class="notranslate">\; 12</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; imag</span>}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="11"\; label="Yin"\; filenames="HDA0000423066960000031.png,HDA0000423066960000041.png"\; state="\{\{state\}\}">Yin</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 11</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; Yin</span>}}_{\mathrm{<span\; class="notranslate">\; 12</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; \&omega;</span>}<span\; class="notranslate">\; \&times;</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gs</span>}}$

$\mathrm{<span\; class="notranslate">\; c</span>}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; real</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="11"\; label="Yin"\; filenames="HDA0000423066960000031.png,HDA0000423066960000041.png"\; state="\{\{state\}\}">Yin</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 11</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; Yin</span>}}_{\mathrm{<span\; class="notranslate">\; 12</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; \&omega;</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="C\; gs"\; filenames="HDA0000423066960000023.png"\; state="\{\{state\}\}">C</figure-callout></span><figure-callout\; id="2"\; label="C\; gs"\; filenames="HDA0000423066960000023.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}^{\mathrm{<span\; class="notranslate">gs</span>}}<span\; class="notranslate">\; \&times;</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; gs</span>}}$

d)(Yin ₂₁ -Yin ₁₂ )·(1+j·ω·C _gs ·R _gs )＝g _m ×e ^-j·ω·τ

e)imag(Yin ₂₂ +Yin ₁₂ )＝ω×C _ds

f)real(Yin ₂₂ +Yin ₁₂ )·ω＝ω×1/R _ds

Among them: the Yin parameter represents the intrinsic Y parameter matrix after de-embedding the parasitic resistance;

The gate-to-drain capacitance C _gd is obtained by fitting the linear relationship between the imaginary part of Yin ₁₂ (imag(Yin ₁₂ )) and the angular velocity (ω); it is extracted according to the linear relationship between the real part of Yin ₁₁ + Yin ₁₂ and ω ² ×C _gs ² The gate-source resistance R _gs , extract the gate-source capacitance C _gs according to the linear relationship between Yin ₁₁ + Yin ₁₂ virtual real part and ω; then obtain the transconductance g _m and time delay by optimizing the nonlinear relationship between Yin ₂₁ -Yin ₁₂ and ω factor τ; finally, use Yin ₂₂ +Yin ₁₂ and the linear relationship between the real part and imaginary part and ω to fit and extract the channel resistance R _ds and the drain-source capacitance C _ds .

Fig. 1 is according to the physical structure and small signal model of InGaAs MOSFET device according to the embodiment of the present invention, material structure comprises: GaAs substrate, AlGaAs buffer layer, InGaAs channel layer, InGaP barrier layer, Al ₂ O ₃ oxide layer, passivation layer, etc., and the following specific examples will illustrate the parameter extraction method of the device with this structure.

Fig. 2 is the direct extraction flowchart of the small signal model parameter of the InGaAs MOSFET device according to the embodiment of the present invention, comprises the following steps:

Step 1: Test the S parameters of the device and the on-chip de-embedding structure, and use the test results to remove the parasitic parameters introduced by the test pads and metal interconnection lines. Accurate extraction of peripheral parasitic parameters will affect the accuracy of internal nonlinear parameters.

Step 2: According to the DC transfer characteristics of the transistor, the small-signal equivalent circuit of the cold-state transistor and the cold-state S-parameter, determine the appropriate bias condition of the transistor when extracting the parasitic resistance;

Test the DC transfer characteristics of the transistor: set the drain voltage to 1V, scan the gate voltage between -1V and 3V to obtain the transfer characteristic curve, and obtain the threshold voltage as 0.5V through linear region extrapolation. Test the cold-state S parameters of the transistor: set the drain voltage to 0V, scan the gate voltage in the range of -2 to 1V with a step size of 0.25V, and at the same time scan the frequency in the range of 1GHz to 40GHz with a step size of 100MHz to obtain a set of different gate voltages. Press down on the cold state S-parameter results. Then de-embed the parasitic parameters introduced by the pads and metal interconnection lines, and then convert them into Y parameters to obtain a set of real part results of Yc ₂₂ under different gate voltages. Finally, the bias condition for extracting the parasitic resistance of the transistor is: V _ds = 0V and V _gs =-0.5V.

Fig. 4a is a curve of the real part of Yc ₂₂ with respect to frequency under different gate voltages according to an embodiment of the present invention, the gate voltage ranges from -0.5V to 0.5V, and the step size is 0.25V. It can be seen that when the gate voltage V _gs =0V, the real part of Yc ₂₂ starts to rise in the whole frequency range. Fig. 4b is the relationship curve of the real part of Yc ₂₂ at a low frequency of 1 GHz with respect to the grid voltage according to an embodiment of the present invention. It is determined that the real part of Yc ₂₂ begins to rise when the grid voltage value is 0V. In the region where the gate voltage is less than 0V, Yc The real part of ₂₂ is small, indicating that the channel resistance is large enough, which has the least influence on the real part of the Y parameter in cold conditions, so it is more accurate to extract parasitic resistance parameters in this region.

Step 3: Under the above bias conditions, remove the influence of channel resistance and extract parasitic resistance parameters;

Fig. 5 is the fitting effect of extracting the parasitic resistance parameter in the cold state condition according to the embodiment of the present invention, wherein the smooth solid line or dotted line represents the cold state equivalent circuit S parameter simulation result, and the scatter graph represents the experimental test data, from the result can be It can be seen that except for some randomness at high frequencies that affects the fitting effect of S parameters, overall, the fitting effect is better in a wider frequency range, and the extracted parasitic resistance parameters meet the requirements. In the cold state of the cut-off region (Vgs=-0.5V, Vds=0V), the extraction results of intrinsic capacitance and channel resistance are: Cds=13fF, Cgd=26.5fF, Cgs=24.6fF, Rds=10K, remove the channel The parasitic resistance parameters obtained after the influence of resistance are: Rs=4.1Ω, Rg=1.34Ω, Rd=7.4Ω.

Step 4: De-embed the parasitic resistance to obtain the intrinsic Y parameter of the transistor;

Step 5: Extract the intrinsic parameters according to the analytical formula of the equivalent circuit of the small signal model and the idea of curve fitting.

Fig. 6a is a fitting effect diagram of the real part of the transistor intrinsic Y parameter according to an embodiment of the present invention, and Fig. 6b is a fitting effect diagram of the imaginary part of the transistor intrinsic Y parameter according to an embodiment of the present invention. Generally speaking, the intrinsic related parameters The method extracted by direct fitting has good reliability and does not need to be re-optimized, so the extracted intrinsic parameter results conform to the physical meaning of the device itself. The extraction results of small signal parameters in the saturation region (Vgs=3V, Vds=2V) are: Cgs=98.2fF, Cgd=20.1fF, Cds=17.7fF, Rgs=1.72Ω, Rds=278.7Ω, gm=53.1mS, tau= 0.1ps.

Fig. 7a and Fig. 7b are the S parameter fitting effect diagrams of the transistor according to the embodiment of the present invention, wherein the smooth solid line represents the simulation result of the equivalent circuit, and the scatter graph represents the experimental test data; wherein the bias condition of the transistor is the gate voltage is 3V, the drain voltage is 2V, the scanning frequency is 1GHz～40GHz, and the step size is 100MHz; it can be seen that the curves of the test and simulation basically overlap, indicating that the equivalent circuit of the present invention reflects the AC characteristics of the InGaAs MOSFET transistor well, so The method for directly extracting parameters of the present invention has good practicability.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (8)

1. The small-signal model parameter direct extraction method of the 1.Yi Zhong III-V MOSFET of family, it is characterized in that, the method is to go embedding by pad and metal interconnection wire, utilize transistor DC transfer characteristics and cold conditions S parameter to determine the suitable bias condition while extracting transistor parasitic resistance, then under this bias condition, remove channel resistance impact, linear fit extracts dead resistance parameter, finally go embedding dead resistance, utilize small-signal model equivalent electrical circuit and the curve of the MOSFET of III-V family to extract intrinsic parameters.
2. 2. the small-signal model parameter direct extraction method of the III-V MOSFET of family according to claim 1, is characterized in that, the method specifically comprises the following steps:

   Step 1: utilize the parasitic parameter that goes embedding testing weld pad and metal interconnection wire to introduce in chip architecture;

   Step 2: according to the cold conditions S parameter of transistorized direct current transfer characteristics, the transistorized small-signal equivalent circuit of cold conditions and different grid voltages, determine transistorized suitable bias condition while extracting dead resistance;

   Step 3: under above-mentioned bias condition, remove the impact of channel resistance, extract dead resistance parameter;

   Step 4: go embedding dead resistance, obtain transistor intrinsic Y parameter;

   Step 5: extract intrinsic parameters according to analytic expression and the curve of the small-signal model equivalent electrical circuit of the MOSFET of III-V family.
3. 3. the small-signal model parameter direct extraction method of the III-V MOSFET of family according to claim 1 and 2, it is characterized in that, the small-signal model equivalent electrical circuit of the described MOSFET of III-V family comprises five resistance, three electric capacity and a voltage-controlled current source, wherein: gate resistance (R _g) relevant with oxide layer contact material on grid, by the distribution losses effect of grid metal, formed; Source/leakage resistance (R _s, R _d) by metal-semiconductor contact resistance and semi-conductive bulk resistor two parts, formed; Grid source electric capacity (C _gs) and gate leakage capacitance (C _gd) the electric discharge charging process of indicator corresponding region, wherein comprised the edge effect between grid and source/leakage, grid leak resistance (R _gs) the non-accurate state effect of indicator gate leakage capacitance charge and discharge process; Channel resistance (R _ds) to derive from drain-source current be not really saturated with leak pressing, C _dsrepresent capacity effect between the static lower source leakage of electricity; Intrinsic transconductance (g _m) representing that grid voltage is to the modulation of channel current or control ability, parameter τ refers to the time delay factor.
4. 4. the small-signal model parameter direct extraction method of the III-V MOSFET of family according to claim 2, it is characterized in that, the transistorized small-signal equivalent circuit of cold conditions described in step 2 comprises four resistance and three electric capacity, described cold conditions refers to that device leaks the bias state without pressure drop, i.e. V in source _ds=0V; Under cold condition, transistorized channel current can be ignored, be similar to and think that grid voltage is not to the modulation of raceway groove or control ability, the difference of the transistorized small-signal equivalent circuit of cold conditions and non-cold conditions transistor small-signal equivalent circuit is not have voltage controlled current source part, and corresponding Z parameter can be write as following expression:

   

   

   

   

   Wherein: the transistorized Z parameter matrix of Zc Parametric Representation cold conditions, the transistorized Y parameter matrix of Yc Parametric Representation cold conditions

   g _ds＝1/R _ds；|Yc|＝jωg _ds(C _gs+C _gd)-ω ²(C _gsC _gd+C _gsC _ds+C _gdC _ds)。
5. 5. the small-signal model parameter direct extraction method of the III-V MOSFET of family according to claim 2, is characterized in that, transistorized suitable bias condition during definite extraction dead resistance described in step 2, comprises the following steps:

   Step 21: press under bias condition certain leakage, scanning grid voltage, obtains direct current transfer characteristics, utilizes linear zone extrapolation method to obtain threshold voltage V _th;

   Step 22: at cold condition V _dsunder=0V, take frequency as the first variable, grid voltage is that the second variable scans, and the scope of grid voltage can be V _th-2V<V _gs<V _th+ 0.5V, obtains cold conditions S parameter result under one group of different grid voltage;

   Step 23: according to cold conditions S parameter result, the parasitic parameter that goes embedding testing weld pad and metal interconnection wire to introduce, is converted to Y parameter afterwards, obtains Yc under one group of different grid voltage ₂₂real part result.When frequency is enough low, intrinsic capacity and channel resistance show very large resistance value, now can ignore the impact of dead resistance on Y parameter, obtain:

   

   wherein: | Zc|=Zc ₁₁zc ₂₂-Zc ₁₂zc ₂₁

   At low frequency Freq=1GHz place, record Yc ₂₂the value of real part, draws Yc ₂₂real part is about the relation curve of grid voltage, and grid voltage is larger, and channel resistance is subject to the modulation of grid voltage and diminishes, and utilizes like this error of cold conditions Z parameter extraction dead resistance to become large, therefore at Yc ₂₂it is the suitable displacement zone of extracting transistor parasitic resistance that the grid voltage that real part starts occur to rise be take lower area, determines Yc ₂₂grid voltage value when real part starts to occur rising is Vh;

   Step 24: the bias condition that obtains extracting transistor parasitic resistance is: V _ds=0V and V _gs=Vh-Vo, the engineering surplus that described Vo representative is introduced.
6. 6. the small-signal model parameter direct extraction method of the III-V MOSFET of family according to claim 2, is characterized in that, the extraction dead resistance parameter described in step 3 comprises the following steps:

   Step 31: the bias condition according to the extraction transistor parasitic resistance arriving, utilize the S parameter under described bias condition, the parasitic parameter that goes embedding testing weld pad and metal interconnection wire to introduce, is converted to Y parameter afterwards, utilizes the imaginary part of Y parameter to extract the transistorized C of cold conditions _gs, C _gd, C _ds, utilize Yc ₂₂the real part result of low frequency is extracted g _ds, concrete fitting formula is as follows:

   a)-imag((Yc ₁₂+Yc ₂₁)/2)＝ω×C _gd

   b)imag(Yc ₁₁)-ω·C _gd＝ω×C _gs

   c)imag(Yc ₂₂)-ω·C _gd＝ω×C _ds

   d)real(Yc22)·ω＝ω×gds| _ω→0

   Step 32: remove channel resistance for the impact of cold conditions Zc parameter, by following matrixing formula:

   

   Wherein: Zr Parametric Representation is removed the Z parameter matrix after channel resistance.

   Step 33: utilize the real part linear fit of Zr parameter to obtain the value of dead resistance, concrete fitting formula is as follows:

   a)real((Zr ₁₂+Zr ₂₁)/2)·ω ²＝ω ²×R _s

   b)real(Zr ₁₁)·ω ²＝ω ²×(R _g+R _s)

   c)real(Zr ₂₂)·ω ²＝ω ²×(R _d+R _s)?。
7. 7. the small-signal model parameter direct extraction method of the III-V MOSFET of family according to claim 2, is characterized in that, described in step 4, goes embedding dead resistance, obtains transistor intrinsic Y parameter, by following matrixing formula, realizes:

   Wherein: Zin Parametric Representation removes the intrinsic Z parameter matrix after embedding dead resistance.
8. 8. the small-signal model parameter direct extraction method of the III-V MOSFET of family according to claim 2, it is characterized in that, analytic expression and curve according to the small-signal model equivalent electrical circuit of the MOSFET of III-V family described in step 5 extract intrinsic parameters, be the Y parameter analytic expression according to intrinsic pin network, comprise following concrete fitting formula:

   a)-imag(Yin ₁₂)＝ω×C _gd

   

   

   d)(Yin ₂₁-Yin ₁₂)·(1+j·ω·C _gs·R _gs)＝g _m×e ^-j·ω·τ

   e)imag(Yin ₂₂+Yin ₁₂)＝ω×C _ds

   f)real(Yin ₂₂+Yin ₁₂)·ω＝ω×1/R _ds

   Wherein: Yin Parametric Representation removes the intrinsic Y parameter matrix after embedding dead resistance;

   Pass through Yin ₁₂imaginary part (imag (Yin ₁₂)) obtain gate leakage capacitance C with the linear relationship matching of angular velocity (ω) _gd; According to Yin ₁₁+ Yin ₁₂real part and ω ²* C _gs ²linear relationship extract grid source resistance R _gs, according to Yin ₁₁+ Yin ₁₂the linear relationship of actual situation portion and ω is extracted grid source capacitor C _gs; Then pass through Yin ₂₁-Yin ₁₂obtain mutual conductance g with the nonlinear relationship Optimal Fitting of ω _mwith time delay factor τ; Finally utilize respectively Yin ₂₂+ Yin ₁₂extract channel resistance R with the linear relationship matching of real part and imaginary part and ω _dswith drain-source capacitor C _ds.

Images