CN103617319A - Method for directly extracting small-signal model parameters of III-V group MOSFET (metal-oxide-semiconductor field effect transistor) - Google Patents
Method for directly extracting small-signal model parameters of III-V group MOSFET (metal-oxide-semiconductor field effect transistor) Download PDFInfo
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Abstract
Description
技术领域technical field
本发明涉及微电子集成电路技术领域,尤其涉及一种III-V族MOSFET的小信号模型参数直接提取方法,可用于有效提取III-V族MOSFET类型器件的小信号参数结果,以用于器件工艺优化和电路仿真设计。The present invention relates to the technical field of microelectronic integrated circuits, in particular to a method for directly extracting small-signal model parameters of III-V MOSFETs, which can be used to effectively extract small-signal parameter results of III-V MOSFET type devices for use in device technology Optimization and circuit simulation design.
背景技术Background technique
在11纳米技术节点及以后,由于硅材料本身的物理特性限制,硅基CMOS技术将面临巨大挑战,高迁移率“非硅”材料将逐步引入到CMOS技术中。III-V族化合物半导体材料具有电子迁移率高,本征延迟时间短,射频性能好,栅的漏电小,静态功耗低等优点,已成为当前国际上MOSFET技术的一个研究热点。小信号模型参数的准确提取对于指导工艺步骤,检测工艺准确性,改善器件结构,研究工艺参数对器件高频性能的影响,集成电路应用等方面具有重要意义,因此研究III-V族MOSFET小信号模型具有很好地研究价值和实用价值。At the 11nm technology node and beyond, due to the limitations of the physical properties of silicon materials, silicon-based CMOS technology will face enormous challenges, and high-mobility "non-silicon" materials will be gradually introduced into CMOS technology. III-V compound semiconductor materials have the advantages of high electron mobility, short intrinsic delay time, good radio frequency performance, small gate leakage, low static power consumption, etc., and have become a research hotspot in the current international MOSFET technology. Accurate extraction of small-signal model parameters is of great significance for guiding process steps, detecting process accuracy, improving device structure, studying the influence of process parameters on high-frequency performance of devices, and integrated circuit applications. Therefore, the study of III-V MOSFET small-signal The model has good research value and practical value.
小信号模型能够反映出器件的物理结构特征和在特定偏置点的高频特性,对于器件高频小信号性能的重现和外推都具有重要的指导意义,而模型参数提取的准确性直接关系到小信号模型的准确性。Gilles Dambrine等人在文献“A new method for determining the FET small signal equivalentcircuit”(IEEE Transaction on Microwave Theory and Techniques,July1988)中对GaAs HEMT的小信号模型参数直接提取方法进行详尽描述,其中寄生电阻参数的提取是器件处于冷态条件,充分考虑栅下沟道电阻和肖特基势垒等效阻抗,利用3组不同的栅电流条件下的Z参数拟合结果作为额外关系条件,得到寄生电阻参数,然而对于MOSFET结构器件,由于栅下氧化层的绝缘性,这样的方法不再适用;其中的本征参数通过解析式方法计算得到本征参数关于频率的函数关系,然后在频率平坦区得到参数的值,这样得到的结果在某些频率区域拟合时会出现一定的偏差。The small-signal model can reflect the physical structure characteristics of the device and the high-frequency characteristics at a specific bias point, which has important guiding significance for the reproduction and extrapolation of the high-frequency small-signal performance of the device, and the accuracy of the model parameter extraction directly It is related to the accuracy of the small signal model. Gilles Dambrine et al. described in detail the direct extraction method of GaAs HEMT small signal model parameters in the literature "A new method for determining the FET small signal equivalent circuit" (IEEE Transaction on Microwave Theory and Techniques, July 1988), in which the parasitic resistance parameter The extraction is that the device is in a cold state, fully consider the channel resistance under the gate and the equivalent impedance of the Schottky barrier, and use the Z parameter fitting results under three different gate current conditions as an additional relationship condition to obtain the parasitic resistance parameter, However, for MOSFET structure devices, due to the insulation of the oxide layer under the gate, such a method is no longer applicable; the intrinsic parameters are calculated by the analytical method to obtain the functional relationship of the intrinsic parameters with respect to frequency, and then the parameters are obtained in the frequency flat region value, the results obtained in this way will have certain deviations when fitting in certain frequency regions.
另外Sanna Taking等人在文献“AlN-GaN MOS-HEMTs with thermallygrown Al2O3 passivation”(IEEE Transaction on Electron Devices,May2011)对于MOS-HEMT结构器件的寄生参数的提取,源/漏寄生电阻通过TLM测试和器件几何尺寸计算得到,栅极寄生电阻通过栅金属的电阻率和尺寸参数计算得到,该方法存在的不足是,提取参数的过程中单独考虑电阻的理论贡献,忽略在器件制作流程过程中寄生电阻可能发生的改变;其中提取本征参数后进行整体优化以消除工艺的随机性,然后优化后的参数结果可能偏离器件本身的物理意义。In addition, in the literature "AlN-GaN MOS-HEMTs with thermally grown Al2O3 passivation" (IEEE Transaction on Electron Devices, May 2011), Sanna Taking et al. extracted the parasitic parameters of the MOS-HEMT structure device, and the source/drain parasitic resistance passed the TLM test and the device The geometric size is calculated, and the parasitic resistance of the gate is calculated by the resistivity and size parameters of the gate metal. The disadvantage of this method is that the theoretical contribution of the resistance is considered separately in the process of extracting the parameters, and the possible parasitic resistance during the device manufacturing process is ignored. Changes that occur; the overall optimization is performed after extracting the intrinsic parameters to eliminate the randomness of the process, and then the optimized parameter results may deviate from the physical meaning of the device itself.
发明内容Contents of the invention
(一)要解决的技术问题(1) Technical problems to be solved
为了准确提取III-V族MOSFET器件的寄生电阻和本征参数,本发明提供了一种适用于III-V族MOSFET结构的小信号模型参数直接提取方法。In order to accurately extract the parasitic resistance and intrinsic parameters of the III-V MOSFET device, the invention provides a method for directly extracting small signal model parameters suitable for the III-V MOSFET structure.
(二)技术方案(2) Technical solutions
为达到上述目的,本发明提供了一种III-V族MOSFET的小信号模型参数直接提取方法,该方法是通过焊盘和金属互联线去嵌,利用晶体管直流转移特性和冷态S参数确定提取晶体管寄生电阻时的合适偏置条件,然后在该偏置条件下去除沟道电阻影响,线性拟合提取寄生电阻参数,最后去嵌寄生电阻,利用III-V族MOSFET的小信号模型等效电路和曲线拟合来提取本征参数。In order to achieve the above object, the present invention provides a method for directly extracting small-signal model parameters of III-V MOSFETs. The method is to de-embed through pads and metal interconnection lines, and use transistor DC transfer characteristics and cold-state S parameters to determine the extraction method. Appropriate bias conditions for the parasitic resistance of the transistor, and then remove the influence of the channel resistance under this bias condition, linear fitting to extract the parasitic resistance parameters, and finally de-embed the parasitic resistance, using the equivalent circuit of the small signal model of the III-V MOSFET and curve fitting to extract the intrinsic parameters.
上述方案中,该方法具体包括以下步骤:步骤1:利用在片结构去嵌测试焊盘和金属互联线引入的寄生参数;步骤2:根据晶体管的直流转移特性、冷态晶体管的小信号等效电路和不同栅压的冷态S参数,确定提取寄生电阻时晶体管的合适偏置条件;步骤3:在上述偏置条件下,去除沟道电阻的影响,提取寄生电阻参数;步骤4:去嵌寄生电阻,得到晶体管本征Y参数;步骤5:根据III-V族MOSFET的小信号模型等效电路的解析式和曲线拟合来提取本征参数。In the above scheme, the method specifically includes the following steps: Step 1: Use the on-chip structure to de-embed the parasitic parameters introduced by the test pad and the metal interconnection; Step 2: According to the DC transfer characteristics of the transistor, the small-signal equivalent of the cold-state transistor The cold state S parameters of the circuit and different gate voltages determine the appropriate bias conditions for the transistor when extracting the parasitic resistance; Step 3: Under the above bias conditions, remove the influence of the channel resistance and extract the parasitic resistance parameters; Step 4: De-embedding The parasitic resistance is used to obtain the intrinsic Y parameters of the transistor; Step 5: Extract the intrinsic parameters according to the analytical formula and curve fitting of the small-signal model equivalent circuit of the III-V MOSFET.
上述方案中,所述的III-V族MOSFET的小信号模型等效电路包括五个电阻、三个电容和一个压控电流源,其中:栅电阻(Rg)与栅上氧化层接触材料有关,由栅金属的分布损耗效应构成;源/漏电阻(Rs,Rd)由金属半导体接触电阻和半导体的体电阻两部分组成;栅源电容(Cgs)和栅漏电容(Cgd)表针对应区域的放电充电过程,其中包含了栅和源/漏之间的边缘效应,栅漏电阻(Rgs)表针栅漏电容充放电过程的非准态效应;沟道电阻(Rds)来源于漏源电流并不是真正随漏压饱和,Cds表示电静态下源漏之间电容效应;本征跨导(gm)代表栅压对沟道电流的调制或者控制能力,参数τ指时间延迟因子。In the above scheme, the small-signal model equivalent circuit of the described III-V MOSFET includes five resistors, three capacitors and a voltage-controlled current source, wherein: the gate resistance (R g ) is related to the contact material of the oxide layer on the gate , is composed of the distributed loss effect of the gate metal; the source/drain resistance (R s , R d ) is composed of two parts: the metal-semiconductor contact resistance and the semiconductor body resistance; the gate-source capacitance (C gs ) and the gate-drain capacitance (C gd ) The table pointer corresponds to the discharge and charging process of the area, which includes the edge effect between the gate and the source/drain, the grid-to-drain resistance (R gs ) and the non-quasi-state effect of the grid-to-drain capacitance charging and discharging process; the channel resistance (R ds ) It comes from the fact that the drain-source current does not really saturate with the drain voltage. C ds represents the capacitive effect between the source and drain under electrostatic conditions; the intrinsic transconductance (g m ) represents the modulation or control ability of the gate voltage on the channel current, and the parameter τ refers to time delay factor.
上述方案中,步骤2中所述的冷态晶体管的小信号等效电路包括四个电阻和三个电容,所述的冷态是指器件处于源漏无压降的偏置状态,即Vds=0V;在冷态条件下,晶体管的沟道电流可忽略,近似认为栅压没有对沟道的调制或者控制能力,冷态晶体管的小信号等效电路与非冷态晶体管小信号等效电路的区别在于没有电压受控电流源部分,对应Z参数可以写成如下表达式:In the above solution, the small-signal equivalent circuit of the cold-state transistor described in
其中:Zc参数表示冷态晶体管的Z参数矩阵,Yc参数表示冷态晶体管的Y参数矩阵Among them: the Zc parameter represents the Z parameter matrix of the cold state transistor, and the Yc parameter represents the Y parameter matrix of the cold state transistor
gds=1/Rds;|Yc|=jωgds(Cgs+Cgd)-ω2(CgsCgd+CgsCds+CgdCds)。g ds =1/R ds ; |Yc|=jωg ds (C gs +C gd )−ω 2 (C gs C gd +C gs C ds +C gd C ds ).
上述方案中,步骤2中所述的确定提取寄生电阻时晶体管的合适偏置条件,包括以下步骤:In the above scheme, determining the appropriate bias condition of the transistor when extracting the parasitic resistance described in
步骤21:在一定漏压偏置条件下,扫描栅压,得到直流转移特性,利用线性区外推法获得阈值电压Vth;Step 21: Under a certain drain voltage bias condition, scan the gate voltage to obtain the DC transfer characteristics, and obtain the threshold voltage V th by using the linear region extrapolation method;
步骤22:在冷态条件Vds=0V下,以频率为第一变量,栅压为第二变量进行扫描,栅压的范围可以是Vth-2V<Vgs<Vth+0.5V,得到一组不同栅压下冷态S参数结果;Step 22: Under cold condition V ds = 0V, scan with frequency as the first variable and gate voltage as the second variable, the range of gate voltage can be V th -2V<V gs <V th +0.5V, and get A set of cold-state S-parameter results under different grid voltages;
步骤23:根据冷态S参数结果,去嵌测试焊盘和金属互联线引入的寄生参数,之后转换为Y参数,得到一组不同栅压下Yc22的实部结果。在频率足够低时,本征电容和沟道电阻表现出很大的阻抗值,此时可以忽略寄生电阻对Y参数的影响,得到:Step 23: According to the cold-state S-parameter results, de-embed the parasitic parameters introduced by the test pads and metal interconnection lines, and then convert them into Y parameters to obtain a set of real part results of Yc 22 under different gate voltages. When the frequency is low enough, the intrinsic capacitance and channel resistance show a large impedance value. At this time, the influence of the parasitic resistance on the Y parameter can be ignored, and it is obtained:
其中:|Zc|=Zc11·Zc22-Zc12·Zc21 Where: |Zc|=Zc 11 ·Zc 22 -Zc 12 ·Zc 21
在低频Freq=1GHz处记录Yc22实部的值,绘制Yc22实部关于栅压的关系曲线,栅极电压越大,沟道电阻受到栅压的调制而变小,这样利用冷态Z参数提取寄生电阻的误差变大,因此在Yc22实部开始出现上升的栅压以下区域为提取晶体管寄生电阻的合适偏置区域,确定Yc22实部开始出现上升时的栅压值为Vh;Record the value of the real part of Yc 22 at the low frequency Freq=1GHz, and draw the relationship curve of the real part of Yc 22 with respect to the gate voltage. The larger the gate voltage is, the channel resistance becomes smaller due to the modulation of the gate voltage. In this way, the cold state Z parameter is used The error of extracting the parasitic resistance becomes larger, so the area below the gate voltage where the real part of Yc 22 begins to rise is the appropriate bias area for extracting the parasitic resistance of the transistor, and the gate voltage value when the real part of Yc 22 begins to rise is determined to be Vh;
步骤24:得到提取晶体管寄生电阻的偏置条件为:Vds=0V和Vgs=Vh-Vo,所述Vo代表引入的工程余量。Step 24: Obtain the bias conditions for extracting the parasitic resistance of the transistor as follows: V ds =0V and V gs =Vh-Vo, where Vo represents the introduced engineering margin.
上述方案中,步骤3中所述的提取寄生电阻参数包括以下步骤:In the above scheme, the extraction of parasitic resistance parameters described in
步骤31:根据到的提取晶体管寄生电阻的偏置条件,利用所述偏置条件下的S参数,去嵌测试焊盘和金属互联线引入的寄生参数,之后转换为Y参数,利用Y参数的虚部提取冷态晶体管的Cgs,Cgd,Cds,利用Yc22低频的实部结果提取gds,具体拟合公式如下:Step 31: According to the obtained bias conditions for extracting the parasitic resistance of the transistor, use the S parameters under the bias conditions to de-embed the parasitic parameters introduced by the test pad and metal interconnection lines, and then convert them into Y parameters, and use the S parameters of the Y parameters The imaginary part extracts C gs , C gd , and C ds of the cold transistor, and the real part of Yc 22 low frequency is used to extract g ds . The specific fitting formula is as follows:
a)-imag((Yc12+Yc21)/2)=ω×Cgd a)-imag((Yc 12 +Yc 21 )/2)=ω×C gd
b)imag(Yc11)-ω·Cgd=ω×Cgs b) imag(Yc 11 )-ω·C gd =ω×C gs
c)imag(Yc22)-ω·Cgd=ω×Cds c)imag(Yc 22 )-ω·C gd =ω×C ds
d)real(Yc22)·ω=ω×gds|ω→0 d)real(Yc22)·ω=ω×gds| ω→0
步骤32:去除沟道电阻对于冷态Zc参数的影响,通过如下矩阵变换式子:Step 32: Remove the influence of the channel resistance on the cold-state Zc parameter, through the following matrix transformation formula:
其中:Zr参数表示去除沟道电阻之后的Z参数矩阵。Among them: the Zr parameter represents the Z parameter matrix after removing the channel resistance.
步骤33:利用Zr参数的实部线性拟合得到寄生电阻的值,具体拟合公式如下:Step 33: Use the real part of the Zr parameter to linearly fit to obtain the value of the parasitic resistance. The specific fitting formula is as follows:
a)real((Zr12+Zr21)/2)·ω2=ω2×Rs a)real((Zr 12 +Zr 21 )/2)·ω 2 =ω 2 ×R s
b)real(Zr11)·ω2=ω2×(Rg+Rs)b)real(Zr 11 )·ω 2 =ω 2 ×(R g +R s )
c)real(Zr22)·ω2=ω2×(Rd+Rs)c)real(Zr 22 )·ω 2 =ω 2 ×(R d +R s )
上述方案中,步骤4中所述的去嵌寄生电阻,得到晶体管本征Y参数,是通过如下矩阵变换式子实现的:In the above scheme, de-embedding the parasitic resistance described in step 4 to obtain the intrinsic Y parameter of the transistor is realized by the following matrix transformation formula:
其中:Zin参数表示去嵌寄生电阻之后的本征Z参数矩阵。Where: the Zin parameter represents the intrinsic Z parameter matrix after de-embedding the parasitic resistance.
上述方案中,步骤5中所述的根据III-V族MOSFET的小信号模型等效电路的解析式和曲线拟合来提取本征参数,是根据本征π型网络的Y参数解析式,包括如下具体拟合公式:In the above scheme, the extraction of the intrinsic parameters according to the analytical formula and curve fitting of the small-signal model equivalent circuit of the III-V MOSFET described in
a)-imag(Yin12)=ω×Cgd a)-imag(Yin 12 )=ω×C gd
d)(Yin21-Yin12)·(1+j·ω·Cgs·Rgs)=gm×e-j·ω·τ d)(Yin 21 -Yin 12 )·(1+j·ω·C gs ·R gs )=g m ×e -j·ω·τ
e)imag(Yin22+Yin12)=ω×Cds e)imag(Yin 22 +Yin 12 )=ω×C ds
f)real(Yin22+Yin12)·ω=ω×1/Rds f)real(Yin 22 +Yin 12 )·ω=ω×1/R ds
其中:Yin参数表示去嵌寄生电阻之后的本征Y参数矩阵;Among them: the Yin parameter represents the intrinsic Y parameter matrix after de-embedding the parasitic resistance;
通过Yin12的虚部(imag(Yin12))与角速度(ω)的线性关系拟合得到栅漏电容Cgd;根据Yin11+Yin12的实部与ω2×Cgs 2的线性关系提取栅源电阻Rgs,根据Yin11+Yin12虚实部与ω的线性关系提取栅源电容Cgs;然后通过Yin21-Yin12与ω的非线性关系优化拟合得到跨导gm和时间延迟因子τ;最后分别利用Yin22+Yin12和实部和虚部与ω的线性关系拟合提取沟道电阻Rds和漏源电容Cds。The gate-to-drain capacitance C gd is obtained by fitting the linear relationship between the imaginary part of Yin 12 (imag(Yin 12 )) and the angular velocity (ω); it is extracted according to the linear relationship between the real part of Yin 11 + Yin 12 and ω 2 ×C gs 2 The gate-source resistance R gs , extract the gate-source capacitance C gs according to the linear relationship between Yin 11 + Yin 12 virtual real part and ω; then obtain the transconductance g m and time delay by optimizing the nonlinear relationship between Yin 21 -Yin 12 and ω factor τ; finally, use Yin 22 +Yin 12 and the linear relationship between the real part and imaginary part and ω to fit and extract the channel resistance R ds and the drain-source capacitance C ds .
(三)有益效果(3) Beneficial effects
与现有技术相比,上述技术方案具有以下优点:Compared with the prior art, the above-mentioned technical solution has the following advantages:
1)从器件的物理层面出发建立小信号模型等效拓扑结构,提出了适用于III-V族MOSFET类型器件的参数直接提取方法,对于新材料和新结构器件的小信号建模和参数提取提供适当的参考;1) Starting from the physical level of the device, the equivalent topological structure of the small signal model is established, and a direct parameter extraction method suitable for III-V MOSFET type devices is proposed, which provides new materials and new structure devices for small signal modeling and parameter extraction. appropriate reference;
2)利用直流转移特性为依据,通过输出Y参数的研究,得到提取寄生电阻时晶体管合适偏置点的方法,避免了盲目选择冷态偏置条件引入的误差;2) Based on the DC transfer characteristics, through the research of the output Y parameters, the method of extracting the appropriate bias point of the transistor when the parasitic resistance is obtained, avoiding the error introduced by blindly selecting the cold state bias condition;
3)在提取寄生电阻参数时,去除了沟道电阻的影响,改进了寄生电阻参数结果的精确度,进而提高了本征参数的可信度;3) When extracting parasitic resistance parameters, the influence of channel resistance is removed, and the accuracy of parasitic resistance parameter results is improved, thereby improving the reliability of intrinsic parameters;
4)利用曲线拟合的思想直接拟合Y参数,得到更加准确的参数值,相比于现有技术通过解析式计算的方法来说,上述技术方案能得到确定的本征参数值而不是与频率相关的函数,另外这种提取方法无需进行再次优化过程从而得到的参数值更加符合器件本身的物理意义。4) Use the idea of curve fitting to directly fit the Y parameter to obtain a more accurate parameter value. Compared with the method of analytical calculation in the prior art, the above-mentioned technical solution can obtain the determined intrinsic parameter value instead of the same as In addition, this extraction method does not need to be optimized again, so that the obtained parameter values are more in line with the physical meaning of the device itself.
附图说明Description of drawings
图1为依照本发明实施例的III-V族MOSFET器件结构和小信号模型示意图;1 is a schematic diagram of a III-V MOSFET device structure and a small signal model according to an embodiment of the present invention;
图2为依照本发明实施例的III-V族MOSFET小信号模型参数直接提取流程图;2 is a flow chart of direct extraction of parameters of a III-V MOSFET small-signal model according to an embodiment of the present invention;
图3为依照本发明实施例的III-V族MOSFET器件在冷态条件时的等效电路;3 is an equivalent circuit of a III-V MOSFET device in a cold state according to an embodiment of the present invention;
图4a为依照本发明实施例的不同栅压下Yc22实部结果关于频率的曲线;Fig. 4a is a curve of the real part of Yc 22 with respect to frequency under different gate voltages according to an embodiment of the present invention;
图4b为依照本发明实施例的Yc22实部结果在低频1GHz处关于栅压的关系曲线;Fig. 4b is the relationship curve of the real part of Yc 22 at a low frequency of 1 GHz with respect to grid voltage according to an embodiment of the present invention;
图5为依照本发明实施例的在冷态条件提取寄生电阻参数的拟合效果;FIG. 5 is a fitting effect of extracting parasitic resistance parameters under cold conditions according to an embodiment of the present invention;
图6a为依照本发明实施例的晶体管本征Y参数实部拟合效果图;Fig. 6a is a fitting effect diagram of the real part of the intrinsic Y parameter of a transistor according to an embodiment of the present invention;
图6b为依照本发明实施例的晶体管本征Y参数虚部拟合效果图;Fig. 6b is a fitting effect diagram of the imaginary part of the intrinsic Y parameter of a transistor according to an embodiment of the present invention;
图7a和图7b为依照本发明实施例的晶体管的S参数拟合效果图,其中平滑实线表示等效电路仿真结果。7a and 7b are S-parameter fitting effect diagrams of transistors according to embodiments of the present invention, wherein the smooth solid line represents the equivalent circuit simulation results.
具体实施方式Detailed ways
为使本发明的目的、技术方案和优点更加清楚明白,以下结合具体实施例,并参照附图,对本发明进一步详细说明。In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.
本发明提供的这种III-V族MOSFET的小信号模型参数直接提取方法,是通过焊盘和金属互联线去嵌,利用晶体管直流转移特性和冷态S参数确定提取晶体管寄生电阻时的合适偏置条件,然后在该偏置条件下去除沟道电阻影响,线性拟合提取寄生电阻参数,最后去嵌寄生电阻,利用III-V族MOSFET的小信号模型等效电路和曲线拟合来提取本征参数,该方法具体包括以下步骤:The method for directly extracting small-signal model parameters of this III-V family MOSFET provided by the present invention is to de-embed through pads and metal interconnection lines, and use transistor DC transfer characteristics and cold-state S parameters to determine the appropriate bias when extracting transistor parasitic resistance. Under this bias condition, the influence of the channel resistance is removed, the parasitic resistance parameters are extracted by linear fitting, and finally the parasitic resistance is de-embedded, and the small-signal model equivalent circuit and curve fitting of the III-V MOSFET are used to extract the characteristic parameters, the method specifically includes the following steps:
步骤1:利用在片结构去嵌测试焊盘和金属互联线引入的寄生参数;Step 1: Use the on-chip structure to de-embed the parasitic parameters introduced by the test pad and metal interconnection lines;
步骤2:根据晶体管的直流转移特性、冷态晶体管的小信号等效电路和不同栅压的冷态S参数,确定提取寄生电阻时晶体管的合适偏置条件;Step 2: According to the DC transfer characteristics of the transistor, the small-signal equivalent circuit of the cold-state transistor, and the cold-state S-parameters of different gate voltages, determine the appropriate bias conditions for the transistor when extracting the parasitic resistance;
步骤3:在上述偏置条件下,去除沟道电阻的影响,提取寄生电阻参数;Step 3: Under the above bias conditions, remove the influence of channel resistance and extract parasitic resistance parameters;
步骤4:去嵌寄生电阻,得到晶体管本征Y参数;Step 4: De-embed the parasitic resistance to obtain the intrinsic Y parameter of the transistor;
步骤5:根据III-V族MOSFET的小信号模型等效电路的解析式和曲线拟合来提取本征参数。Step 5: Extract the intrinsic parameters according to the analytical formula and curve fitting of the small-signal model equivalent circuit of the III-V MOSFET.
其中,所述的III-V族MOSFET的小信号模型等效电路包括五个电阻、三个电容和一个压控电流源,其中:栅电阻(Rg)与栅上氧化层接触材料有关,由栅金属的分布损耗效应构成;源/漏电阻(Rs,Rd)由金属半导体接触电阻和半导体的体电阻两部分组成;栅源电容(Cgs)和栅漏电容(Cgd)表针对应区域的放电充电过程,其中包含了栅和源/漏之间的边缘效应,栅漏电阻(Rgs)表针栅漏电容充放电过程的非准态效应;沟道电阻(Rds)来源于漏源电流并不是真正随漏压饱和,Cds表示电静态下源漏之间电容效应;本征跨导(gm)代表栅压对沟道电流的调制或者控制能力,参数τ指时间延迟因子。Wherein, the small-signal model equivalent circuit of the described III-V family MOSFET includes five resistors, three capacitors and a voltage-controlled current source, wherein: the gate resistance (R g ) is related to the contact material of the oxide layer on the gate, and is determined by The distribution loss effect of the gate metal; the source/drain resistance (R s , R d ) is composed of two parts: the metal-semiconductor contact resistance and the semiconductor body resistance; the gate-source capacitance (C gs ) and the gate-drain capacitance (C gd ) are for The discharge and charge process of the response area, which includes the edge effect between the gate and the source/drain, the gate-to-drain resistance (R gs ) indicates the non-quasi-state effect of the gate-to-drain capacitance charge and discharge process; the channel resistance (R ds ) comes from The drain-source current does not really saturate with the drain voltage, C ds represents the capacitive effect between the source and drain under electrostatic conditions; the intrinsic transconductance (g m ) represents the modulation or control ability of the gate voltage on the channel current, and the parameter τ refers to the time delay factor.
步骤2中所述的冷态晶体管的小信号等效电路包括四个电阻和三个电容,所述的冷态是指器件处于源漏无压降的偏置状态,即Vds=0V;在冷态条件下,晶体管的沟道电流可忽略,近似认为栅压没有对沟道的调制或者控制能力,冷态晶体管的小信号等效电路与非冷态晶体管小信号等效电路的区别在于没有电压受控电流源部分,对应Z参数可以写成如下表达式:The small-signal equivalent circuit of the cold-state transistor described in
其中:Zc参数表示冷态晶体管的Z参数矩阵,Yc参数表示冷态晶体管的Y参数矩阵Among them: the Zc parameter represents the Z parameter matrix of the cold state transistor, and the Yc parameter represents the Y parameter matrix of the cold state transistor
gds=1/Rds;|Yc|=jωgds(Cgs+Cgd)-ω2(CgsCgd+CgsCds+CgdCds)。g ds =1/R ds ; |Yc|=jωg ds (C gs +C gd )−ω 2 (C gs C gd +C gs C ds +C gd C ds ).
步骤2中所述的确定提取寄生电阻时晶体管的合适偏置条件,包括以下步骤:Determining suitable biasing conditions for transistors when extracting parasitic resistances as described in
步骤21:在一定漏压偏置条件下,扫描栅压,得到直流转移特性,利用线性区外推法获得阈值电压Vth;Step 21: Under a certain drain voltage bias condition, scan the gate voltage to obtain the DC transfer characteristics, and obtain the threshold voltage V th by using the linear region extrapolation method;
步骤22:在冷态条件Vds=0V下,以频率为第一变量,栅压为第二变量进行扫描,栅压的范围可以是Vth-2V<Vgs<Vth+0.5V,得到一组不同栅压下冷态S参数结果;如图3所示,图3是本发明的III-V族MOSFET器件在冷态条件时的等效电路;Step 22: Under cold condition V ds = 0V, scan with frequency as the first variable and gate voltage as the second variable, the range of gate voltage can be V th -2V<V gs <V th +0.5V, and get A group of cold-state S parameter results under different grid voltages; as shown in Figure 3, Figure 3 is the equivalent circuit of the III-V group MOSFET device of the present invention under cold-state conditions;
步骤23:根据冷态S参数结果,去嵌测试焊盘和金属互联线引入的寄生参数,之后转换为Y参数,得到一组不同栅压下Yc22的实部结果。在频率足够低时,本征电容和沟道电阻表现出很大的阻抗值,此时可以忽略寄生电阻对Y参数的影响,得到:Step 23: According to the cold-state S-parameter results, de-embed the parasitic parameters introduced by the test pads and metal interconnection lines, and then convert them into Y parameters to obtain a set of real part results of Yc 22 under different gate voltages. When the frequency is low enough, the intrinsic capacitance and channel resistance show a large impedance value. At this time, the influence of the parasitic resistance on the Y parameter can be ignored, and it is obtained:
其中:|Zc|=Zc11·Zc22-Zc12·Zc21 Where: |Zc|=Zc 11 ·Zc 22 -Zc 12 ·Zc 21
在低频Freq=1GHz处记录Yc22实部的值,绘制Yc22实部关于栅压的关系曲线,栅极电压越大,沟道电阻受到栅压的调制而变小,这样利用冷态Z参数提取寄生电阻的误差变大,因此在Yc22实部开始出现上升的栅压以下区域为提取晶体管寄生电阻的合适偏置区域,确定Yc22实部开始出现上升时的栅压值为Vh;Record the value of the real part of Yc 22 at the low frequency Freq=1GHz, and draw the relationship curve of the real part of Yc 22 with respect to the gate voltage. The larger the gate voltage is, the channel resistance becomes smaller due to the modulation of the gate voltage. In this way, the cold state Z parameter is used The error of extracting the parasitic resistance becomes larger, so the area below the gate voltage where the real part of Yc 22 begins to rise is the appropriate bias area for extracting the parasitic resistance of the transistor, and the gate voltage value when the real part of Yc 22 begins to rise is determined to be Vh;
步骤24:得到提取晶体管寄生电阻的偏置条件为:Vds=0V和Vgs=Vh-Vo,所述Vo代表引入的工程余量。Step 24: Obtain the bias conditions for extracting the parasitic resistance of the transistor as follows: V ds =0V and V gs =Vh-Vo, where Vo represents the introduced engineering margin.
步骤3中所述的提取寄生电阻参数包括以下步骤:The extraction of parasitic resistance parameters described in
步骤31:根据到的提取晶体管寄生电阻的偏置条件,利用所述偏置条件下的S参数,去嵌测试焊盘和金属互联线引入的寄生参数,之后转换为Y参数,利用Y参数的虚部提取冷态晶体管的Cgs,Cgd,Cds,利用Yc22低频的实部结果提取gds,具体拟合公式如下:Step 31: According to the obtained bias conditions for extracting the parasitic resistance of the transistor, use the S parameters under the bias conditions to de-embed the parasitic parameters introduced by the test pad and metal interconnection lines, and then convert them into Y parameters, and use the S parameters of the Y parameters The imaginary part extracts C gs , C gd , and C ds of the cold transistor, and the real part of Yc 22 low frequency is used to extract g ds . The specific fitting formula is as follows:
a)-imag((Yc12+Yc21)/2)=ω×Cgd a)-imag((Yc 12 +Yc 21 )/2)=ω×C gd
b)imag(Yc11)-ω·Cgd=ω×Cgs b) imag(Yc 11 )-ω·C gd =ω×C gs
c)imag(Yc22)-ω·Cgd=ω×Cds c)imag(Yc 22 )-ω·C gd =ω×C ds
d)real(Yc22)·ω=ω×gds|ω→0 d)real(Yc22)·ω=ω×gds| ω→0
步骤32:去除沟道电阻对于冷态Zc参数的影响,通过如下矩阵变换式子:Step 32: Remove the influence of the channel resistance on the cold-state Zc parameter, through the following matrix transformation formula:
其中:Zr参数表示去除沟道电阻之后的Z参数矩阵。Among them: the Zr parameter represents the Z parameter matrix after removing the channel resistance.
步骤33:利用Zr参数的实部线性拟合得到寄生电阻的值,具体拟合公式如下:Step 33: Use the real part of the Zr parameter to linearly fit to obtain the value of the parasitic resistance. The specific fitting formula is as follows:
a)real((Zr12+Zr21)/2)·ω2=ω2×Rs a)real((Zr 12 +Zr 21 )/2)·ω 2 =ω 2 ×R s
b)real(Zr11)·ω2=ω2×(Rg+Rs)b)real(Zr 11 )·ω 2 =ω 2 ×(R g +R s )
c)real(Zr22)·ω2=ω2×(Rd+Rs)c)real(Zr 22 )·ω 2 =ω 2 ×(R d +R s )
步骤4中所述的去嵌寄生电阻,得到晶体管本征Y参数,是通过如下矩阵变换式子实现的:The de-embedded parasitic resistance described in step 4 to obtain the intrinsic Y parameters of the transistor is realized by the following matrix transformation formula:
其中:Zin参数表示去嵌寄生电阻之后的本征Z参数矩阵。Where: the Zin parameter represents the intrinsic Z parameter matrix after de-embedding the parasitic resistance.
步骤5中所述的根据III-V族MOSFET的小信号模型等效电路的解析式和曲线拟合来提取本征参数,是根据本征π型网络的Y参数解析式,包括如下具体拟合公式:The extraction of intrinsic parameters according to the analytical formula and curve fitting of the small-signal model equivalent circuit of the III-V MOSFET described in
a)-imag(Yin12)=ω×Cgd a)-imag(Yin 12 )=ω×C gd
d)(Yin21-Yin12)·(1+j·ω·Cgs·Rgs)=gm×e-j·ω·τ d)(Yin 21 -Yin 12 )·(1+j·ω·C gs ·R gs )=g m ×e -j·ω·τ
e)imag(Yin22+Yin12)=ω×Cds e)imag(Yin 22 +Yin 12 )=ω×C ds
f)real(Yin22+Yin12)·ω=ω×1/Rds f)real(Yin 22 +Yin 12 )·ω=ω×1/R ds
其中:Yin参数表示去嵌寄生电阻之后的本征Y参数矩阵;Among them: the Yin parameter represents the intrinsic Y parameter matrix after de-embedding the parasitic resistance;
通过Yin12的虚部(imag(Yin12))与角速度(ω)的线性关系拟合得到栅漏电容Cgd;根据Yin11+Yin12的实部与ω2×Cgs 2的线性关系提取栅源电阻Rgs,根据Yin11+Yin12虚实部与ω的线性关系提取栅源电容Cgs;然后通过Yin21-Yin12与ω的非线性关系优化拟合得到跨导gm和时间延迟因子τ;最后分别利用Yin22+Yin12和实部和虚部与ω的线性关系拟合提取沟道电阻Rds和漏源电容Cds。The gate-to-drain capacitance C gd is obtained by fitting the linear relationship between the imaginary part of Yin 12 (imag(Yin 12 )) and the angular velocity (ω); it is extracted according to the linear relationship between the real part of Yin 11 + Yin 12 and ω 2 ×C gs 2 The gate-source resistance R gs , extract the gate-source capacitance C gs according to the linear relationship between Yin 11 + Yin 12 virtual real part and ω; then obtain the transconductance g m and time delay by optimizing the nonlinear relationship between Yin 21 -Yin 12 and ω factor τ; finally, use Yin 22 +Yin 12 and the linear relationship between the real part and imaginary part and ω to fit and extract the channel resistance R ds and the drain-source capacitance C ds .
图1是依照本发明实施例的用InGaAs MOSFET器件物理结构和小信号模型,材料结构包括:GaAs衬底,AlGaAs缓冲层,InGaAs沟道层,InGaP势垒层,Al2O3氧化层,钝化层等,后面具体的实例对这种结构的器件的参数提取方法进行说明。Fig. 1 is according to the physical structure and small signal model of InGaAs MOSFET device according to the embodiment of the present invention, material structure comprises: GaAs substrate, AlGaAs buffer layer, InGaAs channel layer, InGaP barrier layer, Al 2 O 3 oxide layer, passivation layer, etc., and the following specific examples will illustrate the parameter extraction method of the device with this structure.
图2为依照本发明实施例的InGaAs MOSFET器件的小信号模型参数直接提取流程图,包括如下步骤:Fig. 2 is the direct extraction flowchart of the small signal model parameter of the InGaAs MOSFET device according to the embodiment of the present invention, comprises the following steps:
步骤1:测试器件和在片去嵌结构的S参数,利用测试结果去除测试焊盘和金属互联线引入的寄生参数,外围寄生参数的准确提取会影响内部非线性参数的准确性。Step 1: Test the S parameters of the device and the on-chip de-embedding structure, and use the test results to remove the parasitic parameters introduced by the test pads and metal interconnection lines. Accurate extraction of peripheral parasitic parameters will affect the accuracy of internal nonlinear parameters.
步骤2:根据晶体管的直流转移特性、冷态晶体管的小信号等效电路和冷态S参数,确定提取寄生电阻时晶体管的合适偏置条件;Step 2: According to the DC transfer characteristics of the transistor, the small-signal equivalent circuit of the cold-state transistor and the cold-state S-parameter, determine the appropriate bias condition of the transistor when extracting the parasitic resistance;
测试晶体管直流转移特性:设置漏极电压为1V,栅极电压在-1V~3V区间扫描,得到转移特性曲线,通过线性区外推法得到阈值电压为0.5V。测试晶体管冷态S参数:设置漏极电压为0V,栅极电压在-2~1V区间以0.25V为步长进行扫描,同时在1GHz~40GHz区间以100MHz为步长扫描频率得到一组不同栅压下冷态S参数结果。然后去嵌焊盘和金属互联线引入的寄生参数,之后转换为Y参数,得到一组不同栅压下Yc22的实部结果,最后得到提取晶体管寄生电阻的偏置条件为:Vds=0V和Vgs=-0.5V。Test the DC transfer characteristics of the transistor: set the drain voltage to 1V, scan the gate voltage between -1V and 3V to obtain the transfer characteristic curve, and obtain the threshold voltage as 0.5V through linear region extrapolation. Test the cold-state S parameters of the transistor: set the drain voltage to 0V, scan the gate voltage in the range of -2 to 1V with a step size of 0.25V, and at the same time scan the frequency in the range of 1GHz to 40GHz with a step size of 100MHz to obtain a set of different gate voltages. Press down on the cold state S-parameter results. Then de-embed the parasitic parameters introduced by the pads and metal interconnection lines, and then convert them into Y parameters to obtain a set of real part results of Yc 22 under different gate voltages. Finally, the bias condition for extracting the parasitic resistance of the transistor is: V ds = 0V and V gs =-0.5V.
图4a为依照本发明实施例的不同栅压下Yc22实部结果关于频率的曲线,栅极电压的范围为-0.5V~0.5V,以0.25V为步长。可以看出当栅极电压Vgs=0V时,Yc22的实部在整个频率范围里开始出现上升趋势。图4b为依照本发明实施例的Yc22实部结果在低频1GHz处关于栅压的关系曲线,确定Yc22实部开始出现上升的栅压值为0V,在栅极电压小于0V的区域,Yc22实部较小,表明沟道电阻足够大,这样对于冷态条件Y参数的实部影响最小,因此在该区域里提取寄生电阻参数较为准确。Fig. 4a is a curve of the real part of Yc 22 with respect to frequency under different gate voltages according to an embodiment of the present invention, the gate voltage ranges from -0.5V to 0.5V, and the step size is 0.25V. It can be seen that when the gate voltage V gs =0V, the real part of Yc 22 starts to rise in the whole frequency range. Fig. 4b is the relationship curve of the real part of Yc 22 at a low frequency of 1 GHz with respect to the grid voltage according to an embodiment of the present invention. It is determined that the real part of Yc 22 begins to rise when the grid voltage value is 0V. In the region where the gate voltage is less than 0V, Yc The real part of 22 is small, indicating that the channel resistance is large enough, which has the least influence on the real part of the Y parameter in cold conditions, so it is more accurate to extract parasitic resistance parameters in this region.
步骤3:在上述偏置条件下,去除沟道电阻的影响,提取寄生电阻参数;Step 3: Under the above bias conditions, remove the influence of channel resistance and extract parasitic resistance parameters;
图5为依照本发明实施例的在冷态条件提取寄生电阻参数的拟合效果,其中平滑实线或虚线表示冷态等效电路S参数仿真结果,散点图形表示实验测试数据,从结果可以看出,除了高频处出现一些随机性影响S参数的拟合效果,总体来看,在较宽频率范围里拟合效果较好,提取的寄生电阻参数符合要求。在截止区冷态条件(Vgs=-0.5V,Vds=0V)时本征电容和沟道电阻提取结果为:Cds=13fF,Cgd=26.5fF,Cgs=24.6fF,Rds=10K,去除沟道电阻影响后得到的寄生电阻参数为:Rs=4.1Ω,Rg=1.34Ω,Rd=7.4Ω。Fig. 5 is the fitting effect of extracting the parasitic resistance parameter in the cold state condition according to the embodiment of the present invention, wherein the smooth solid line or dotted line represents the cold state equivalent circuit S parameter simulation result, and the scatter graph represents the experimental test data, from the result can be It can be seen that except for some randomness at high frequencies that affects the fitting effect of S parameters, overall, the fitting effect is better in a wider frequency range, and the extracted parasitic resistance parameters meet the requirements. In the cold state of the cut-off region (Vgs=-0.5V, Vds=0V), the extraction results of intrinsic capacitance and channel resistance are: Cds=13fF, Cgd=26.5fF, Cgs=24.6fF, Rds=10K, remove the channel The parasitic resistance parameters obtained after the influence of resistance are: Rs=4.1Ω, Rg=1.34Ω, Rd=7.4Ω.
步骤4:去嵌寄生电阻,得到晶体管本征Y参数;Step 4: De-embed the parasitic resistance to obtain the intrinsic Y parameter of the transistor;
步骤5:根据小信号模型等效电路的解析式和曲线拟合的思想提取本征参数。Step 5: Extract the intrinsic parameters according to the analytical formula of the equivalent circuit of the small signal model and the idea of curve fitting.
图6a为依照本发明实施例的晶体管本征Y参数实部拟合效果图,图6b为依照本发明实施例的晶体管本征Y参数虚部拟合效果图,总体来说,本征相关参数通过直接拟合提取的方法具有良好的可信度,同时不需要进行再次优化的过程,因此提取的本征参数结果符合器件本身的物理意义。饱和区(Vgs=3V,Vds=2V)小信号参数提取结果为:Cgs=98.2fF,Cgd=20.1fF,Cds=17.7fF,Rgs=1.72Ω,Rds=278.7Ω,gm=53.1mS,tau=0.1ps。Fig. 6a is a fitting effect diagram of the real part of the transistor intrinsic Y parameter according to an embodiment of the present invention, and Fig. 6b is a fitting effect diagram of the imaginary part of the transistor intrinsic Y parameter according to an embodiment of the present invention. Generally speaking, the intrinsic related parameters The method extracted by direct fitting has good reliability and does not need to be re-optimized, so the extracted intrinsic parameter results conform to the physical meaning of the device itself. The extraction results of small signal parameters in the saturation region (Vgs=3V, Vds=2V) are: Cgs=98.2fF, Cgd=20.1fF, Cds=17.7fF, Rgs=1.72Ω, Rds=278.7Ω, gm=53.1mS, tau= 0.1ps.
图7a和图7b为依照本发明实施例的晶体管的S参数拟合效果图,其中平滑实线表示等效电路仿真结果,散点图形表示实验测试数据;其中晶体管的偏置条件为栅极电压为3V,漏极电压为2V,扫描频率1GHz~40GHz,步长为100MHz;可以看出测试和仿真的曲线基本重合,说明本发明等效电路很好地反映了InGaAs MOSFET晶体管的交流特性,因此本发明参数直接提取的方法具有很好地实用性。Fig. 7a and Fig. 7b are the S parameter fitting effect diagrams of the transistor according to the embodiment of the present invention, wherein the smooth solid line represents the simulation result of the equivalent circuit, and the scatter graph represents the experimental test data; wherein the bias condition of the transistor is the gate voltage is 3V, the drain voltage is 2V, the scanning frequency is 1GHz~40GHz, and the step size is 100MHz; it can be seen that the curves of the test and simulation basically overlap, indicating that the equivalent circuit of the present invention reflects the AC characteristics of the InGaAs MOSFET transistor well, so The method for directly extracting parameters of the present invention has good practicability.
以上所述的具体实施例,对本发明的目的、技术方案和有益效果进行了进一步详细说明,所应理解的是,以上所述仅为本发明的具体实施例而已,并不用于限制本发明,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.
Claims (8)
- The small-signal model parameter direct extraction method of the 1.Yi Zhong III-V MOSFET of family, it is characterized in that, the method is to go embedding by pad and metal interconnection wire, utilize transistor DC transfer characteristics and cold conditions S parameter to determine the suitable bias condition while extracting transistor parasitic resistance, then under this bias condition, remove channel resistance impact, linear fit extracts dead resistance parameter, finally go embedding dead resistance, utilize small-signal model equivalent electrical circuit and the curve of the MOSFET of III-V family to extract intrinsic parameters.
- 2. the small-signal model parameter direct extraction method of the III-V MOSFET of family according to claim 1, is characterized in that, the method specifically comprises the following steps:Step 1: utilize the parasitic parameter that goes embedding testing weld pad and metal interconnection wire to introduce in chip architecture;Step 2: according to the cold conditions S parameter of transistorized direct current transfer characteristics, the transistorized small-signal equivalent circuit of cold conditions and different grid voltages, determine transistorized suitable bias condition while extracting dead resistance;Step 3: under above-mentioned bias condition, remove the impact of channel resistance, extract dead resistance parameter;Step 4: go embedding dead resistance, obtain transistor intrinsic Y parameter;Step 5: extract intrinsic parameters according to analytic expression and the curve of the small-signal model equivalent electrical circuit of the MOSFET of III-V family.
- 3. the small-signal model parameter direct extraction method of the III-V MOSFET of family according to claim 1 and 2, it is characterized in that, the small-signal model equivalent electrical circuit of the described MOSFET of III-V family comprises five resistance, three electric capacity and a voltage-controlled current source, wherein: gate resistance (R g) relevant with oxide layer contact material on grid, by the distribution losses effect of grid metal, formed; Source/leakage resistance (R s, R d) by metal-semiconductor contact resistance and semi-conductive bulk resistor two parts, formed; Grid source electric capacity (C gs) and gate leakage capacitance (C gd) the electric discharge charging process of indicator corresponding region, wherein comprised the edge effect between grid and source/leakage, grid leak resistance (R gs) the non-accurate state effect of indicator gate leakage capacitance charge and discharge process; Channel resistance (R ds) to derive from drain-source current be not really saturated with leak pressing, C dsrepresent capacity effect between the static lower source leakage of electricity; Intrinsic transconductance (g m) representing that grid voltage is to the modulation of channel current or control ability, parameter τ refers to the time delay factor.
- 4. the small-signal model parameter direct extraction method of the III-V MOSFET of family according to claim 2, it is characterized in that, the transistorized small-signal equivalent circuit of cold conditions described in step 2 comprises four resistance and three electric capacity, described cold conditions refers to that device leaks the bias state without pressure drop, i.e. V in source ds=0V; Under cold condition, transistorized channel current can be ignored, be similar to and think that grid voltage is not to the modulation of raceway groove or control ability, the difference of the transistorized small-signal equivalent circuit of cold conditions and non-cold conditions transistor small-signal equivalent circuit is not have voltage controlled current source part, and corresponding Z parameter can be write as following expression:Wherein: the transistorized Z parameter matrix of Zc Parametric Representation cold conditions, the transistorized Y parameter matrix of Yc Parametric Representation cold conditionsg ds=1/R ds;|Yc|=jωg ds(C gs+C gd)-ω 2(C gsC gd+C gsC ds+C gdC ds)。
- 5. the small-signal model parameter direct extraction method of the III-V MOSFET of family according to claim 2, is characterized in that, transistorized suitable bias condition during definite extraction dead resistance described in step 2, comprises the following steps:Step 21: press under bias condition certain leakage, scanning grid voltage, obtains direct current transfer characteristics, utilizes linear zone extrapolation method to obtain threshold voltage V th;Step 22: at cold condition V dsunder=0V, take frequency as the first variable, grid voltage is that the second variable scans, and the scope of grid voltage can be V th-2V<V gs<V th+ 0.5V, obtains cold conditions S parameter result under one group of different grid voltage;Step 23: according to cold conditions S parameter result, the parasitic parameter that goes embedding testing weld pad and metal interconnection wire to introduce, is converted to Y parameter afterwards, obtains Yc under one group of different grid voltage 22real part result.When frequency is enough low, intrinsic capacity and channel resistance show very large resistance value, now can ignore the impact of dead resistance on Y parameter, obtain:At low frequency Freq=1GHz place, record Yc 22the value of real part, draws Yc 22real part is about the relation curve of grid voltage, and grid voltage is larger, and channel resistance is subject to the modulation of grid voltage and diminishes, and utilizes like this error of cold conditions Z parameter extraction dead resistance to become large, therefore at Yc 22it is the suitable displacement zone of extracting transistor parasitic resistance that the grid voltage that real part starts occur to rise be take lower area, determines Yc 22grid voltage value when real part starts to occur rising is Vh;Step 24: the bias condition that obtains extracting transistor parasitic resistance is: V ds=0V and V gs=Vh-Vo, the engineering surplus that described Vo representative is introduced.
- 6. the small-signal model parameter direct extraction method of the III-V MOSFET of family according to claim 2, is characterized in that, the extraction dead resistance parameter described in step 3 comprises the following steps:Step 31: the bias condition according to the extraction transistor parasitic resistance arriving, utilize the S parameter under described bias condition, the parasitic parameter that goes embedding testing weld pad and metal interconnection wire to introduce, is converted to Y parameter afterwards, utilizes the imaginary part of Y parameter to extract the transistorized C of cold conditions gs, C gd, C ds, utilize Yc 22the real part result of low frequency is extracted g ds, concrete fitting formula is as follows:a)-imag((Yc 12+Yc 21)/2)=ω×C gdb)imag(Yc 11)-ω·C gd=ω×C gsc)imag(Yc 22)-ω·C gd=ω×C dsd)real(Yc22)·ω=ω×gds| ω→0Step 32: remove channel resistance for the impact of cold conditions Zc parameter, by following matrixing formula:Wherein: Zr Parametric Representation is removed the Z parameter matrix after channel resistance.Step 33: utilize the real part linear fit of Zr parameter to obtain the value of dead resistance, concrete fitting formula is as follows:a)real((Zr 12+Zr 21)/2)·ω 2=ω 2×R sb)real(Zr 11)·ω 2=ω 2×(R g+R s)c)real(Zr 22)·ω 2=ω 2×(R d+R s)?。
- 7. the small-signal model parameter direct extraction method of the III-V MOSFET of family according to claim 2, is characterized in that, described in step 4, goes embedding dead resistance, obtains transistor intrinsic Y parameter, by following matrixing formula, realizes:Wherein: Zin Parametric Representation removes the intrinsic Z parameter matrix after embedding dead resistance.
- 8. the small-signal model parameter direct extraction method of the III-V MOSFET of family according to claim 2, it is characterized in that, analytic expression and curve according to the small-signal model equivalent electrical circuit of the MOSFET of III-V family described in step 5 extract intrinsic parameters, be the Y parameter analytic expression according to intrinsic pin network, comprise following concrete fitting formula:a)-imag(Yin 12)=ω×C gdd)(Yin 21-Yin 12)·(1+j·ω·C gs·R gs)=g m×e -j·ω·τe)imag(Yin 22+Yin 12)=ω×C dsf)real(Yin 22+Yin 12)·ω=ω×1/R dsWherein: Yin Parametric Representation removes the intrinsic Y parameter matrix after embedding dead resistance;Pass through Yin 12imaginary part (imag (Yin 12)) obtain gate leakage capacitance C with the linear relationship matching of angular velocity (ω) gd; According to Yin 11+ Yin 12real part and ω 2* C gs 2linear relationship extract grid source resistance R gs, according to Yin 11+ Yin 12the linear relationship of actual situation portion and ω is extracted grid source capacitor C gs; Then pass through Yin 21-Yin 12obtain mutual conductance g with the nonlinear relationship Optimal Fitting of ω mwith time delay factor τ; Finally utilize respectively Yin 22+ Yin 12extract channel resistance R with the linear relationship matching of real part and imaginary part and ω dswith drain-source capacitor C ds.
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