CN103617319A - Method for directly extracting small-signal model parameters of III-V group MOSFET (metal-oxide-semiconductor field effect transistor) - Google Patents

Abstract

The invention discloses a method for directly extracting small-signal model parameters of a III-V group MOSFET (metal-oxide-semiconductor field effect transistor), belonging to the technical field of microelectronic integrated circuits. According to the method, de-embedding is carried out through a bonding pad and a metal interconnection line, proper bias conditions during extraction of parasitic resistance of a transistor are determined by using direct current transfer characteristics and cold state S parameters of the transistor, then channel resistance influence is removed under the bias conditions, parasitic resistance parameters are extracted through linear fitting, the parasitic resistance is finally de-embedded, and intrinsic parameters are extracted through a small signal model equivalent circuit and curve fitting of a III-V group MOSFET. The small signal parameter direct extraction process provided by the invention completely accords with the physical significance of devices, provides a necessary basis for the application of integrated circuit technology, and has a good reference function for extracting small signal model parameters of other types of devices such as new materials, new structures and the like.

Description

The small-signal model parameter direct extraction method of a kind of III-V MOSFET of family

Technical field

The present invention relates to microelectronic integrated circuit technical field, relate in particular to the small-signal model parameter direct extraction method of a kind of III-V MOSFET of family, can be used for effectively extracting the small-signal parameter result of the MOSFET of III-V family types of devices, for device technology optimization and circuit simulation design.

Background technology

11 nm technology node and after, due to the physical characteristics restriction of silicon materials itself, silicon base CMOS technology will face huge challenge, high mobility " non-silicon " material will progressively be incorporated in CMOS technology.The advantages such as it is high that III-V group iii v compound semiconductor material has electron mobility, and intrinsic is short time delay, and radio-frequency performance is good, and the electric leakage of grid is little, and quiescent dissipation is low, have become a study hotspot of the current technology of MOSFET in the world.The accurate extraction of small-signal model parameter is for instructing processing step, characterization processes accuracy, improve device architecture, the impact of research technological parameter on device high frequency performance, the aspects such as Application of integrated circuit are significant, and therefore studying the MOSFET of III-V family small-signal model has researching value and practical value well.

Small-signal model can reflect the physical arrangement feature of device and in the high frequency characteristics of certain bias point, reproduction and extrapolation for device high frequency small-signal performance all have important directive significance, and the accuracy of model parameter extraction is directly connected to the accuracy of small-signal model.The people such as Gilles Dambrine are at document " A new method for determining the FET small signal equivalent circuit " (IEEE Transaction on Microwave Theory and Techniques, July1988) the small-signal model parameter direct extraction method to GaAs HEMT in is carried out detailed description, wherein the extraction of dead resistance parameter is that device is in cold condition, take into full account grid lower channel resistance and Schottky barrier equiva lent impedance, utilize 3 groups of Z parameter fitting results under different gate current conditions as additional relationships condition, obtain dead resistance parameter, yet for MOSFET structure devices, insulativity due to oxide layer under grid, such method is no longer applicable, intrinsic parameters wherein calculates intrinsic parameters about the funtcional relationship of frequency by analytic expression method, then in frequency-flat district, obtains the value of parameter, and the result obtaining like this there will be certain deviation when some frequency field matching.

The people such as Sanna Taking is at document " AlN-GaN MOS-HEMTs with thermally grown Al2O3 passivation " (IEEE Transaction on Electron Devices in addition, May2011) for the extraction of the parasitic parameter of MOS-HEMT structure devices, source/leakage dead resistance is tested by TLM and device geometries calculates, grid dead resistance obtains by resistivity and the sizecalculation of grid metal, the deficiency that the method exists is, in the process of extracting parameter, consider separately the theory contribution of resistance, ignore the contingent change of dead resistance in element manufacturing flowchart process, after wherein extracting intrinsic parameters, carry out global optimization to eliminate the randomness of technique, the parameter the possibility of result after then optimizing departs from the physical significance of device itself.

Summary of the invention

(1) technical matters that will solve

In order accurately to extract dead resistance and the intrinsic parameters of the MOSFET of III-V family device, the invention provides a kind of small-signal model parameter direct extraction method of the III-V of the being applicable to MOSFET of family structure.

(2) technical scheme

For achieving the above object, the invention provides the small-signal model parameter direct extraction method of a kind of III-V MOSFET of family, the method is to go embedding by pad and metal interconnection wire, utilize transistor DC transfer characteristics and cold conditions S parameter to determine the suitable bias condition while extracting transistor parasitic resistance, then under this bias condition, remove channel resistance impact, linear fit extracts dead resistance parameter, finally go embedding dead resistance, utilize small-signal model equivalent electrical circuit and the curve of the MOSFET of III-V family to extract intrinsic parameters.

In such scheme, the method specifically comprises the following steps: step 1: utilize the parasitic parameter that goes embedding testing weld pad and metal interconnection wire to introduce in chip architecture; Step 2: according to the cold conditions S parameter of transistorized direct current transfer characteristics, the transistorized small-signal equivalent circuit of cold conditions and different grid voltages, determine transistorized suitable bias condition while extracting dead resistance; Step 3: under above-mentioned bias condition, remove the impact of channel resistance, extract dead resistance parameter; Step 4: go embedding dead resistance, obtain transistor intrinsic Y parameter; Step 5: extract intrinsic parameters according to analytic expression and the curve of the small-signal model equivalent electrical circuit of the MOSFET of III-V family.

In such scheme, the small-signal model equivalent electrical circuit of the described MOSFET of III-V family comprises five resistance, three electric capacity and a voltage-controlled current source, wherein: gate resistance (R _g) relevant with oxide layer contact material on grid, by the distribution losses effect of grid metal, formed; Source/leakage resistance (R _s, R _d) by metal-semiconductor contact resistance and semi-conductive bulk resistor two parts, formed; Grid source electric capacity (C _gs) and gate leakage capacitance (C _gd) the electric discharge charging process of indicator corresponding region, wherein comprised the edge effect between grid and source/leakage, grid leak resistance (R _gs) the non-accurate state effect of indicator gate leakage capacitance charge and discharge process; Channel resistance (R _ds) to derive from drain-source current be not really saturated with leak pressing, C _dsrepresent capacity effect between the static lower source leakage of electricity; Intrinsic transconductance (g _m) representing that grid voltage is to the modulation of channel current or control ability, parameter τ refers to the time delay factor.

In such scheme, the transistorized small-signal equivalent circuit of the cold conditions described in step 2 comprises four resistance and three electric capacity, and described cold conditions refers to that device leaks the bias state without pressure drop, i.e. V in source _ds=0V; Under cold condition, transistorized channel current can be ignored, be similar to and think that grid voltage is not to the modulation of raceway groove or control ability, the difference of the transistorized small-signal equivalent circuit of cold conditions and non-cold conditions transistor small-signal equivalent circuit is not have voltage controlled current source part, and corresponding Z parameter can be write as following expression:

${\mathrm{<figure-callout\; id="11"\; label="Zc"\; filenames="HDA0000423066960000031.png,HDA0000423066960000041.png"\; state="\{\{state\}\}">Zc</figure-callout>}}_{11}=\frac{g_{\mathrm{ds}}+\mathrm{j\&omega;}(C_{\mathrm{gd}}+C_{\mathrm{ds}})}{\left|\mathrm{Yc}\right|}+R_g+R_s$

${\mathrm{<figure-callout\; id="12"\; label="Zc"\; filenames="HDA0000423066960000022.png,HDA0000423066960000023.png"\; state="\{\{state\}\}">Zc</figure-callout>}}_{12}=\frac{\mathrm{j\&omega;}{C}_{\mathrm{gd}}}{\left|\mathrm{Yc}\right|}+R_s$

${\mathrm{Zc}}_{21}=\frac{\mathrm{j\&omega;}{C}_{\mathrm{gd}}}{\left|\mathrm{Yc}\right|}+R_s$

${\mathrm{<figure-callout\; id="22"\; label="Zc"\; filenames="HDA0000423066960000031.png,HDA0000423066960000041.png"\; state="\{\{state\}\}">Zc</figure-callout>}}_{22}=\frac{\mathrm{j\&omega;}(C_{\mathrm{gs}}+C_{\mathrm{gd}})}{\left|\mathrm{Yc}\right|}+R_d+R_s$

Wherein: the transistorized Z parameter matrix of Zc Parametric Representation cold conditions, the transistorized Y parameter matrix of Yc Parametric Representation cold conditions

g _ds＝1/R _ds；|Yc|＝jωg _ds(C _gs+C _gd)-ω ²(C _gsC _gd+C _gsC _ds+C _gdC _ds)。

In such scheme, transistorized suitable bias condition during definite extraction dead resistance described in step 2, comprises the following steps:

Step 21: press under bias condition certain leakage, scanning grid voltage, obtains direct current transfer characteristics, utilizes linear zone extrapolation method to obtain threshold voltage V _th;

Step 22: at cold condition V _dsunder=0V, take frequency as the first variable, grid voltage is that the second variable scans, and the scope of grid voltage can be V _th-2V<V _gs<V _th+ 0.5V, obtains cold conditions S parameter result under one group of different grid voltage;

Step 23: according to cold conditions S parameter result, the parasitic parameter that goes embedding testing weld pad and metal interconnection wire to introduce, is converted to Y parameter afterwards, obtains Yc under one group of different grid voltage ₂₂real part result.When frequency is enough low, intrinsic capacity and channel resistance show very large resistance value, now can ignore the impact of dead resistance on Y parameter, obtain:

wherein: | Zc|=Zc ₁₁zc ₂₂-Zc ₁₂zc ₂₁

At low frequency Freq=1GHz place, record Yc ₂₂the value of real part, draws Yc ₂₂real part is about the relation curve of grid voltage, and grid voltage is larger, and channel resistance is subject to the modulation of grid voltage and diminishes, and utilizes like this error of cold conditions Z parameter extraction dead resistance to become large, therefore at Yc ₂₂it is the suitable displacement zone of extracting transistor parasitic resistance that the grid voltage that real part starts occur to rise be take lower area, determines Yc ₂₂grid voltage value when real part starts to occur rising is Vh;

Step 24: the bias condition that obtains extracting transistor parasitic resistance is: V _ds=0V and V _gs=Vh-Vo, the engineering surplus that described Vo representative is introduced.

In such scheme, the extraction dead resistance parameter described in step 3 comprises the following steps:

Step 31: the bias condition according to the extraction transistor parasitic resistance arriving, utilize the S parameter under described bias condition, the parasitic parameter that goes embedding testing weld pad and metal interconnection wire to introduce, is converted to Y parameter afterwards, utilizes the imaginary part of Y parameter to extract the transistorized C of cold conditions _gs, C _gd, C _ds, utilize Yc ₂₂the real part result of low frequency is extracted g _ds, concrete fitting formula is as follows:

a)-imag((Yc ₁₂+Yc ₂₁)/2)＝ω×C _gd

b)imag(Yc ₁₁)-ω·C _gd＝ω×C _gs

c)imag(Yc ₂₂)-ω·C _gd＝ω×C _ds

d)real(Yc22)·ω＝ω×gds| _ω→0

Step 32: remove channel resistance for the impact of cold conditions Zc parameter, by following matrixing formula:

$\left[\begin{array}{cc}{\mathrm{<figure-callout\; id="11"\; label="Zr"\; filenames="HDA0000423066960000031.png,HDA0000423066960000041.png"\; state="\{\{state\}\}">Zr</figure-callout>}}_{11}& {\mathrm{<figure-callout\; id="12"\; label="Zr"\; filenames="HDA0000423066960000022.png,HDA0000423066960000023.png"\; state="\{\{state\}\}">Zr</figure-callout>}}_{12}\\ {\mathrm{Zr}}_{21}& {\mathrm{<figure-callout\; id="22"\; label="Zr"\; filenames="HDA0000423066960000031.png,HDA0000423066960000041.png"\; state="\{\{state\}\}">Zr</figure-callout>}}_{22}\end{array}\right]=\left[\begin{array}{cc}{\mathrm{Zc}}_{11}-\frac{g_{\mathrm{ds}}+\mathrm{j\&omega;}(C_{\mathrm{gd}}+C_{\mathrm{ds}})}{\left|\mathrm{Yc}\right|}& {\mathrm{Zc}}_{12}-\frac{\mathrm{j\&omega;}{C}_{\mathrm{gd}}}{\left|\mathrm{Yc}\right|}\\ {\mathrm{Zc}}_{21}-\frac{\mathrm{j\&omega;}{C}_{\mathrm{gd}}}{\left|\mathrm{Yc}\right|}& {\mathrm{Zc}}_{22}-\frac{\mathrm{j\&omega;}(C_{\mathrm{gs}}+C_{\mathrm{gd}})}{\left|\mathrm{Yc}\right|}\end{array}\right]$

Wherein: Zr Parametric Representation is removed the Z parameter matrix after channel resistance.

Step 33: utilize the real part linear fit of Zr parameter to obtain the value of dead resistance, concrete fitting formula is as follows:

a)real((Zr ₁₂+Zr ₂₁)/2)·ω ²＝ω ²×R _s

b)real(Zr ₁₁)·ω ²＝ω ²×(R _g+R _s)

c)real(Zr ₂₂)·ω ²＝ω ²×(R _d+R _s)

In such scheme, described in step 4, go embedding dead resistance, obtain transistor intrinsic Y parameter, by following matrixing formula, realize:

$\left[\begin{array}{cc}{\mathrm{Zin}}_{11}& {\mathrm{Zin}}_{12}\\ {\mathrm{Zin}}_{21}& {\mathrm{Zin}}_{22}\end{array}\right]=\left[\begin{array}{cc}{\mathrm{Zr}}_{11}-R_g-R_s& {\mathrm{Zr}}_{12}-R_s\\ {\mathrm{Zr}}_{21}-R_s& {\mathrm{Zr}}_{22}-R_d-R_s\end{array}\right]$

Wherein: Zin Parametric Representation removes the intrinsic Z parameter matrix after embedding dead resistance.

In such scheme, analytic expression and curve according to the small-signal model equivalent electrical circuit of the MOSFET of III-V family described in step 5 extract intrinsic parameters, are the Y parameter analytic expressions according to intrinsic pin network, comprise following concrete fitting formula:

a)-imag(Yin ₁₂)＝ω×C _gd

$b)\frac{\mathrm{imag}({\mathrm{Yin}}_{11}+{\mathrm{Yin}}_{12})}{1+\mathrm{real}{({\mathrm{Yin}}_{11}+{\mathrm{Yin}}_{12})}^2/\mathrm{imag}{({\mathrm{Yin}}_{11}+{\mathrm{Yin}}_{12})}^2}=\mathrm{\&omega;}\&times;C_{\mathrm{gs}}$

$c)\mathrm{real}({\mathrm{Yin}}_{11}+{\mathrm{Yin}}_{12})={\mathrm{\&omega;}}^2\&CenterDot;{\mathrm{<figure-callout\; id="2"\; label="C\; gs"\; filenames="HDA0000423066960000023.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{gs}}^{}\&times;R_{\mathrm{gs}}$

d)(Yin ₂₁-Yin ₁₂)·(1+j·ω·C _gs·R _gs)＝g _m×e ^-j·ω·τ

e)imag(Yin ₂₂+Yin ₁₂)＝ω×C _ds

f)real(Yin ₂₂+Yin ₁₂)·ω＝ω×1/R _ds

Wherein: Yin Parametric Representation removes the intrinsic Y parameter matrix after embedding dead resistance;

Pass through Yin ₁₂imaginary part (imag (Yin ₁₂)) obtain gate leakage capacitance C with the linear relationship matching of angular velocity (ω) _gd; According to Yin ₁₁+ Yin ₁₂real part and ω ²* C _gs ²linear relationship extract grid source resistance R _gs, according to Yin ₁₁+ Yin ₁₂the linear relationship of actual situation portion and ω is extracted grid source capacitor C _gs; Then pass through Yin ₂₁-Yin ₁₂obtain mutual conductance g with the nonlinear relationship Optimal Fitting of ω _mwith time delay factor τ; Finally utilize respectively Yin ₂₂+ Yin ₁₂extract channel resistance R with the linear relationship matching of real part and imaginary part and ω _dswith drain-source capacitor C _ds.

(3) beneficial effect

Compared with prior art, technique scheme has the following advantages:

1) from the physical layer of device, set up small-signal model equivalent topologies structure, propose to be applicable to the parameter direct extraction method of the MOSFET of III-V family types of devices, for small-signal modeling and the parameter extraction of new material and new construction device, provide suitable reference;

2) utilize direct current transfer characteristics for foundation, by the research of output Y parameter, the method for the suitable bias point of transistor while obtaining extracting dead resistance, has avoided the error of blindly selecting cold conditions bias condition to introduce;

3) when extracting dead resistance parameter, the impact of having removed channel resistance, has improved the degree of accuracy of dead resistance parameter result, and then has improved the confidence level of intrinsic parameters;

4) utilize the direct matching Y parameter of thought of curve, obtain parameter value more accurately, the method of calculating by analytic expression than prior art, technique scheme can obtain definite intrinsic parameters value rather than with the function of frequency dependence, thereby this extracting method is without the physical significance of carrying out again parameter value that optimizing process obtains and more meet device itself in addition.

Accompanying drawing explanation

Fig. 1 is according to the MOSFET of the III-V family device architecture of the embodiment of the present invention and small-signal model schematic diagram;

Fig. 2 is for directly to extract process flow diagram according to the MOSFET of the III-V family small-signal model parameter of the embodiment of the present invention;

Fig. 3 is the equivalent electrical circuit when the cold condition according to the MOSFET of the III-V family device of the embodiment of the present invention;

Fig. 4 a is according to Yc under the different grid voltages of the embodiment of the present invention ₂₂real part result is about the curve of frequency;

Fig. 4 b is the Yc according to the embodiment of the present invention ₂₂real part result is the relation curve about grid voltage at low frequency 1GHz place;

Fig. 5 is the fitting effect in cold condition extraction dead resistance parameter according to the embodiment of the present invention;

Fig. 6 a is the transistor intrinsic Y parameter real part fitting result chart according to the embodiment of the present invention;

Fig. 6 b is the transistor intrinsic Y parameter imaginary part fitting result chart according to the embodiment of the present invention;

Fig. 7 a and Fig. 7 b are the transistorized S parameter fitting design sketch according to the embodiment of the present invention, and wherein level and smooth solid line represents equivalent electrical circuit simulation result.

Embodiment

For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.

The small-signal model parameter direct extraction method of this III-V MOSFET of family provided by the invention, to go embedding by pad and metal interconnection wire, utilize transistor DC transfer characteristics and cold conditions S parameter to determine the suitable bias condition while extracting transistor parasitic resistance, then under this bias condition, remove channel resistance impact, linear fit extracts dead resistance parameter, finally go embedding dead resistance, utilize small-signal model equivalent electrical circuit and the curve of the MOSFET of III-V family to extract intrinsic parameters, the method specifically comprises the following steps:

Step 1: utilize the parasitic parameter that goes embedding testing weld pad and metal interconnection wire to introduce in chip architecture;

Step 2: according to the cold conditions S parameter of transistorized direct current transfer characteristics, the transistorized small-signal equivalent circuit of cold conditions and different grid voltages, determine transistorized suitable bias condition while extracting dead resistance;

Step 3: under above-mentioned bias condition, remove the impact of channel resistance, extract dead resistance parameter;

Step 4: go embedding dead resistance, obtain transistor intrinsic Y parameter;

Step 5: extract intrinsic parameters according to analytic expression and the curve of the small-signal model equivalent electrical circuit of the MOSFET of III-V family.

Wherein, the small-signal model equivalent electrical circuit of the described MOSFET of III-V family comprises five resistance, three electric capacity and a voltage-controlled current source, wherein: gate resistance (R _g) relevant with oxide layer contact material on grid, by the distribution losses effect of grid metal, formed; Source/leakage resistance (R _s, R _d) by metal-semiconductor contact resistance and semi-conductive bulk resistor two parts, formed; Grid source electric capacity (C _gs) and gate leakage capacitance (C _gd) the electric discharge charging process of indicator corresponding region, wherein comprised the edge effect between grid and source/leakage, grid leak resistance (R _gs) the non-accurate state effect of indicator gate leakage capacitance charge and discharge process; Channel resistance (R _ds) to derive from drain-source current be not really saturated with leak pressing, C _dsrepresent capacity effect between the static lower source leakage of electricity; Intrinsic transconductance (g _m) representing that grid voltage is to the modulation of channel current or control ability, parameter τ refers to the time delay factor.

The transistorized small-signal equivalent circuit of cold conditions described in step 2 comprises four resistance and three electric capacity, and described cold conditions refers to that device leaks the bias state without pressure drop, i.e. V in source _ds=0V; Under cold condition, transistorized channel current can be ignored, be similar to and think that grid voltage is not to the modulation of raceway groove or control ability, the difference of the transistorized small-signal equivalent circuit of cold conditions and non-cold conditions transistor small-signal equivalent circuit is not have voltage controlled current source part, and corresponding Z parameter can be write as following expression:

${\mathrm{<figure-callout\; id="11"\; label="Zc"\; filenames="HDA0000423066960000031.png,HDA0000423066960000041.png"\; state="\{\{state\}\}">Zc</figure-callout>}}_{11}=\frac{g_{\mathrm{ds}}+\mathrm{j\&omega;}(C_{\mathrm{gd}}+C_{\mathrm{ds}})}{\left|\mathrm{Yc}\right|}+R_g+R_s$

${\mathrm{<figure-callout\; id="12"\; label="Zc"\; filenames="HDA0000423066960000022.png,HDA0000423066960000023.png"\; state="\{\{state\}\}">Zc</figure-callout>}}_{12}=\frac{\mathrm{j\&omega;}{C}_{\mathrm{gd}}}{\left|\mathrm{Yc}\right|}+R_s$

${\mathrm{Zc}}_{21}=\frac{\mathrm{j\&omega;}{C}_{\mathrm{gd}}}{\left|\mathrm{Yc}\right|}+R_s$

${\mathrm{<figure-callout\; id="22"\; label="Zc"\; filenames="HDA0000423066960000031.png,HDA0000423066960000041.png"\; state="\{\{state\}\}">Zc</figure-callout>}}_{22}=\frac{\mathrm{j\&omega;}(C_{\mathrm{gs}}+C_{\mathrm{gd}})}{\left|\mathrm{Yc}\right|}+R_d+R_s$

Wherein: the transistorized Z parameter matrix of Zc Parametric Representation cold conditions, the transistorized Y parameter matrix of Yc Parametric Representation cold conditions

g _ds＝1/R _ds；|Yc|＝jωg _ds(C _gs+C _gd)-ω ²(C _gsC _gd+C _gsC _ds+C _gdC _ds)。

Transistorized suitable bias condition during definite extraction dead resistance described in step 2, comprises the following steps:

Step 21: press under bias condition certain leakage, scanning grid voltage, obtains direct current transfer characteristics, utilizes linear zone extrapolation method to obtain threshold voltage V _th;

Step 22: at cold condition V _dsunder=0V, take frequency as the first variable, grid voltage is that the second variable scans, and the scope of grid voltage can be V _th-2V<V _gs<V _th+ 0.5V, obtains cold conditions S parameter result under one group of different grid voltage; As shown in Figure 3, Fig. 3 is the equivalent electrical circuit of the III-V MOSFET of family device of the present invention when cold condition;

Step 23: according to cold conditions S parameter result, the parasitic parameter that goes embedding testing weld pad and metal interconnection wire to introduce, is converted to Y parameter afterwards, obtains Yc under one group of different grid voltage ₂₂real part result.When frequency is enough low, intrinsic capacity and channel resistance show very large resistance value, now can ignore the impact of dead resistance on Y parameter, obtain:

wherein: | Zc|=Zc ₁₁zc ₂₂-Zc ₁₂zc ₂₁

At low frequency Freq=1GHz place, record Yc ₂₂the value of real part, draws Yc ₂₂real part is about the relation curve of grid voltage, and grid voltage is larger, and channel resistance is subject to the modulation of grid voltage and diminishes, and utilizes like this error of cold conditions Z parameter extraction dead resistance to become large, therefore at Yc ₂₂it is the suitable displacement zone of extracting transistor parasitic resistance that the grid voltage that real part starts occur to rise be take lower area, determines Yc ₂₂grid voltage value when real part starts to occur rising is Vh;

Step 24: the bias condition that obtains extracting transistor parasitic resistance is: V _ds=0V and V _gs=Vh-Vo, the engineering surplus that described Vo representative is introduced.

Extraction dead resistance parameter described in step 3 comprises the following steps:

Step 31: the bias condition according to the extraction transistor parasitic resistance arriving, utilize the S parameter under described bias condition, the parasitic parameter that goes embedding testing weld pad and metal interconnection wire to introduce, is converted to Y parameter afterwards, utilizes the imaginary part of Y parameter to extract the transistorized C of cold conditions _gs, C _gd, C _ds, utilize Yc ₂₂the real part result of low frequency is extracted g _ds, concrete fitting formula is as follows:

a)-imag((Yc ₁₂+Yc ₂₁)/2)＝ω×C _gd

b)imag(Yc ₁₁)-ω·C _gd＝ω×C _gs

c)imag(Yc ₂₂)-ω·C _gd＝ω×C _ds

d)real(Yc22)·ω＝ω×gds| _ω→0

Step 32: remove channel resistance for the impact of cold conditions Zc parameter, by following matrixing formula:

$\left[\begin{array}{cc}{\mathrm{Zr}}_{11}& {\mathrm{<figure-callout\; id="12"\; label="Zr"\; filenames="HDA0000423066960000022.png,HDA0000423066960000023.png"\; state="\{\{state\}\}">Zr</figure-callout>}}_{12}\\ {\mathrm{Zr}}_{21}& {\mathrm{<figure-callout\; id="22"\; label="Zr"\; filenames="HDA0000423066960000031.png,HDA0000423066960000041.png"\; state="\{\{state\}\}">Zr</figure-callout>}}_{22}\end{array}\right]=\left[\begin{array}{cc}{\mathrm{Zc}}_{11}-\frac{g_{\mathrm{ds}}+\mathrm{j\&omega;}(C_{\mathrm{gd}}+C_{\mathrm{ds}})}{\left|\mathrm{Yc}\right|}& {\mathrm{Zc}}_{12}-\frac{\mathrm{j\&omega;}{C}_{\mathrm{gd}}}{\left|\mathrm{Yc}\right|}\\ {\mathrm{Zc}}_{21}-\frac{\mathrm{j\&omega;}{C}_{\mathrm{gd}}}{\left|\mathrm{Yc}\right|}& {\mathrm{Zc}}_{22}-\frac{\mathrm{j\&omega;}(C_{\mathrm{gs}}+C_{\mathrm{gd}})}{\left|\mathrm{Yc}\right|}\end{array}\right]$

Wherein: Zr Parametric Representation is removed the Z parameter matrix after channel resistance.

Step 33: utilize the real part linear fit of Zr parameter to obtain the value of dead resistance, concrete fitting formula is as follows:

a)real((Zr ₁₂+Zr ₂₁)/2)·ω ²＝ω ²×R _s

b)real(Zr ₁₁)·ω ²＝ω ²×(R _g+R _s)

c)real(Zr ₂₂)·ω ²＝ω ²×(R _d+R _s)

Described in step 4, go embedding dead resistance, obtain transistor intrinsic Y parameter, by following matrixing formula, realize:

$\left[\begin{array}{cc}{\mathrm{<figure-callout\; id="11"\; label="Zin"\; filenames="HDA0000423066960000031.png,HDA0000423066960000041.png"\; state="\{\{state\}\}">Zin</figure-callout>}}_{11}& {\mathrm{<figure-callout\; id="12"\; label="Zin"\; filenames="HDA0000423066960000022.png,HDA0000423066960000023.png"\; state="\{\{state\}\}">Zin</figure-callout>}}_{12}\\ {\mathrm{Zin}}_{21}& {\mathrm{<figure-callout\; id="22"\; label="Zin"\; filenames="HDA0000423066960000031.png,HDA0000423066960000041.png"\; state="\{\{state\}\}">Zin</figure-callout>}}_{22}\end{array}\right]=\left[\begin{array}{cc}{\mathrm{Zr}}_{11}-R_g-R_s& {\mathrm{Zr}}_{12}-R_s\\ {\mathrm{Zr}}_{21}-R_s& {\mathrm{Zr}}_{22}-R_d-R_s\end{array}\right]$

Wherein: Zin Parametric Representation removes the intrinsic Z parameter matrix after embedding dead resistance.

Analytic expression and curve according to the small-signal model equivalent electrical circuit of the MOSFET of III-V family described in step 5 extract intrinsic parameters, are the Y parameter analytic expressions according to intrinsic pin network, comprise following concrete fitting formula:

a)-imag(Yin ₁₂)＝ω×C _gd

$b)\frac{\mathrm{imag}({\mathrm{<figure-callout\; id="11"\; label="Yin"\; filenames="HDA0000423066960000031.png,HDA0000423066960000041.png"\; state="\{\{state\}\}">Yin</figure-callout>}}_{11}+{\mathrm{Yin}}_{12})}{1+\mathrm{real}{({\mathrm{<figure-callout\; id="11"\; label="Yin"\; filenames="HDA0000423066960000031.png,HDA0000423066960000041.png"\; state="\{\{state\}\}">Yin</figure-callout>}}_{11}+{\mathrm{Yin}}_{12})}^2/\mathrm{imag}{({\mathrm{<figure-callout\; id="11"\; label="Yin"\; filenames="HDA0000423066960000031.png,HDA0000423066960000041.png"\; state="\{\{state\}\}">Yin</figure-callout>}}_{11}+{\mathrm{Yin}}_{12})}^2}=\mathrm{\&omega;}\&times;C_{\mathrm{gs}}$

$c)\mathrm{real}({\mathrm{<figure-callout\; id="11"\; label="Yin"\; filenames="HDA0000423066960000031.png,HDA0000423066960000041.png"\; state="\{\{state\}\}">Yin</figure-callout>}}_{11}+{\mathrm{Yin}}_{12})={\mathrm{\&omega;}}^2\&CenterDot;{\mathrm{<figure-callout\; id="2"\; label="C\; gs"\; filenames="HDA0000423066960000023.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{gs}}^{}\&times;R_{\mathrm{gs}}$

d)(Yin ₂₁-Yin ₁₂)·(1+j·ω·C _gs·R _gs)＝g _m×e ^-j·ω·τ

e)imag(Yin ₂₂+Yin ₁₂)＝ω×C _ds

f)real(Yin ₂₂+Yin ₁₂)·ω＝ω×1/R _ds

Wherein: Yin Parametric Representation removes the intrinsic Y parameter matrix after embedding dead resistance;

Pass through Yin ₁₂imaginary part (imag (Yin ₁₂)) obtain gate leakage capacitance C with the linear relationship matching of angular velocity (ω) _gd; According to Yin ₁₁+ Yin ₁₂real part and ω ²* C _gs ²linear relationship extract grid source resistance R _gs, according to Yin ₁₁+ Yin ₁₂the linear relationship of actual situation portion and ω is extracted grid source capacitor C _gs; Then pass through Yin ₂₁-Yin ₁₂obtain mutual conductance g with the nonlinear relationship Optimal Fitting of ω _mwith time delay factor τ; Finally utilize respectively Yin ₂₂+ Yin ₁₂extract channel resistance R with the linear relationship matching of real part and imaginary part and ω _dswith drain-source capacitor C _ds.

Fig. 1 is use InGaAs MOSFET device physics structure and the small-signal model according to the embodiment of the present invention, and material structure comprises: GaAs substrate, AlGaAs cushion, InGaAs channel layer, InGaP barrier layer, Al ₂o ₃oxide layer, passivation layer etc., after concrete example the parameter extracting method of the device of this structure is described.

Fig. 2 directly extracts process flow diagram for the small-signal model parameter of the InGaAs MOSFET device according to the embodiment of the present invention, comprises the steps:

Step 1: test component and go the S parameter of embedding structure at sheet, utilize test result to remove the parasitic parameter that testing weld pad and metal interconnection wire are introduced, the accurate extraction of peripheral parasitic parameter can affect the accuracy of internal nonlinearity parameter.

Step 2: according to transistorized direct current transfer characteristics, the transistorized small-signal equivalent circuit of cold conditions and cold conditions S parameter, determine transistorized suitable bias condition while extracting dead resistance;

Measuring transistor DC transfer characteristics: it is 1V that drain voltage is set, grid voltage, in the interval scanning of-1V～3V, obtains transfer characteristic curve, and by linear zone extrapolation method, obtaining threshold voltage is 0.5V.Test transistor cold conditions S parameter: it is 0V that drain voltage is set, grid voltage be take 0.25V and is scanned as step-length in-2～1V interval, and the 100MHz of simultaneously take in 1GHz～40GHz interval obtains cold conditions S parameter result under one group of different grid voltage as step scan frequency.Then the parasitic parameter that goes scarfweld dish and metal interconnection wire to introduce, is converted to Y parameter afterwards, obtains Yc under one group of different grid voltage ₂₂real part result, the bias condition that finally obtains extracting transistor parasitic resistance is: V _ds=0V and V _gs=-0.5V.

Fig. 4 a is according to Yc under the different grid voltages of the embodiment of the present invention ₂₂real part result is about the curve of frequency, and the scope of grid voltage is-0.5V～0.5V to take 0.25V as step-length.Can find out as grid voltage V _gsduring=0V, Yc ₂₂real part in whole frequency range, start to occur ascendant trend.Fig. 4 b is the Yc according to the embodiment of the present invention ₂₂real part result is the relation curve about grid voltage at low frequency 1GHz place, determines Yc ₂₂real part starts to occur that the grid voltage value rising is 0V, is less than the region of 0V, Yc at grid voltage ₂₂real part is less, shows that channel resistance is enough large, minimum for the real part impact of cold condition Y parameter like this, therefore in this region, extracts dead resistance parameter comparatively accurate.

Step 3: under above-mentioned bias condition, remove the impact of channel resistance, extract dead resistance parameter;

Fig. 5 is the fitting effect in cold condition extraction dead resistance parameter according to the embodiment of the present invention, wherein level and smooth solid line or dotted line represent cold conditions equivalent electrical circuit S parameters simulation result, scatter diagram shape represents test data of experiment, as can be seen from the results, except appearring in high frequency treatment, some randomnesss affect the fitting effect of S parameter, all in all, in wider frequency range, fitting effect is better, and the dead resistance parameter of extraction meets the requirements.At cut-off region cold condition (Vgs=-0.5V, Vds=0V) time, intrinsic capacity and channel resistance extraction result are: Cds=13fF, Cgd=26.5fF, Cgs=24.6fF, Rds=10K, removing the dead resistance parameter obtaining after channel resistance impact is: Rs=4.1 Ω, Rg=1.34 Ω, Rd=7.4 Ω.

Step 4: go embedding dead resistance, obtain transistor intrinsic Y parameter;

Step 5: extract intrinsic parameters according to the thought of the analytic expression of small-signal model equivalent electrical circuit and curve.

Fig. 6 a is the transistor intrinsic Y parameter real part fitting result chart according to the embodiment of the present invention, Fig. 6 b is the transistor intrinsic Y parameter imaginary part fitting result chart according to the embodiment of the present invention, on the whole, the method that intrinsic correlation parameter extracts by direct matching has good confidence level, the process that does not need to carry out suboptimization again, the intrinsic parameters result of therefore extracting meets the physical significance of device itself simultaneously.Saturation region (Vgs=3V, Vds=2V) small-signal parameter extracts result: Cgs=98.2fF, Cgd=20.1fF, Cds=17.7fF, Rgs=1.72 Ω, Rds=278.7 Ω, gm=53.1mS, tau=0.1ps.

Fig. 7 a and Fig. 7 b are the transistorized S parameter fitting design sketch according to the embodiment of the present invention, and wherein level and smooth solid line represents equivalent electrical circuit simulation result, and scatter diagram shape represents test data of experiment; Wherein transistorized bias condition is that grid voltage is 3V, and drain voltage is 2V, sweep frequency 1GHz～40GHz, and step-length is 100MHz; The curve that can find out test and emulation overlaps substantially, illustrates that equivalent electrical circuit of the present invention has reflected the AC characteristic of InGaAs mosfet transistor well, so the method that parameter of the present invention is directly extracted has practicality well.

Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.

Claims (8)

1. The small-signal model parameter direct extraction method of the 1.Yi Zhong III-V MOSFET of family, it is characterized in that, the method is to go embedding by pad and metal interconnection wire, utilize transistor DC transfer characteristics and cold conditions S parameter to determine the suitable bias condition while extracting transistor parasitic resistance, then under this bias condition, remove channel resistance impact, linear fit extracts dead resistance parameter, finally go embedding dead resistance, utilize small-signal model equivalent electrical circuit and the curve of the MOSFET of III-V family to extract intrinsic parameters.
2. 2. the small-signal model parameter direct extraction method of the III-V MOSFET of family according to claim 1, is characterized in that, the method specifically comprises the following steps:

   Step 1: utilize the parasitic parameter that goes embedding testing weld pad and metal interconnection wire to introduce in chip architecture;

   Step 2: according to the cold conditions S parameter of transistorized direct current transfer characteristics, the transistorized small-signal equivalent circuit of cold conditions and different grid voltages, determine transistorized suitable bias condition while extracting dead resistance;

   Step 3: under above-mentioned bias condition, remove the impact of channel resistance, extract dead resistance parameter;

   Step 4: go embedding dead resistance, obtain transistor intrinsic Y parameter;

   Step 5: extract intrinsic parameters according to analytic expression and the curve of the small-signal model equivalent electrical circuit of the MOSFET of III-V family.
3. 3. the small-signal model parameter direct extraction method of the III-V MOSFET of family according to claim 1 and 2, it is characterized in that, the small-signal model equivalent electrical circuit of the described MOSFET of III-V family comprises five resistance, three electric capacity and a voltage-controlled current source, wherein: gate resistance (R _g) relevant with oxide layer contact material on grid, by the distribution losses effect of grid metal, formed; Source/leakage resistance (R _s, R _d) by metal-semiconductor contact resistance and semi-conductive bulk resistor two parts, formed; Grid source electric capacity (C _gs) and gate leakage capacitance (C _gd) the electric discharge charging process of indicator corresponding region, wherein comprised the edge effect between grid and source/leakage, grid leak resistance (R _gs) the non-accurate state effect of indicator gate leakage capacitance charge and discharge process; Channel resistance (R _ds) to derive from drain-source current be not really saturated with leak pressing, C _dsrepresent capacity effect between the static lower source leakage of electricity; Intrinsic transconductance (g _m) representing that grid voltage is to the modulation of channel current or control ability, parameter τ refers to the time delay factor.
4. 4. the small-signal model parameter direct extraction method of the III-V MOSFET of family according to claim 2, it is characterized in that, the transistorized small-signal equivalent circuit of cold conditions described in step 2 comprises four resistance and three electric capacity, described cold conditions refers to that device leaks the bias state without pressure drop, i.e. V in source _ds=0V; Under cold condition, transistorized channel current can be ignored, be similar to and think that grid voltage is not to the modulation of raceway groove or control ability, the difference of the transistorized small-signal equivalent circuit of cold conditions and non-cold conditions transistor small-signal equivalent circuit is not have voltage controlled current source part, and corresponding Z parameter can be write as following expression:

   

   

   

   

   Wherein: the transistorized Z parameter matrix of Zc Parametric Representation cold conditions, the transistorized Y parameter matrix of Yc Parametric Representation cold conditions

   g _ds＝1/R _ds；|Yc|＝jωg _ds(C _gs+C _gd)-ω ²(C _gsC _gd+C _gsC _ds+C _gdC _ds)。
5. 5. the small-signal model parameter direct extraction method of the III-V MOSFET of family according to claim 2, is characterized in that, transistorized suitable bias condition during definite extraction dead resistance described in step 2, comprises the following steps:

   Step 21: press under bias condition certain leakage, scanning grid voltage, obtains direct current transfer characteristics, utilizes linear zone extrapolation method to obtain threshold voltage V _th;

   Step 22: at cold condition V _dsunder=0V, take frequency as the first variable, grid voltage is that the second variable scans, and the scope of grid voltage can be V _th-2V<V _gs<V _th+ 0.5V, obtains cold conditions S parameter result under one group of different grid voltage;

   Step 23: according to cold conditions S parameter result, the parasitic parameter that goes embedding testing weld pad and metal interconnection wire to introduce, is converted to Y parameter afterwards, obtains Yc under one group of different grid voltage ₂₂real part result.When frequency is enough low, intrinsic capacity and channel resistance show very large resistance value, now can ignore the impact of dead resistance on Y parameter, obtain:

   

   wherein: | Zc|=Zc ₁₁zc ₂₂-Zc ₁₂zc ₂₁

   At low frequency Freq=1GHz place, record Yc ₂₂the value of real part, draws Yc ₂₂real part is about the relation curve of grid voltage, and grid voltage is larger, and channel resistance is subject to the modulation of grid voltage and diminishes, and utilizes like this error of cold conditions Z parameter extraction dead resistance to become large, therefore at Yc ₂₂it is the suitable displacement zone of extracting transistor parasitic resistance that the grid voltage that real part starts occur to rise be take lower area, determines Yc ₂₂grid voltage value when real part starts to occur rising is Vh;

   Step 24: the bias condition that obtains extracting transistor parasitic resistance is: V _ds=0V and V _gs=Vh-Vo, the engineering surplus that described Vo representative is introduced.
6. 6. the small-signal model parameter direct extraction method of the III-V MOSFET of family according to claim 2, is characterized in that, the extraction dead resistance parameter described in step 3 comprises the following steps:

   Step 31: the bias condition according to the extraction transistor parasitic resistance arriving, utilize the S parameter under described bias condition, the parasitic parameter that goes embedding testing weld pad and metal interconnection wire to introduce, is converted to Y parameter afterwards, utilizes the imaginary part of Y parameter to extract the transistorized C of cold conditions _gs, C _gd, C _ds, utilize Yc ₂₂the real part result of low frequency is extracted g _ds, concrete fitting formula is as follows:

   a)-imag((Yc ₁₂+Yc ₂₁)/2)＝ω×C _gd

   b)imag(Yc ₁₁)-ω·C _gd＝ω×C _gs

   c)imag(Yc ₂₂)-ω·C _gd＝ω×C _ds

   d)real(Yc22)·ω＝ω×gds| _ω→0

   Step 32: remove channel resistance for the impact of cold conditions Zc parameter, by following matrixing formula:

   

   Wherein: Zr Parametric Representation is removed the Z parameter matrix after channel resistance.

   Step 33: utilize the real part linear fit of Zr parameter to obtain the value of dead resistance, concrete fitting formula is as follows:

   a)real((Zr ₁₂+Zr ₂₁)/2)·ω ²＝ω ²×R _s

   b)real(Zr ₁₁)·ω ²＝ω ²×(R _g+R _s)

   c)real(Zr ₂₂)·ω ²＝ω ²×(R _d+R _s)?。
7. 7. the small-signal model parameter direct extraction method of the III-V MOSFET of family according to claim 2, is characterized in that, described in step 4, goes embedding dead resistance, obtains transistor intrinsic Y parameter, by following matrixing formula, realizes:

   Wherein: Zin Parametric Representation removes the intrinsic Z parameter matrix after embedding dead resistance.
8. 8. the small-signal model parameter direct extraction method of the III-V MOSFET of family according to claim 2, it is characterized in that, analytic expression and curve according to the small-signal model equivalent electrical circuit of the MOSFET of III-V family described in step 5 extract intrinsic parameters, be the Y parameter analytic expression according to intrinsic pin network, comprise following concrete fitting formula:

   a)-imag(Yin ₁₂)＝ω×C _gd

   

   

   d)(Yin ₂₁-Yin ₁₂)·(1+j·ω·C _gs·R _gs)＝g _m×e ^-j·ω·τ

   e)imag(Yin ₂₂+Yin ₁₂)＝ω×C _ds

   f)real(Yin ₂₂+Yin ₁₂)·ω＝ω×1/R _ds

   Wherein: Yin Parametric Representation removes the intrinsic Y parameter matrix after embedding dead resistance;

   Pass through Yin ₁₂imaginary part (imag (Yin ₁₂)) obtain gate leakage capacitance C with the linear relationship matching of angular velocity (ω) _gd; According to Yin ₁₁+ Yin ₁₂real part and ω ²* C _gs ²linear relationship extract grid source resistance R _gs, according to Yin ₁₁+ Yin ₁₂the linear relationship of actual situation portion and ω is extracted grid source capacitor C _gs; Then pass through Yin ₂₁-Yin ₁₂obtain mutual conductance g with the nonlinear relationship Optimal Fitting of ω _mwith time delay factor τ; Finally utilize respectively Yin ₂₂+ Yin ₁₂extract channel resistance R with the linear relationship matching of real part and imaginary part and ω _dswith drain-source capacitor C _ds.

Images