CN103594510A - 一种源端场板高电子迁移率晶体管 - Google Patents

一种源端场板高电子迁移率晶体管 Download PDF

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CN103594510A
CN103594510A CN201310611822.9A CN201310611822A CN103594510A CN 103594510 A CN103594510 A CN 103594510A CN 201310611822 A CN201310611822 A CN 201310611822A CN 103594510 A CN103594510 A CN 103594510A
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唐武
王云波
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University of Electronic Science and Technology of China
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    • H01L29/7786Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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    • H01ELECTRIC ELEMENTS
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    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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    • H01L29/7782Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material

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Abstract

本发明涉及微电子技术。本发明解决了现有AlGaN/GaN高电子迁移率晶体管沟道电场分布不均匀的问题,提供了一种源端场板高电子迁移率晶体管,其技术方案可概括为:一种源端场板高电子迁移率晶体管,与现有技术区别在于,其势垒层为:AlGaN第一势垒层及AlGaN第二势垒层,AlGaN第二势垒层上还具有氮化镓盖帽层及氮化硅钝化层,氮化镓盖帽层上设置源极金属、漏极金属及栅极金属,氮化硅钝化层设置在氮化镓盖帽层上,源极金属及漏极金属之间,所述氮化硅钝化层上靠近源极金属位置设置有源端场板。本发明的有益效果是,击穿电压更大,提高了输出功率,适用于高电子迁移率晶体管。

Description

一种源端场板高电子迁移率晶体管
技术领域
本发明涉及微电子技术,特别涉及氮化镓高电子迁移率晶体管的技术。
背景技术
氮化镓(GaN)与第一代和第二代半导体材料相比具有更优良的电学性能,它是一种宽带隙半导体材料,具有高的击穿电场强度、高饱和速度及高热稳定性等,优良性能使其得到了人们的极大关注和研究,其中研究最为广泛的是AlGaN/GaN(氮化铝镓/氮化镓)高电子迁移率晶体管(HEMT),适用于微波大功率器件。
AlGaN/GaN高电子迁移率晶体管是一种异质结场效应晶体管,它是利用具有很高迁移率的二维电子气(2-DEG)工作,其结构示意图如图1所示,包括衬底、氮化镓成核层、氮化镓缓冲层、氮化镓沟道层及AlGaN/GaN势垒层,氮化镓成核层设置在衬底上,氮化镓缓冲层设置在氮化镓成核层上,氮化镓沟道层设置在氮化镓缓冲层上,AlGaN/GaN势垒层设置在氮化镓沟道层上,AlGaN/GaN势垒层上还设置有源极金属、漏极金属及栅极金属。HEMT的功率特性是应用于大功率器件的重点,为了提高HEMT的输出功率,就需要提高击穿电压,而栅极电场集中效应导致器件提前击穿,当GaN HEMT在高的漏源偏压下时,沟道电力线集中指向栅极边缘,在栅极边缘形成电场峰值,沟道电场的不均匀分布使器件在较低漏压下便发生雪崩击穿,从而无法充分发挥GaN材料的高耐压优势。
发明内容
本发明的目的是要克服目前AlGaN/GaN高电子迁移率晶体管沟道电场分布不均匀的问题,提供一种源端场板高电子迁移率晶体管。
本发明解决其技术问题,采用的技术方案是,一种源端场板高电子迁移率晶体管,包括衬底,其特征在于,还包括氮化镓成核层、氮化镓缓冲层、氮化镓沟道层、AlGaN第一势垒层、AlGaN第二势垒层、氮化镓盖帽层及氮化硅钝化层,所述氮化镓成核层设置在衬底上,氮化镓缓冲层设置在氮化镓成核层上,氮化镓沟道层设置在氮化镓缓冲层上,AlGaN第一势垒层设置在氮化镓沟道层上,AlGaN第二势垒层设置在AlGaN第一势垒层上,氮化镓盖帽层设置在AlGaN第二势垒层上,氮化镓盖帽层上设置有源极金属、漏极金属及栅极金属,氮化硅钝化层设置在氮化镓盖帽层上,源极金属及漏极金属之间,所述氮化硅钝化层上靠近源极金属位置设置有源端场板。
具体的,衬底为碳化硅衬底。
进一步的,所述AlGaN第一势垒层中,Al原子与Ga原子的原子比例为0.6:0.4;所述AlGaN第二势垒层中,Al原子与Ga原子的原子比例为0.27:0.73。
具体的,所述衬底的厚度为10nm,氮化镓成核层的厚度为20nm,氮化镓缓冲层的厚度为2μm,氮化镓沟道层的厚度为12nm,AlGaN第一势垒层的厚度为10nm,AlGaN第二势垒层的厚度为10nm,氮化镓盖帽层的厚度为3nm,氮化硅钝化层的厚度为200nm。
再进一步的,所述栅极金属为镍和金制成,栅极金属与氮化镓盖帽层形成肖特基接触,源极金属及漏极金属从下往上由锑、铝、镍及金制成,源极金属及漏极金属与氮化镓盖帽层形成欧姆接触。
具体的,所述源端场板为镍或金,长度为4.5μm。
再进一步的,当源端场板为镍时,其厚度为20nm,当源端场板为金时,其厚度为200nm。
本发明的有益效果是,在本发明方案中,上述的一种源端场板高电子迁移率晶体管,相较于现有氮化镓高电子迁移率晶体管,其击穿电压更大,提高了输出功率,性能更优。
附图说明
图1为现有氮化镓高电子迁移率晶体管的结构示意图;
图2为本发明的一种源端场板高电子迁移率晶体管的结构示意图;
图3为本发明实施例中的一种源端场板高电子迁移率晶体管击穿电压随源端场板长度的变化曲线图;
图4为本发明实施例中的一种源端场板高电子迁移率晶体管击穿电压随氮化硅钝化层厚度的变化曲线图。
具体实施方式
下面结合实施例及附图,详细描述本发明的技术方案。
本发明所述的一种源端场板高电子迁移率晶体管由衬底、氮化镓成核层、氮化镓缓冲层、氮化镓沟道层、AlGaN第一势垒层、AlGaN第二势垒层、氮化镓盖帽层、源极金属、漏极金属、栅极金属及氮化硅钝化层组成,其中,氮化镓成核层设置在衬底上,氮化镓缓冲层设置在氮化镓成核层上,氮化镓沟道层设置在氮化镓缓冲层上,AlGaN第一势垒层设置在氮化镓沟道层上,AlGaN第二势垒层设置在AlGaN第一势垒层上,氮化镓盖帽层设置在AlGaN第二势垒层上,氮化镓盖帽层上设置有源极金属、漏极金属及栅极金属,氮化硅钝化层设置在氮化镓盖帽层上,源极金属及漏极金属之间,氮化硅钝化层上靠近源极金属位置设置有源端场板。
实施例
本例的一种源端场板高电子迁移率晶体管中,衬底的厚度为10nm,氮化镓成核层的厚度为20nm,氮化镓缓冲层的厚度为2μm,氮化镓沟道层的厚度为12nm,AlGaN第一势垒层的厚度为10nm,AlGaN第二势垒层的厚度为10nm,氮化镓盖帽层的厚度为3nm,氮化硅钝化层的厚度为200nm,其结构示意图如图2所示。
具体为:氮化镓成核层设置在衬底上,氮化镓缓冲层设置在氮化镓成核层上,氮化镓沟道层设置在氮化镓缓冲层上,AlGaN第一势垒层设置在氮化镓沟道层上,AlGaN第二势垒层设置在AlGaN第一势垒层上,氮化镓盖帽层设置在AlGaN第二势垒层上,氮化镓盖帽层上设置有源极金属、漏极金属及栅极金属,氮化硅钝化层设置在氮化镓盖帽层上,源极金属及漏极金属之间。
其中,AlGaN第一势垒层中,Al原子与Ga原子的原子比例为0.6:0.4,AlGaN第二势垒层中,Al原子与Ga原子的原子比例为0.27:0.73;衬底为碳化硅衬底;栅极金属为镍和金制成,栅极金属与氮化镓盖帽层形成肖特基接触,源极金属及漏极金属从下往上由锑、铝、镍及金制成,即锑层在最下方与氮化镓盖帽层相接触,其上为铝层,再上是镍层,最后为金层组成完整的源极金属和漏极金属,源极金属及漏极金属与氮化镓盖帽层形成欧姆接触,源极金属及漏极金属与氮化镓盖帽层形成欧姆接触;氮化硅钝化层上靠近源极金属位置还可设置源端场板;源端场板可以为镍或金,长度为4.5μm,当源端场板为镍时,其厚度为20nm,当源端场板为金时,其厚度为200nm。
击穿电压随源端场板长度的变化曲线图如图3所示,可见:当源端场板长度为0~3μm时,器件的击穿电压很低;随着源端场板长度增大,器件的击穿电压开始迅速增大,当源端场板长度为5.5μm时,器件的击穿电压达到最大值,约为955V;随着源端场板长度的继续增大,器件的击穿电压开始下降。其击穿电压随氮化硅钝化层厚度的变化曲线图如图4所示,可见:随着氮化硅钝化层厚度的增大,器件的击穿电压的变化是先增大后减小,氮化硅钝化层厚度为50nm时,击穿电压约为370V;随着氮化硅钝化层厚度的增大,器件的击穿电压迅速增大,在氮化硅钝化层厚度为0.2μm时器件的击穿电压达到了最大值,为985V;随后,击穿电压开始减小。具体可见,该氮化镓高电子迁移率晶体管可以具有更高的击穿电压,使输出功率提高,性能更优。

Claims (8)

1.一种源端场板高电子迁移率晶体管,包括衬底,其特征在于,还包括氮化镓成核层、氮化镓缓冲层、氮化镓沟道层、AlGaN第一势垒层、AlGaN第二势垒层、氮化镓盖帽层及氮化硅钝化层,所述氮化镓成核层设置在衬底上,氮化镓缓冲层设置在氮化镓成核层上,氮化镓沟道层设置在氮化镓缓冲层上,AlGaN第一势垒层设置在氮化镓沟道层上,AlGaN第二势垒层设置在AlGaN第一势垒层上,氮化镓盖帽层设置在AlGaN第二势垒层上,氮化镓盖帽层上设置有源极金属、漏极金属及栅极金属,氮化硅钝化层设置在氮化镓盖帽层上,源极金属及漏极金属之间,所述氮化硅钝化层上靠近源极金属位置设置有源端场板。
2.如权利要求1所述的一种源端场板高电子迁移率晶体管,其特征在于,衬底为碳化硅衬底。
3.如权利要求1所述的一种源端场板高电子迁移率晶体管,其特征在于,所述AlGaN第一势垒层中,Al原子与Ga原子的原子比例为0.6:0.4。
4.如权利要求1所述的一种源端场板高电子迁移率晶体管,其特征在于,所述AlGaN第二势垒层中,Al原子与Ga原子的原子比例为0.27:0.73。
5.如权利要求1所述的一种源端场板高电子迁移率晶体管,其特征在于,所述衬底的厚度为10nm,氮化镓成核层的厚度为20nm,氮化镓缓冲层的厚度为2μm,氮化镓沟道层的厚度为12nm,AlGaN第一势垒层的厚度为10nm,AlGaN第二势垒层的厚度为10nm,氮化镓盖帽层的厚度为3nm,氮化硅钝化层的厚度为200nm。
6.如权利要求1所述的一种源端场板高电子迁移率晶体管,其特征在于,所述栅极金属为镍和金制成,栅极金属与氮化镓盖帽层形成肖特基接触,源极金属及漏极金属从下往上由锑、铝、镍及金制成,源极金属及漏极金属与氮化镓盖帽层形成欧姆接触。
7.如权利要求1或2或3或4或5或6所述的一种源端场板高电子迁移率晶体管,其特征在于,所述源端场板为镍或金,长度为4.5μm。
8.如权利要求7所述的一种源端场板高电子迁移率晶体管,其特征在于,当源端场板为镍时,其厚度为20nm,当源端场板为金时,其厚度为200nm。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105097900A (zh) * 2014-05-08 2015-11-25 恩智浦有限公司 半导体器件及制造方法
CN110114862A (zh) * 2016-12-27 2019-08-09 住友化学株式会社 半导体衬底及电子器件

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