CN103594470A - Integrated circuit having a vertical power MOS transistor - Google Patents
Integrated circuit having a vertical power MOS transistor Download PDFInfo
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- CN103594470A CN103594470A CN201210568749.7A CN201210568749A CN103594470A CN 103594470 A CN103594470 A CN 103594470A CN 201210568749 A CN201210568749 A CN 201210568749A CN 103594470 A CN103594470 A CN 103594470A
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Abstract
The invention discloses an integrated circuit having a vertical power MOS transistor. The integrated circuit comprises a plurality of lateral devices and quasi vertical devices formed in a same semiconductor die. The quasi vertical devices include two trenches. A first trench is formed between a first drain/source region and a second drain/source region. The first trench comprises a dielectric layer formed in a bottom portion of the first trench and a gate region formed in an upper portion of the first trench. A second trench is formed on an opposite side of the second drain/source region from the first trench. The second trench is coupled between the second drain/source region and a buried layer, wherein the second trench is of the same depth as the first trench.
Description
The application is that the part of the title submitted on July 11st, 2012 U.S. Patent Application Serial Number 13/546,506 that is " Apparatus and Method forPower MOS Transistor " continues, and its content is hereby expressly incorporated by reference.
Technical field
Present invention relates in general to semiconductor applications, more specifically, relate to the integrated circuit with vertical power MOS transistor.
Background technology
For example, due to the raising of various electronic units (, transistor, diode, resistor, capacitor etc.) integration density, semicon industry has experienced fast development.To a great extent, this raising of integration density comes from dwindle (for example, reduction process node is to the sub-20nm node) of semiconductor technology node.Scaled along with semiconductor device, needs new technology to carry out the performance that maintains electronic unit generation upon generation of.For example, expect that transistorized low gate-to-drain electric capacity and low conduction impedance can meet the requirement of power application.In addition, be desirably in integrated Vertical power transistors and lateral direction power transistor on identical semiconductor element.
Along with the development of semiconductor technology, mos field effect transistor (MOSFET) has been used to current integrated circuit widely.MOSFET is voltage control device.When the grid to MOSFET applies, control voltage and control voltage while being greater than the threshold value of MOSFET, between the drain electrode of MOSFET and source electrode, build conduction.As a result, electric current flows between the drain electrode of MOSFET and source electrode.On the other hand, when control voltage is less than the threshold value of MOSFET, correspondingly end MOSFET.
MOSFET can comprise two large classes.A n channel mosfet, another kind is p channel mosfet.According to the difference of structure, MOSFET can also be divided into two subclasses, i.e. groove power MOSFET and lateral direction power MOSFET.In n raceway groove groove power MOSFET, p tagma is used to form raceway groove, and wherein raceway groove is coupling in and is formed on the source area on p tagma and is formed between the drain region under p tagma.In addition,, in groove power MOSFET, drain electrode and source electrode are placed in the opposite side of wafer.Can have and comprise and be formed on the drain electrode of groove power MOSFET and the groove structure of the gate electrode between source electrode.
Groove power MOSFET is known as vertical power mosfet conventionally.Due to low grid driving power, fast switch speed and low conduction impedance, vertical power mosfet has been widely used in high voltage and the application of high electric current.
Summary of the invention
According to an aspect of the present invention, a kind of semiconductor device is provided, comprise: the first vertical transistor, the firstth district that comprises the second conductivity on the substrate that is formed on the first conductivity, Second Region from the growth of the firstth district, be formed on the first conductivity 3rd district in Second Region, be formed on the first drain/source region of the second conductivity in San district, the first groove, the second drain/source region of the second conductivity and the second groove, wherein, the first groove comprises dielectric layer in the bottom that is formed on the first groove and is formed on the gate regions in the top of the first groove, the second drain/source region is formed in Second Region and the second drain/source region and the first drain/source region are positioned at the opposite side of the first groove, and the second groove is coupling between the second drain/source region and Second Region, the degree of depth of the second groove is identical with the degree of depth of the first groove, and a plurality of lateral transistors, be formed in the Second Region on substrate.
Preferably, the width of the second groove is greater than the width of the first groove.
Preferably, the second groove is configured to generate accumulation layer along the sidewall of the second groove.
Preferably, the firstth district is buried layer, and Second Region is epitaxial loayer, and San district is tagma.
Preferably, lateral transistor is selected from the group that comprises high-pressure N-shaped MOS transistor, high-voltage P-type MOS transistor, low pressure N-type MOS transistor, low pressure P type MOS transistor and their any combination.
Preferably, this semiconductor device also comprises the second vertical transistor, and the first vertical transistor and the second vertical transistor are shared the second groove.
Preferably, the second vertical transistor and the first vertical transistor are in parallel.
Preferably, gate regions is coupled to described the second groove.
Preferably, this semiconductor device also comprises: high pressure trap, be formed in Second Region, and wherein, Second Region is P type epitaxial loayer, and high pressure trap is N-type high pressure trap.
Preferably, this semiconductor device also comprises: a plurality of isolated areas, lateral transistor and the first vertical transistor are separated.
According to a further aspect in the invention, a kind of device is provided, comprise: the first vertical transistor, comprise the first drain/source region, first grid, the second drain/source region and the second groove, wherein, the first drain/source region has the first conductivity and is formed on the first semiconductor layer forming in substrate, first grid is formed in the first groove, the first groove comprises the dielectric layer that is formed on first grid below, the second drain/source region has the first conductivity, the first drain/source region and the second drain/source region are formed on the opposite side of first grid, and the second drain/source region is formed in the first semiconductor layer, the degree of depth of the second groove is identical with the degree of depth of the first groove, and the second groove and the first groove are formed on the opposite side of the second drain/source region, and a plurality of lateral transistors, be formed on similar the second semiconductor layer of the first semiconductor layer in, lateral transistor is selected from the group that comprises high-pressure N-shaped MOS transistor, high-voltage P-type MOS transistor, low pressure N-type MOS transistor, low pressure P type MOS transistor and their any combination.
Preferably, the first semiconductor layer is the first high pressure trap; And second semiconductor layer be the second high pressure trap, the property class of the first high pressure trap and the second high pressure trap is seemingly.
Preferably, the channel length of high-pressure N-shaped MOS transistor is scalable.
Preferably, lateral transistor and the first vertical transistor are shared N-type epitaxial loayer.
Preferably, lateral transistor and the first vertical transistor are formed in corresponding high-pressure N-shaped trap, and wherein, high-pressure N-shaped trap is shared P type epitaxial loayer.
According to another aspect of the invention, provide a kind of method, having comprised: on the substrate with the second conductivity, formed the buried layer with the first conductivity; Grown epitaxial layer on substrate; Formation extends into the first groove and second groove of epitaxial loayer and buried layer, and wherein, the first groove is identical with the degree of depth of the second groove, and the width of the second groove is greater than the width of the first groove; In the bottom of the first groove, form dielectric layer; In the top of the first groove, form first grid electrode; For a plurality of lateral transistors that are formed in substrate form gate electrode; By the Implantation with the second conductivity in the epitaxial loayer in the first side of the first groove to form tagma; On tagma in the first side of the first groove, form the first drain/source region; And form the second drain/source region on the epitaxial loayer in the second side of the first groove.
Preferably, the method also comprises: on substrate, growth has the epitaxial loayer of the second conductivity; And in epitaxial loayer, form the high pressure trap with the first conductivity.
Preferably, the method also comprises: in epitaxial loayer, form a plurality of deep traps with the second conductivity; And in each deep trap, form the high pressure trap with the first conductivity.
Preferably, the method also comprises: by dielectric deposition in the first groove and the second groove until the first groove is filled completely by dielectric material and the second groove is filled by dielectric material portion.
Preferably, the method also comprises: inject ion to be formed for drain electrode and the source area of lateral transistor.
Accompanying drawing explanation
In order more completely to understand the disclosure and advantage thereof, carry out in conjunction with the accompanying drawings as a reference now following description, wherein:
Fig. 1 shows according to the sectional view of semiconductor device of comprising of embodiment of accurate vertical trench MOS transistor;
Fig. 2 shows according to the sectional view of the semiconductor device that comprises a plurality of accurate vertical MOS transistors of embodiment;
Fig. 3 shows according to the sectional view of the semiconductor device that comprises accurate vertical MOS transistor of another embodiment;
Fig. 4 shows according to the sectional view of the semiconductor device that comprises a plurality of accurate vertical MOS transistors of another embodiment;
Fig. 5 shows the sectional view that forms the semiconductor device after N-type epitaxial loayer and NBL layer above substrate according to embodiment;
Fig. 6 shows according to semiconductor device shown in Fig. 5 of embodiment and on substrate, forms dielectric layer and the sectional view after semiconductor device applies a plurality of ion implantation technologies;
Fig. 7 shows according to semiconductor device shown in Fig. 6 of embodiment and on substrate, forms the sectional view after hard mask layer;
Fig. 8 shows according to semiconductor device shown in Fig. 7 of embodiment at the sectional view after dielectric layer and hard mask layer are applied suitable etch process;
Fig. 9 shows according to semiconductor device shown in Fig. 8 of embodiment at the sectional view after N-type epitaxial loayer application etch process;
Figure 10 shows according to semiconductor device shown in Fig. 9 of embodiment at the sectional view after the first groove and the second groove application dielectric medium depositing operation;
Figure 11 shows according to semiconductor device shown in Figure 10 of embodiment at the sectional view after oxide skin(coating) application etch process;
Figure 12 shows the sectional view apply hard mask removal technique to the end face of semiconductor device after according to semiconductor device shown in Figure 11 of embodiment;
Figure 13 shows and according to semiconductor device shown in Figure 12 of embodiment, in groove and on the end face of semiconductor device, forms gate dielectric sectional view afterwards;
Figure 14 shows according to semiconductor device shown in Figure 13 of embodiment and in groove, forms gate electrode layer and on the end face of semiconductor device, form the sectional view after a plurality of gate electrodes;
Figure 15 shows according to semiconductor device shown in Figure 14 of embodiment at the sectional view after the end face of semiconductor device is applied various ion implantation technologies; And
Figure 16-Figure 27 shows the intermediate steps that comprises the semiconductor device of accurate vertical trench MOS transistor 100 shown in Fig. 3 according to the manufacture of embodiment;
Unless otherwise, same numbers and symbology same section in different figure conventionally.Drafting figure to be so that the related content of each embodiment to be clearly described, but is not necessarily to scale.
Embodiment
Below discuss manufacture and the use of the present embodiment in detail.Yet, should be appreciated that, the disclosure provide many can in various specific environments, specialize can application invention concept.The specific embodiment of discussing is only the explanation of the manufacture of disclosure embodiment and the concrete mode of use, does not limit the scope of the present disclosure.
The disclosure is described with reference to the embodiment of specific environment, has accurate vertical power metal-oxide semiconductor (MOS) (MOS) transistor device and comprises high-voltage MOS transistor and the integrated circuit of a plurality of lateral MOS transistors of low voltage mos transistor.Yet embodiment of the present disclosure also can be applicable to various semiconductor device.Hereinafter, describe with reference to the accompanying drawings each embodiment in detail.
Fig. 1 shows according to the sectional view of semiconductor device of comprising of embodiment of accurate vertical trench MOS transistor.Semiconductor device 10 comprises Wu Ge district, that is, be used to form accurate vertical trench MOS transistor the first district 100, be used to form the high pressure NMOS part with scalable channel length Second Region 200, be used to form high voltage PMOS device tri-districts 300, be used to form low pressure nmos device tetra-districts 400 and be used to form low pressure PMOS device five districts 500.For example, by isolated area (, shallow trench isolation is from (STI) district 101), limit each district 100,200,300,400 and 500.Alternatively, can form field oxide as isolated area.
Accurate vertical trench MOS transistor 100 comprises the substrate 102 of the first conduction type.According to embodiment, the first conduction type is P type.Accurate vertical trench MOS transistor 100 also comprises the N-type buried layer (NBL) 104 being formed on substrate 102 and is formed on the N-type epitaxial loayer 106 on NBL layer 104.Accurate vertical trench MOS transistor 100 also comprises the first groove, and it comprises 110He gate regions, oxide region 112.As shown in Figure 1, gate regions 112 is formed on zoneofoxidation 110.,P+ district 126, P type body (PB) district 108 (being formed in N-type epitaxial loayer 106), Yi N+ district 122 and Er N+ district 124 that accurate vertical trench MOS transistor 100 also can comprise.
，P+ district 126 and Yi N+ district 122 are formed in PB district 108 as shown in Figure 1.Er N+ district 124 is formed in N-type epitaxial loayer 106.According to embodiment, Yi N+ district 122 is source areas of accurate vertical trench MOS transistor 100.Er N+ district 124 is drain regions of accurate vertical trench MOS transistor 100.PB district 108 is coupling in the source electrode of accurate vertical trench MOS transistor 100 and the raceway groove between drain electrode.As shown in Figure 1, Yi N+ district 122 and Er N+ district 124 are formed on the opposite side of gate regions 112.Er N+ district 124 is as drain region, and it is coupled to channel region (PB district 108) by N-type epitaxial loayer 106 and NBL floor 104.
Accurate vertical trench MOS transistor 100 comprises the second groove having with the first groove same depth.Particularly, the second groove comprises deep trench 114 and the accumulation layer (not shown) forming along the sidewall of deep trench 114.As shown in Figure 1, the second groove is formed adjacent with Er N+ district 124.According to embodiment, deep trench 114 can be electrically coupled to gate regions 112.When to gate regions 112 and deep trench 114 while applying grid-control voltage, grid-control voltage can attract most of charge carriers and generate accumulation layer (not shown) along the sidewall of deep trench 114.Accumulation layer can have most charge carriers.As a result, between NBL floor 104 and Er N+ district 124, set up Low ESR drain current conductive path.
As shown in Figure 1, although N-type epitaxial loayer 106 can be sent to Er N+ district 124 from NBL floor 104 by drain current, the impedance of N-type epitaxial loayer 106 is greater than the impedance of the accumulation layer forming along the sidewall of deep trench 114.By employing, be coupling in the accumulation layer between Er N+ district 124 and NBL floor 104, improved current delivery.In addition,, by coupling NBL floor 140 and Er N+ district 124, can from NBL layer 104, obtain drain current.As a result, the drain electrode of accurate vertical trench MOS transistor 100 can be placed with source electrode homonymy.
A favorable characteristics of accurate vertical MOS transistor 100 is that accurate vertical stratification shown in Fig. 1 can easily be integrated in horizontal manufacturing process.Another favorable characteristics of accurate vertical MOS transistor 100 is that the accumulation layer forming along the second trenched side-wall contributes to provide low conduction impedance raceway groove for drain current.As a result, although use accurate vertical stratification, also increased the conduction impedance of MOS transistor 100.
Fig. 1 also shows the semiconductor device 10 that comprises a plurality of transversal devices, and transversal device is integrated in identical Semiconductor substrate (P type substrate 102) with accurate vertical MOS transistor 100.High pressure NMOS part 200 comprises the dark P trap 202 being formed in N-type epitaxial loayer 106.Similarly, high voltage PMOS device 300 comprises dark P trap 302.Low pressure nmos device 400 and low pressure PMOS device 500 share dark P trap 402.As shown in Figure 1, dark P trap 202,302 and 402 is formed in N-type epitaxial loayer 106 and by N-type epitaxial loayer 106 parts between isolated area 101 and two adjacent dark P traps and is spaced from each other.Transversal device 200,300,400 and 500 can comprise other traps, drain/source region and gate electrode.The detailed manufacturing step of transversal device is described referring to Fig. 5 to Figure 15.
A favorable characteristics with accurate vertical MOS transistor 100 shown in Fig. 1 is that accurate vertical MOS structure can be integrated in same substrate with lateral MOS device.So, can reuse existing transversal device manufacturing process.Existing transversal device manufacturing process contributes to reduce the cost of manufacturing accurate vertical MOS transistor 100.
Fig. 2 shows according to the sectional view of the semiconductor device that comprises a plurality of accurate vertical MOS transistors of embodiment.Except deep trench is used to provide low conduction impedance raceway groove for the drain current of a plurality of accurate vertical MOS transistors, shown in the structure of semiconductor device 20 and Fig. 1, the structure of semiconductor device 10 is similar.Particularly, Fig. 2 shows the deep trench that low conduction impedance raceway groove is provided for two accurate vertical MOS transistors of parallel connection.Should be noted that deep trench can provide conducting channel for many accurate vertical MOS transistors, in order simply only to show two accurate vertical MOS transistors.
Fig. 3 shows according to the sectional view of the semiconductor device that comprises accurate vertical MOS transistor of another embodiment.Except N-type epitaxial loayer can be formed on the high pressure N trap replacement in P type epitaxial loayer, shown in the structure of semiconductor device 30 and Fig. 1, the structure of semiconductor device 10 is similar.Referring to Figure 16 to Figure 27, formation and the manufacturing step that semiconductor device 30 is detailed described.
Fig. 4 shows according to the sectional view of the semiconductor device that comprises a plurality of accurate vertical MOS transistors of another embodiment.Except N-type epitaxial loayer can be formed on the high pressure N trap replacement in P type epitaxial loayer, shown in the structure of semiconductor device 40 and Fig. 2, the structure of semiconductor device 20 is similar.
Fig. 5 to Figure 15 shows the intermediate steps that comprises the semiconductor device of accurate vertical trench MOS transistor 100 shown in Fig. 1 according to the manufacture of embodiment.Fig. 5 shows the sectional view that forms the semiconductor device after N-type epitaxial loayer, NBL layer and a plurality of isolated area above substrate according to embodiment.As shown in Figure 5, on P type substrate 102, form NBL layer 104.Particularly, in the upper left corner of P type substrate 102, form NBL layer 104.On NBL layer 104 and P type substrate 102, form N-type epitaxial loayer 106.As shown in Figure 5, can in N-type epitaxial loayer 106, form a plurality of isolated areas 101.
Although should be noted that the electrical conductance that Fig. 5 illustrates substrate 102 is P type, this is only example.Substrate 102 is N-type.The conduction type that it will be appreciated by those skilled in the art that other layers can change in response to the conduction type of substrate 102 and change.
Can form NBL layer 104 by inject N-type dopant materials (such as phosphorus etc.) to substrate 102.Alternatively, can form NBL layer 104 by diffusion technology.According to embodiment, the doping content of NBL layer 104 is about 10
19/ cm
3to about 10
21/ cm
3scope in.
From NBL layer 104 growth N-type epitaxial loayer 106.Can be by using the epitaxial growth that realizes N-type epitaxial loayer 106 such as any applicable semiconductor fabrication process of chemical vapor deposition (CVD), high vacuum chemical gas deposition (UHV-CVD) etc.According to embodiment, the doping content of N-type epitaxial loayer 106 is about 10
15/ cm
3to about 10
18/ cm
3scope in.
Isolated area 101 can be shallow trench isolation from (STI) district, and can form grooves and form with dielectric material filling groove well known in the art by etching N-type epitaxial loayer 106.Isolated area 101 can be filled with the dielectric material such as oxide material, high concentration plasma (HDP) oxide etc., and forms by conventional method well known in the art.
Fig. 6 shows according to semiconductor device shown in Fig. 5 of embodiment and above substrate, is forming dielectric layer and the sectional view after a plurality of ion implantation technologies to semiconductor device application.On N-type epitaxial loayer 106, form dielectric layer 602.Dielectric layer 602 can comprise oxide skin(coating).Can by any oxidation technology, (for example comprise oxide, H
2wet type in the surrounding environment of O, NO or their combination or dry type thermal oxidation) or by using tetraethoxysilane (TEOS) and oxygen to form dielectric layer 602 as the CVD technology of precursor.
As shown in Figure 6, in N-type epitaxial loayer 106, form three dark P traps 202,302 and 402.By isolated area and N-type epitaxial loayer 106, separate three dark P traps 202,302 and 402.According to embodiment, the doping content of dark P trap can be about 10
16/ cm
3to about 10
19/ cm
3scope in.Can form dark P trap by the p-type alloy injecting such as boron.Similarly, three high pressure N traps 204,304 and 404 are respectively formed in dark P trap 202,302 and 402.By with about 10
15/ cm
3to about 10
18/ cm
3the N-shaped alloy that doping content in scope is injected such as phosphorus forms high pressure N trap.
Fig. 6 also shows the 5V P trap 206 that is formed in high pressure N trap 204, is formed on P type double diffusion (PDD) district 306 in high pressure N trap 304 and is formed on 5V P trap 406 in high pressure N trap 404.According to embodiment, the doping content of 5V P trap can be about 10
15/ cm
3with about 10
18/ cm
3scope in.The doping content in PDD district 306 is about 10
15/ cm
3with about 10
18/ cm
3scope in.The p-type alloy that can inject such as boron forms 5V P trap and PDD district.
Fig. 7 shows according to semiconductor device shown in Fig. 6 of embodiment and on substrate, forms the sectional view after hard mask layer.According to embodiment, hard mask layer 702 is deposited on dielectric layer 602.Hard mask layer 702 can be formed by silicon nitride.Hard mask layer 702 is deposited on the top of dielectric layer 602 by suitable manufacturing technology (such as CVD etc.).
Fig. 8 shows according to semiconductor device shown in Fig. 7 of embodiment at the sectional view after dielectric layer and hard mask layer are applied suitable etch process.According to the position of the first groove of accurate vertical MOS transistor 100 (shown in Figure 1) and the second groove, come patterning hard mask layer 702 and dielectric layer 602.After this, carry out etch process (for example, reactive ion etching (RIE) or other dry ecthings, anisotropy wet etching or any other applicable anisotropic etching or Patternized technique) to form the opening 802 and 804 shown in Fig. 8.Should be noted that according to embodiment, the width of opening 804 is greater than the width of opening 802.
Fig. 9 shows according to semiconductor device shown in Fig. 8 of embodiment at the sectional view after N-type epitaxial loayer application etch process.To N-type epitaxial loayer 106, apply etch processs (such as RIE, dry ecthing, wet etching or any other applicable anisotropic etch techniques) to form groove 902 and groove 904.As shown in Figure 9, in identical manufacturing step, form the first groove 902 and the second groove 904.This one step of the first groove 902 and the second groove 904 is formed with the manufacturing cost that helps reduce accurate vertical MOS transistor 100.
As shown in Figure 9, etch process can etching penetrate N-type epitaxial loayer 106 partially-etched NBL layer 104.In addition the degree of depth that, Fig. 9 shows the first groove 902 is approximately equal to the degree of depth of the second groove 904.Should be noted that as shown in Figure 9, the width of the second groove 904 is greater than the width of the first groove 902.The second larger groove 904 contributes to maintain opening during follow-up oxide depositing operation relatively.Hereinafter with reference to Figure 10, describe oxide depositing operation in detail.
Figure 10 shows according to semiconductor device shown in Fig. 9 of embodiment at the sectional view after the first groove and the second groove application dielectric medium depositing operation.As shown in figure 10, the first groove 902 shown in dielectric layer 1002 blank maps 9, but be partially filled the second groove 904.After dielectric medium depositing operation, in the second groove 904, can there is opening 1004.Described in Fig. 9, the width of the second opening 904 is greater than the width of the first opening 902.As a result, by controlling dielectric medium depositing operation, dielectric layer 1002 can be partially filled the second groove 904.
According to embodiment, dielectric layer 1002 can be formed by oxide.In whole specification, dielectric layer 1002 is called as oxide skin(coating) 1002 alternatively.By utilizing applicable heat treatment technics, wet processed technology or forming oxide skin(coating) 1002 such as the deposition technique of PVD, CVD, ALD etc.Should be noted that oxide skin(coating) shown in Figure 10 is only example.Can use alternatively other dielectric materials, such as nitride, nitrogen oxide, high k material, their combination and their multilayer.
Figure 11 shows according to semiconductor device shown in Figure 10 of embodiment at the sectional view after oxide skin(coating) application etch process.Carry out etch process (such as RIE, anisotropy wet etching or any other applicable anisotropic dry etch) to remove the top of oxide skin(coating) in the first groove, thereby form the oxide skin(coating) 110 shown in Figure 11.
In addition, controlling etch process is completely removed the oxide skin(coating) in the second groove.In other words, the second groove does not have oxide.According to embodiment, the thickness of oxide skin(coating) shown in Figure 11 110 is H1.H1 arrives in the scope of about 5um at about 0.5um.Should be noted that the size of mentioning in whole specification is only example, and can become different values.Should also be noted that oxide skin(coating) shown in Figure 11 110 can be used as field plate (field plate), it contributes to reduce surface field.In addition the surface field reducing along oxide skin(coating) 110, can increase the rated voltage of accurate vertical MOS transistor 100.
Figure 12 shows the sectional view apply hard mask removal technique to the end face of semiconductor device after according to semiconductor device shown in Figure 11 of embodiment.As shown in figure 12, by applicable hard mask layer, remove technique (such as, wet etching process) and removed the hard mask layer shown in Figure 11 and oxide skin(coating).Technique is removed in end face application to semiconductor device, until expose N-type epitaxial loayer 106.
Figure 13 shows and according to semiconductor device shown in Figure 12 of embodiment, in groove and on the end face of semiconductor device, forms gate dielectric sectional view afterwards.As shown in figure 13, in the first groove, form gate dielectric 1302 in the second groove and on the end face of semiconductor device.Gate dielectric 1302 can be by forming such as oxide, nitride, nitrogen oxide, high k material, their combination and the conventional dielectric material of their multilayer.
According to embodiment, gate dielectric 1302 is oxide skin(coating)s.Can use applicable heat treatment technics, wet process technology or deposition technique (for example, PVD, CVD, ALD etc.) to form gate dielectric 1302.
Figure 14 shows according to semiconductor device shown in Figure 13 of embodiment and in groove, forms gate electrode layer and on the end face of semiconductor device, form the sectional view after a plurality of gate electrodes.By identical manufacturing process, gate regions 112, deep trench 114, gate electrode 208,308,408 and 508 can be filled with same material.
According to embodiment, gate regions 112, deep trench 114, gate electrode 208,308,408 and 508 can be formed by polysilicon.Can utilize low-pressure chemical vapor deposition (LPCVD) dopant deposition or un-doped polysilicon to form gate regions (for example, 112,208,308,408 and 508) and deep trench 114.According to another embodiment, gate regions (for example, 112,208,308,408 and 508) and deep trench 114 can be formed by metal material (such as titanium nitride, tantalum nitride, tungsten nitride, titanium, tantalum and/or their combination).Utilize applicable deposition technique (for example, ALD, CVD, PVD etc.) to form metal gate electrode layer.Above-mentioned deposition technique is known in ability, so does not discuss in literary composition.
Figure 15 shows according to semiconductor device shown in Figure 14 of embodiment at the sectional view after the end face of semiconductor device is applied various ion implantation technologies.As shown in figure 15, in N-type epitaxial loayer 106, form PB district 108.According to the doping content in embodiment ，PB district about 10
16/ cm
3with about 10
18/ cm
3scope in.
A plurality of spacer (not shown) can form their corresponding gate electrodes.Can on gate electrode and substrate, cover the one or more wall (not shown) of deposition and form distance piece.Wall can comprise SiN, nitrogen oxide, SiC, SiON, oxide etc. and can form by the common method such as chemical vapor deposition (CVD), plasma enhanced CVD, sputter and additive method known in the art.For example can carry out patterning wall by isotropism or anisotropic etching, thereby remove wall and form distance piece from the horizontal surface of structure.
Can pass through with about 10
19/ cm
3with about 10
21/ cm
3between the p-type alloy that injects such as boron of concentration form P+ district 126.On PB district 108, form Yi N+ district 122.According to embodiment, Yi N+ district 122 is as the source electrode of MOS transistor 100.Can pass through with about 10
19/ cm
3with about 10
21/ cm
3between the N-shaped alloy that injects such as phosphorus of concentration form source area.In addition, can on Yi N+ district 122, form source electrode contact (not shown).
Can pass through with about 10
19/ cm
3with about 10
21/ cm
3between the p-type alloy that injects such as boron of concentration form P+ district 126.P+ district 126 can contact the p-type body of MOS transistor 100.In order to eliminate bulk effect ，P+ district 126, can be coupled to Yi N+ district 122 (source electrode of MOS transistor 100) by source electrode contact (not shown).
On the end face of semiconductor device shown in Figure 15, form interlayer dielectric (ILD) layer (not shown).ILD layer can be formed by the silicate glass of doped silicon nitride, although can use alternatively other materials, such as phosphosilicate glass of doped with boron etc.Can in ILD layer, form by etch process contact openings (not shown).After etch process, retain a part for ILD layer and become grid-source class dielectric layer 132.In addition, electric conducting material is deposited in opening to form source electrode contact (not shown).
The N+He P+ district with the transversal device of gate electrode 208,308,408 and 508 can be formed by the manufacturing process identical with forming Yi N+ district 122,124He P+ district, Er N+ district 126.The formation in the formation in the N+He P+ district of transversal device and the N+He P+ district of accurate vertical MOS transistor 100 is similar, therefore, and for avoiding repetition further not discuss in detail at this.
Figure 16 to Figure 27 shows the intermediate steps that comprises the semiconductor device of accurate vertical trench MOS transistor 100 shown in Fig. 3 according to the manufacture of embodiment.Except the epitaxial loayer of N-type shown in Fig. 5 is formed on high pressure N trap in the P type epitaxial loayer of Figure 16 replaces, the manufacturing step shown in the manufacturing step shown in Figure 16 to Figure 27 and Fig. 5 to Figure 15 is similar.
As shown in figure 16, semiconductor device comprises a plurality of NBL layers 104,332,342 and 452 that are formed in substrate 102.Replace the N-type epitaxial loayer 106 shown in Fig. 5, P type epitaxial loayer 1602 is grown on substrate 102.The doping content of P type substrate is about 10
14/ cm
3to about 10
17/ cm
3scope in.
Figure 16 also shows a plurality of high pressure N traps 302,334,344 and 454 that are formed in P type epitaxial loayer 1602.High pressure N trap 302,334,344 and 454 doping content can be about 10
15/ cm
3to about 10
18/ cm
3scope in.Manufacturing process shown in Figure 16 to Figure 27, with similar above with reference to the manufacturing process shown in Fig. 5 to Figure 15, is not therefore discussed at this again.
Although described disclosure embodiment and advantage thereof in detail, should be appreciated that, can carry out various changes, replacement and change and do not deviate from the spirit and scope of the present disclosure that claims limit.
In addition, the application's scope is not intended to be limited to the specific embodiment of technique, mechanical device, material composition, instrument, method and the step described in explanation.Ability technical staff easily understands according to the disclosure, according to the disclosure, can utilize and the basic identical function of execution of corresponding embodiment described herein or technique, mechanical device, material composition, instrument, method or the step that realizes the current existing of basic identical result or develop in the future.Therefore, claims are intended to comprise in the scope of this technique, mechanical device, material composition, instrument, method or step.
Claims (10)
1. a semiconductor device, comprising:
The first vertical transistor, comprising:
Be formed on the firstth district of the second conductivity on the substrate of the first conductivity;
Second Region from described the firstth district growth;
Be formed on described the first conductivity 3rd district in described Second Region;
Be formed on the first drain/source region of described the second conductivity in described San district;
The first groove, comprising:
Be formed on the dielectric layer in the bottom of described the first groove; With
Be formed on the gate regions in the top of described the first groove;
The second drain/source region of described the second conductivity, is formed in described Second Region and described the second drain/source region and described the first drain/source region are positioned at the opposite side of described the first groove; With
The second groove, is coupling between described the second drain/source region and described Second Region, and the degree of depth of described the second groove is identical with the degree of depth of described the first groove; And
A plurality of lateral transistors, are formed in the described Second Region on described substrate.
2. semiconductor device according to claim 1, wherein:
The width of described the second groove is greater than the width of described the first groove.
3. semiconductor device according to claim 1, wherein:
Described the second groove is configured to generate accumulation layer along the sidewall of described the second groove.
4. semiconductor device according to claim 1, wherein:
Described the firstth district is buried layer;
Described Second Region is epitaxial loayer; And
Described San district is tagma.
5. semiconductor device according to claim 1, wherein:
Described lateral transistor is selected from the group that comprises high-pressure N-shaped MOS transistor, high-voltage P-type MOS transistor, low pressure N-type MOS transistor, low pressure P type MOS transistor and their any combination.
6. semiconductor device according to claim 1, also comprises:
The second vertical transistor, described the first vertical transistor and described the second vertical transistor are shared described the second groove.
7. semiconductor device according to claim 6, wherein:
Described the second vertical transistor and described the first vertical transistor are in parallel.
8. semiconductor device according to claim 1, wherein, described gate regions is coupled to described the second groove.
9. a device, comprising:
The first vertical transistor, comprising:
The first drain/source region, has the first conductivity, and described the first drain/source region is formed on the first semiconductor layer forming in described substrate;
First grid, is formed in described the first groove, and described the first groove comprises the dielectric layer that is formed on described first grid below;
The second drain/source region, has described the first conductivity, wherein:
Described the first drain/source region and described the second drain/source region are formed on the opposite side of described first grid; And
Described the second drain/source region is formed in described the first semiconductor layer; With
The second groove, wherein:
The degree of depth of described the second groove is identical with the degree of depth of described the first groove; And
Described the second groove and described the first groove are formed on the opposite side of described the second drain/source region; And
A plurality of lateral transistors, be formed on similar the second semiconductor layer of described the first semiconductor layer in, described lateral transistor is selected from the group that comprises high-pressure N-shaped MOS transistor, high-voltage P-type MOS transistor, low pressure N-type MOS transistor, low pressure P type MOS transistor and their any combination.
10. a method, comprising:
On the substrate with the second conductivity, form the buried layer with the first conductivity;
Grown epitaxial layer on described substrate;
Formation extends into the first groove and second groove of described epitaxial loayer and described buried layer, wherein:
Described the first groove is identical with the degree of depth of described the second groove; And
The width of described the second groove is greater than the width of described the first groove;
In the bottom of described the first groove, form dielectric layer;
In the top of described the first groove, form first grid electrode;
For a plurality of lateral transistors that are formed in substrate form gate electrode;
By the Implantation with described the second conductivity in the epitaxial loayer in the first side of described the first groove to form tagma;
On described tagma in the first side of described the first groove, form the first drain/source region; And
On epitaxial loayer in the second side of described the first groove, form the second drain/source region.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/588,070 US9130060B2 (en) | 2012-07-11 | 2012-08-17 | Integrated circuit having a vertical power MOS transistor |
| US13/588,070 | 2012-08-17 |
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| Publication Number | Publication Date |
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| CN103594470A true CN103594470A (en) | 2014-02-19 |
| CN103594470B CN103594470B (en) | 2016-10-05 |
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| CN103594470B (en) | 2016-10-05 |
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