CN103592631A - Radar signal control system and method - Google Patents
Radar signal control system and method Download PDFInfo
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- CN103592631A CN103592631A CN201210295477.8A CN201210295477A CN103592631A CN 103592631 A CN103592631 A CN 103592631A CN 201210295477 A CN201210295477 A CN 201210295477A CN 103592631 A CN103592631 A CN 103592631A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/35—Details of non-pulse systems
- G01S7/352—Receivers
- G01S7/354—Extracting wanted echo-signals
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/02—Systems using reflection of radio waves, e.g. primary radar systems; Analogous systems
- G01S13/0209—Systems with very large relative bandwidth, i.e. larger than 10 %, e.g. baseband, pulse, carrier-free, ultrawideband
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/35—Details of non-pulse systems
- G01S7/352—Receivers
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Abstract
The invention provides a radar signal control system and method. The system comprises: a differential clock signal generation unit for generating a first differential clock signal and a second differential clock signal which are synchronized, wherein the first differential clock signal serves as the working clock of an FPGA unit; the FPGA unit for generating a time-delay control word according to sampling parameters and sending the word to a time-delay unit, generating a receiving trigger pulse according to sampling starting signals, and receiving radar echo data from a sampling unit and forwarding the data to a control unit under the triggering of the receiving trigger pulse; a first time-delay channel for performing time delay on the second differential clock signal according to the time-delay control word inputted by the FPGA unit; and the sampling unit for performing sampling on radar echo signals by taking the time-delayed second differential clock signal as a sampling clock and forwarding the radar echo data obtained through sampling to the FPGA unit. By using the system and method provided by the invention, data acquisition at a variable time relative to a time reference can be realized.
Description
Technical field
The present invention relates to electron trade data acquisition and processing technology field, relate in particular to a kind of based on field programmable gate array radar signal control system and the method for (Field programmable Gate Array is called for short FPGA).
Background technology
In recent years, major natural disasters and accident take place frequently both at home and abroad, cause a tremendous loss of lives and economic loss, and life detection radar attracts great attention.Generally, transmit frequency band in 0.3GHz-3GHz time, ULTRA-WIDEBAND RADAR has good penetration capacity.Because ultra broadband life detection radar has advantages of that penetration capacity is strong, detection range is large and resolution is high, thereby obtained in practice increasing application.Data acquisition system (DAS) is as a key component of ultra broadband life detection radar, and its function is to control ultra-broadband signal generation unit produce ultra-broadband signal and radar echo signal is gathered, and directly affects the performance of radar.
Applicant finds that prior art radar signal control mode exists following technological deficiency: (1) cannot realize the data acquisition in the variable moment of relative time benchmark; (2) according to Shannon's sampling theorem, if adopt real-time sampling method to gather the ULTRA-WIDEBAND RADAR echoed signal in 0.3GHz-3GHz bandwidth range, data acquisition system (DAS) at least reaches the real-time sampling rate of 6GHz, such data acquisition system sampling rate is fixed, expensive and volume is larger, is not easy to apply.
Summary of the invention
(1) technical matters that will solve
For solving above-mentioned one or more problems, the invention provides a kind of radar signal control system and method.
(2) technical scheme
According to an aspect of the present invention, a kind of radar signal control system is provided, comprise: differential clock signal generation unit, for generation of synchronous first via differential clock signal and the second road differential clock signal, this first via differential clock signal is sent to FPGA unit as its work clock; Control module, for transmitting sampling parameter and sampling enabling signal to FPGA unit, and receives the radar return data that transmit from FPGA unit; FPGA unit, be connected with differential clock signal generation unit, control module, for producing time delay control word to delay unit according to sampling parameter, according to sampling enabling signal, produce and receive trigger pulse, and receiving under the triggering of trigger pulse, reception is from the radar return data of sampling unit, and forwards it to control module; Delay unit, be connected with FPGA unit, differential clock signal generation unit, for the signal of input being carried out to time delay according to the time delay control word receiving from FPGA unit, comprise: the first time delay passage, be connected with described differential clock signal generation unit, for the second road differential clock signal being carried out to time delay according to the time delay control word of being inputted by FPGA unit, wherein, delay < T, delay is the amount of delay of described time delay, and T is the sampling period of sampling clock in sampling unit; And sampling unit, its input end of analog signal is connected with receiving antenna, and for utilizing the second road differential clock signal after time delay as sampling clock, radar echo signal to be sampled, and the radar return data retransmission that sampling is obtained is to FPGA unit.
According to another aspect of the present invention, a kind of radar signal control method based on above-mentioned radar signal control system is also provided, the method is carried out by FPGA unit, comprise: steps A, the sampling parameter that reception control unit sends, this sampling parameter comprises: the sampling period is counted N, sampling number M and sampling interval Δ T; Step B, the sampling enabling signal that reception control unit is sent, initialization sampling number register and time delay control word register; Step C, delivers to delay unit by the value of time delay control word register; Step e, produces and receives trigger pulse, triggers the N point data that self read from sampling unit, and these N point data are stored; Step F, adds N by sampling number register value, judges whether sampling number register value has reached sampling number M, if reached, and execution step G, otherwise, execution step H; Step G, increases a stepping by time delay control word register value, and this stepping makes the amount of delay of the first time delay passage in delay unit increase Δ T, execution step C; Step H, reconfigures the M point data of storage, and the M point data after combination is delivered to PC104.
(3) beneficial effect
From technique scheme, can find out, radar signal control system of the present invention and method have following beneficial effect:
(1) adopt FPGA to write time delay control word to delay unit, control the time delay of delay unit the first time delay passage and the second time delay passage, thereby reach the data acquisition that realizes the variable moment of relative time benchmark;
(2) delay unit adopts the cascade of three binary channels programmable delay lines, the every programmable delay line time delay passage of realizing two 0-5.115ns able to programme, three cascades are able to programme realizes two 0-15.345ns time delay passages, can according to the reference time delay of system needs and time delay passage, choose the crystal oscillator of proper operation frequency, improve system flexibility;
(3) the time delay resolution of the binary channels programmable delay line adopting is 5ps, sampling unit can be programmed and be realized the time delay of 5ps stepping, life detection radar data acquisition system (DAS) can realize take one to many times data acquisitions that time delay resolution is sampling interval, thereby can be according to the bandwidth of ultra-broadband signal, programming realizes suitable sampling interval, when bandwidth is larger, can programme and realize less sampling interval, bandwidth hour, can programme and realize larger sampling interval, to carry out high-speed data acquisition;
(4) FPGA unit, sampling unit, delay unit and transformer unit etc. are integrated on the pcb board of a 20cm * 10cm, and volume is little and quality is light, can realize portable use.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of embodiment of the present invention radar signal control system;
Fig. 2 is the structural representation of delay unit in embodiment of the present invention radar signal control system;
The program flow diagram that Fig. 3 is the embodiment of the present invention radar signal control method carried out in FPGA unit.
[main element symbol description]
1-transformer unit; 2-sampling unit;
3-delay unit; 4-FPGA unit;
5-control module; 6-ultra-broadband signal generation unit;
7-Power Management Unit; 8-differential clock signal generation unit.
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in further detail.
It should be noted that, in accompanying drawing or instructions description, similar or identical part is all used identical figure number.And in the accompanying drawings, to simplify or convenient sign.Moreover the element or the implementation that do not illustrate in accompanying drawing or describe, be form known to a person of ordinary skill in the art in affiliated technical field.In addition, although the demonstration of the parameter that comprises particular value can be provided herein, should be appreciated that, parameter is without definitely equaling corresponding value, but can in acceptable error margin or design constraint, be similar to corresponding value.
In one exemplary embodiment of the present invention, a kind of radar signal control system has been proposed.As shown in Figure 1, the present embodiment radar signal control system comprises: differential clock signal generation unit 8, control module 5, FPGA unit 4, delay unit 3, ultra-broadband signal generation unit 6, sampling unit 2, transformer unit 1 and Power Management Unit 7.Wherein:
Differential clock signal generation unit 8, for generation of first via differential clock signal and the second road differential clock signal, this first via differential clock signal and the second road differential clock signal are synchronous signals, wherein this first via differential clock signal is sent to FPGA unit as its work clock, and the differential clocks input end that this second road differential clock signal is delivered to sampling unit 2 after the first time delay passage of delay unit 3 is as its sampling clock.
The first time delay passage, its control end is connected to FPGA unit 4, its input end is inputted the second road differential clock signal, its output terminal is connected to the sampling clock port of sampling unit, for the second road differential clock signal being carried out to a time delay in the clock period according to the time delay control word of being inputted by FPGA unit;
The second time delay passage, its control end is connected to FPGA unit 4, the transmitting trigger pulse of its input end input FPGA unit output, its output terminal is connected to ultra-broadband signal generation unit, for this transmitting trigger pulse being carried out to time delay according to the time delay control word of being inputted by FPGA unit.
Ultra-broadband signal generation unit, its input end is connected with the output terminal of delay unit the second time delay passage, for producing ultra-broadband signal according to it, and this ultra-broadband signal is gone out by antenna transmission.
In the present embodiment, FPGA unit carries out time delay by delay unit to the transmitting trigger pulse providing, thereby has realized the data acquisition in the variable moment of relative time benchmark.
As shown in Figure 1, differential clock signal generation unit 8 comprises crystal oscillator and single-ended transfer difference chip.Wherein, crystal oscillator is connected with pcb board by SMA connector, for generation of single-ended clock signal.Single-ended transfer difference chip is positioned on pcb board, generates the differential clock signal of two-way for the single-ended clock signal that crystal oscillator is produced.First via differential clock signal is delivered to FPGA unit 4 as the work clock of FPGA unit 4, and the differential clocks input end that the second road differential clock signal is delivered to sampling unit 2 after the first time delay passage of delay unit 3 is as its sampling clock.
In the present embodiment, the frequency of the unit clock signal that crystal oscillator produces is 100MHz.Certainly, also can change crystal oscillator according to the reference time delay of system works needs and delay unit, to produce the clock signal of higher frequency, as 250MHz clock signal, or the clock signal of lower frequency, as 75MHz clock signal, but low-limit frequency can not be lower than 65MHz, this is because delay unit maximum can time delay 15.345ns, the first time delay passage of delay unit only need be to the time delay within a clock period of the second road differential clock signal, therefore clock period maximum can be selected 15.345ns, corresponding minimum clock frequency is about 65MHz, this can make system works more flexible.
As shown in Figure 1, single-ended transfer difference integrated chip in transformer unit 1, sampling unit 2, delay unit 3, FPGA unit 4 and differential clock signal generation unit 8 is on the pcb board of a 20cm * 10cm, control module 5 is connected with pcb board by PC104 interface, ultra-broadband signal generation unit 6 is connected with pcb board by SMA connector with the crystal oscillator in differential clock signal generation unit 8, and Power Management Unit 7 is connected with pcb board with the crystal oscillator in ultra-broadband signal generation unit 6, differential clock signal generation unit 8 by electrical connection.The present invention is integrated in numerous logical blocks on a pcb board, and volume is little and quality is light, can realize portable use.
As shown in Figure 1, the programming Control end of delay unit 3 is connected with FPGA unit 4, comprises the first time delay passage and the second time delay passage.The amount of delay of the first time delay passage and the second time delay passage is controlled by programming Control end by FPGA unit 4.
As shown in Figure 2, delay unit 3 adopts three binary channels programmable delay line cascades that time delay resolution is 5ps.Passage 1,2 outputs of delay line 3-1 are connected with passage 1,2 inputs of delay line 3-2 respectively; Passage 1,2 outputs of delay line 3-2 are connected with passage 1,2 inputs of delay line 3-3 respectively, thereby, passage 1 common formation the first time delay passage of delay line 3-1,3-2 and 3-3, the passage 2 of delay line 3-1,3-2 and 3-3 forms the second time delay passage jointly.Certainly, can design as required the quantity of binary channels programmable delay line.
In the present embodiment, this binary channels programmable delay line is the SY89297U delay line that MICREL company produces.The all time delays that realizes 0-5.115ns able to programme of two passages of every binary channels programmable delay line, three SY89297U cascades are able to programme realizes two passage 0-15.345ns time delay.Certainly, the SY89297U chip in delay unit 3 can replace with other programmable delay line chips.
In the present embodiment, control module 5 can adopt PC104 chip.As shown in Figure 1, PC104 unit 5 is connected with pcb board by PC104 interface, in the mode of IO mouth, to FPGA unit, 4 transmits sampling parameters, as the sampling period is counted N, sampling number M, sampling interval Δ T, and sampling enabling signal.In addition, on PC104 unit 5, be also integrated with DMA chip, can from FPGA unit 4, read by dma mode radar return data.
In the present embodiment, sampling unit 2 adopts the ADS5463 chip of TI company, sampling resolution 12-bit, input bandwidth 2.3GHz, meet the bandwidth requirement of ultra-broadband signal, the sampling rate of ADS5463 chip is controlled by its sampled clock signal, reaches as high as 500MSPS, and ADS5463 converts the differential analog signal of input to differential digital signal.What ultra-broadband signal generation unit 6 produced is that pulse height is greater than 52V, and pulse width is 300ps, the undersuing of bandwidth 2GHz.
Radar signal control system based on above-mentioned, in another exemplary embodiment of the present invention, has also proposed a kind of radar signal control method, and the FPGA unit of the method in above-mentioned radar signal control system carried out, and comprising:
Steps A, the sampling parameter that reception control unit sends, this sampling parameter comprises: the sampling period is counted N, sampling number M and sampling interval Δ T;
Step B, the sampling enabling signal that reception control unit is sent, initialization sampling number register and time delay control word register, generally, be initialized as 0 by both;
Step C, delivers to delay unit by the value of time delay control word register;
Step D, produces transmitting trigger pulse, and this transmitting trigger pulse triggers ultra-broadband signal generation unit and produces ultra-broadband signal after the second time delay passage of delay unit, and wherein, the time delay of this second time delay passage is controlled by time delay control word and is fixed value;
Step e, produces and receives trigger pulse, triggers the N point data that self read from sampling unit, and these N point data are stored;
Step F, adds N by sampling number register value, judges whether sampling number register value has reached sampling number M, if reached, and execution step G, otherwise, execution step H;
Step G, increases a stepping by time delay control word register value, and this stepping makes the amount of delay of the first time delay passage in delay unit increase Δ T, execution step C;
In this step, in time delay control word register, only deposit the low 10 of time delay control word, if there are 3 programmable delay lines, in this step, in time delay control word register, deposited for controlling the low 10 place value sums of three groups of time delay control words of three programmable delay line passages 1.
Step H, reconfigures M point data, and the M point data after combination are sent to PC104 by dma mode, and data acquisition finishes.
Below data anabolic process of the present invention is described, in steps A, the sampling period is counted N, sampling number M and sampling interval Δ T, and these three parameters meet:
M＝N×1/(F×ΔT)；
The frequency of operation that wherein F is crystal oscillator, in the embodiment of the present invention, F is 100MHz.
In addition, by these three parameters, can determine that FPGA unit is to the number of times I of sampling unit reading out data, wherein I should equal M/N.
Suppose that the N point data that read for the i time are as follows: D
i1, D
i2, D
i3..., D
iN,, in step H, the data after M point data being reconfigured should be:
D
11, D
21, D
31..., D
11; D
12, D
22, D
32..., D
i2; D
13, D
23, D
33..., D
i3; D
1 (N-1), D
2 (N-1), D
3 (N-1)..., D
i (N-1); D
1N, D
2N, D
3N..., D
iN, M data altogether, wherein i=1,2,3 ..., I-1, I.
In the present embodiment, the second time delay communication channel delay value is fixed in 4 programmings of FPGA unit, controlling the first time delay communication channel delay value increases progressively as time delay step value by sampling interval, control ultra-broadband signal generation unit and with respect to time reference, at constant time lag place, produce ultra-broadband signal, controlling sampling unit increases progressively radar echo signal is sampled as time delay step value by sampling interval with respect to time reference, thereby realize high-speed data acquisition
Generally, 1/F≤L * Δ T ', wherein: Δ T ' is each passage maximum delay amount of binary channels programmable delay line, F is the sampling clock frequency of sampling unit, and Δ T=P * Δ t, wherein: Δ T is the sampling interval of radar signal control system, Δ t is the time delay resolution of programmable delay line, P is greater than 1 integer, and 1/F=Q *=Δ T, and Q is greater than 2 integer.
In step C, when the value of time delay control word register is between 0 to 1000, corresponding the first time delay communication channel delay amount 0 to 5ns, this value is low 10 to first delay line time delay control word, all the other low 10 of two delay line time delay control words all give 0, when the value of time delay control word register is between 1001 to 2000, corresponding the first time delay communication channel delay amount 5.005ns is to 10ns, give 1000 for low 10 of first delay line time delay control word, time delay control word register value deducts after 1000 low 10 to second delay line time delay control word, the 3rd low 10 of delay line time delay control word gives 0, when the value of time delay control word register is between 2001 to 3000, corresponding the first time delay communication channel delay amount 10.005ns is to 15ns, give 1000 for low 10 of first delay line time delay control word, give 1000 for low 10 of second delay line time delay control word, time delay control word register value deducts after 2000 low 10 to the 3rd delay line time delay control word, and high 10 of three delay line time delay control words give a fixed value all the time, be defaulted as 0, corresponding the second time delay communication channel delay amount is 0.
The delay unit that the device of take is mentioned in embodiment is example by three binary channels programmable delay lines, the every time delay that realizes 0-5.115ns able to programme, three SY89297U cascades are able to programme realizes 0-15.345ns time delay, and this binary channels programmable delay line time delay resolution is 5ps, can realize and take one to many times data acquisitions that time delay resolution is sampling interval, thereby can be according to the bandwidth of ultra-broadband signal, programming realizes suitable sampling interval, when bandwidth is larger, can programme and realize less sampling interval, bandwidth hour, can programme and realize larger sampling interval, thereby carry out flexibly, data acquisition at a high speed.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (12)
1. a radar signal control system, comprising:
Differential clock signal generation unit, for generation of synchronous first via differential clock signal and the second road differential clock signal, this first via differential clock signal is transferred into FPGA unit as its work clock, and this second road differential clock signal is transferred into delay unit;
Control module, for transmitting sampling parameter and sampling enabling signal to FPGA unit, and receives the radar return data that transmit from FPGA unit;
FPGA unit, be connected with described differential clock signal generation unit, control module, for producing time delay control word and this time delay control word be sent to delay unit according to sampling parameter, according to sampling enabling signal, produce and receive trigger pulse, and under the triggering of described reception trigger pulse, reception is from the radar return data of sampling unit, and forwards it to control module;
Delay unit, is connected with described FPGA unit, differential clock signal generation unit, for the signal of input being carried out to time delay according to the time delay control word receiving from FPGA unit, comprising:
The first time delay passage, be connected with described differential clock signal generation unit, for the second road differential clock signal being carried out to time delay according to the time delay control word of being inputted by FPGA unit, wherein, delay < T, delay is the amount of delay of described time delay, and T is the sampling period of sampling clock in sampling unit;
And, sampling unit, its input end of analog signal is connected with receiving antenna, and for utilizing the second road differential clock signal after time delay as sampling clock, radar echo signal to be sampled, and the radar return data retransmission that sampling is obtained is to FPGA unit.
2. radar signal control system according to claim 1, wherein:
Described FPGA unit, also for producing transmitting trigger pulse according to sampling enabling signal;
Described delay unit also comprises: the second time delay passage, is connected with described FPGA unit, for the transmitting trigger pulse of input being carried out to time delay according to the time delay control word of FPGA unit input;
Described radar signal control system also comprises: ultra-broadband signal generation unit, its input end is connected with the output terminal of delay unit the second time delay passage, for producing ultra-wideband radar signal according to transmitting trigger pulse, and this ultra-wideband radar signal is gone out by antenna transmission.
3. radar signal control system according to claim 2, wherein, described delay unit is comprised of L sheet binary channels programmable delay line;
The described first time delay passage of passage 1 common formation of this L sheet binary channels programmable delay line, passage 2 common formation the second time delay passages;
Described FPGA unit generates the L group time delay control word of corresponding L sheet binary channels programmable delay line, for each group time delay control word, its low T1 position is for controlling the amount of delay of corresponding binary channels programmable delay line passage 1, and its high T2 position is for the amount of delay of control channel 2.
4. radar signal control system according to claim 3, wherein, described binary channels programmable delay line and sampling unit meet:
1/F≤L * Δ T ', wherein, Δ T ' is each passage maximum delay amount of binary channels programmable delay line, the sampling clock frequency that F is sampling unit, and
Δ T=P * Δ t, wherein, Δ T is the sampling interval of radar signal control system, the time delay resolution that Δ t is programmable delay line, P is greater than 1 integer, and
1/F=Q * Δ T, wherein, Q is greater than 2 integer.
5. radar signal control system according to claim 4, wherein, described L=3, Δ T '=5.115ns, F > 65MHz, Δ t=5ps;
Figure place of each group time delay control word is 20, its low 10 for controlling the amount of delay of corresponding binary channels programmable delay line passage 1, its high 10 amount of delay for control channel 2.
6. radar signal control system according to claim 3, wherein, described binary channels programmable delay line is SY89297U delay line, and described control module is PC104 chip, and described sampling unit is ADS5463 chip.
7. according to the radar signal control system described in any one in claim 1 to 6, wherein, described differential clock signal generation unit comprises:
Crystal oscillator, for generation of single-ended clock signal;
Single-ended transfer difference chip, is connected with described crystal oscillator, for described single-ended clock signal being generated to the differential clock signal of two-way.
8. radar signal control system according to claim 7, also comprises:
Transformer unit, is arranged between sampling unit and receiving antenna, after the single-ended simulating signal from receiving antenna is converted to differential analog signal, delivers to sampling unit; And
Power Management Unit, is used to differential clock signal generation unit, FPGA unit, sampling unit and control module that voltage is provided respectively.
9. radar signal control system according to claim 8, wherein, the single-ended transfer difference chip of described transformer unit, sampling unit, delay unit, FPGA unit and differential clock signal generation unit is all integrated on a pcb board.
10. the radar signal control method based on radar signal control system described in any one in claim 1 to 6, the method is carried out by FPGA unit, comprising:
Steps A, the sampling parameter that reception control unit sends, this sampling parameter comprises: the sampling period is counted N, sampling number M and sampling interval Δ T;
Step B, the sampling enabling signal that reception control unit is sent, initialization sampling number register and time delay control word register;
Step C, delivers to delay unit by the value of time delay control word register;
Step e, produces and receives trigger pulse, triggers the N point data that self read from sampling unit, and these N point data are stored;
Step F, adds N by sampling number register value, judges whether sampling number register value has reached sampling number M, if reached, and execution step G, otherwise, execution step H;
Step G, increases a stepping by time delay control word register value, and this stepping makes the amount of delay of the first time delay passage in delay unit increase Δ T, execution step C;
Step H, reconfigures the M point data of storage, and the M point data after combination is delivered to PC104, and data acquisition finishes.
11. collecting methods according to claim 10, wherein, the described sampling period is counted N, and sampling number M and sampling interval Δ T meet:
M＝N×1/(F×ΔT)
Wherein, the frequency of operation that F is crystal oscillator.
12. collecting methods according to claim 11, wherein, in described step H, by the M point data of storage reconfigure into:
D
11、D
21、D
31、……、D
11；D
12、D
22、D
32、……、D
I2；D
13、D
23、D
33、……、D
I3；…………；D
1(N-1)、D
2(N-1)、D
3(N-1)、……、D
I(N-1)；D
1N、D
2N、D
3N、……、D
IN；
Wherein, the N point data that FPGA unit is read for the i time by sampling unit are: D
i1, D
i2, D
i3..., D
(i-1) N,, D
iN, wherein i=1,2,3 ..., I-1, I.
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| CN103728893A (en) * | 2013-12-31 | 2014-04-16 | 中国电子科技集团公司第二十二研究所 | High-precision time-sequence control circuit of ground penetrating radar |
| CN106537170A (en) * | 2014-07-17 | 2017-03-22 | 德州仪器公司 | Distributed radar signal processing in a radar system |
| CN109725305A (en) * | 2019-01-02 | 2019-05-07 | 公安部第一研究所 | A kind of ultra wideband radar system of Low Power High Performance |
| CN110658497A (en) * | 2018-06-29 | 2020-01-07 | 比亚迪股份有限公司 | Radar signal generation method and device and radar |
| CN111812592A (en) * | 2020-06-16 | 2020-10-23 | 南京云航信息技术有限公司 | Arbitrary waveform broadband radar intermediate frequency signal source |
| CN113885775A (en) * | 2021-10-26 | 2022-01-04 | 成都中科合迅科技有限公司 | ADC sampling self-adaptive adjusting signal delay system based on FPGA |
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| CN103728893A (en) * | 2013-12-31 | 2014-04-16 | 中国电子科技集团公司第二十二研究所 | High-precision time-sequence control circuit of ground penetrating radar |
| CN103728893B (en) * | 2013-12-31 | 2016-05-11 | 中国电子科技集团公司第二十二研究所 | A kind of GPR high accuracy sequential control circuit |
| US10627480B2 (en) | 2014-07-17 | 2020-04-21 | Texas Instruments Incorporated | Distributed radar signal processing in a radar system |
| CN106537170B (en) * | 2014-07-17 | 2019-04-12 | 德州仪器公司 | Distributed radar signal processing in radar system |
| CN106537170A (en) * | 2014-07-17 | 2017-03-22 | 德州仪器公司 | Distributed radar signal processing in a radar system |
| US11047950B2 (en) | 2014-07-17 | 2021-06-29 | Texas Instruments Incorporated | Distributed radar signal processing in a radar system |
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| CN110658497B (en) * | 2018-06-29 | 2021-07-20 | 比亚迪股份有限公司 | Radar signal generation method and device and radar |
| CN109725305A (en) * | 2019-01-02 | 2019-05-07 | 公安部第一研究所 | A kind of ultra wideband radar system of Low Power High Performance |
| CN111812592A (en) * | 2020-06-16 | 2020-10-23 | 南京云航信息技术有限公司 | Arbitrary waveform broadband radar intermediate frequency signal source |
| CN111812592B (en) * | 2020-06-16 | 2024-01-19 | 南京安麦森电子科技有限公司 | Arbitrary waveform broadband radar intermediate frequency signal source |
| CN113885775A (en) * | 2021-10-26 | 2022-01-04 | 成都中科合迅科技有限公司 | ADC sampling self-adaptive adjusting signal delay system based on FPGA |
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