CN103579730A - Balun and optimizing method thereof - Google Patents
Balun and optimizing method thereof Download PDFInfo
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- CN103579730A CN103579730A CN201210254316.4A CN201210254316A CN103579730A CN 103579730 A CN103579730 A CN 103579730A CN 201210254316 A CN201210254316 A CN 201210254316A CN 103579730 A CN103579730 A CN 103579730A
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- unblanced transformer
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Abstract
The invention discloses a balun and an optimizing method of the balun. The balun is integrated in a chip, the outlet phase difference of the balun is of an asymmetrical structure, and through adjustment of an output port of the balun, the purposes that component layout in the chip is optimized, external wiring of components or modules is reduced, and accuracy of the chip is improved can be achieved.
Description
Technical field
The present invention relates to a kind of balanced-to-unblanced transformer and optimization method thereof, particularly relate to a kind of balanced-to-unblanced transformer and optimization method thereof of core Embedded.
Background technology
Balun (balanced-to-unblanced transformer) is widely used in radio communication and cable communication.Its effect, except balanced-unbalanced conversion, also depends on form, the structure of Balun simultaneously, the impedance transformation of ratio such as can carry out 1: 1,4: 1,6: 1,9: 1,25: 1.
At present radio frequency chip transmitting receive path all needs Balun to carry out single-endedly turning both-end or both-end turns single-ended conversion to radiofrequency signal conventionally, or uses Balun based on 2 little advantages of inductance of Balun Area Ratio.Because radiofrequency signal is very sensitive on the various impacts of link, receiving terminal particularly, signal power is very faint, the model accuracy of Balun and the parasitic parameter of signal link have a great impact design, so the accurate extraction of the parasitic parameter of all devices in signal link is just become to the major issue of signal link in radio frequency chip.
Conventionally the Balun of core Embedded often carries out symmetric design for guaranteeing the symmetry of 2 paths, outlet differs 180 degree for symmetry, as shown in Figure 1, like this layout of chip is just required very high, chip area probably increases thus, because Balun symmetry need peripheral wiring and device in full accord, can not to certain line, carry out abnormity design separately, and symmetrical Balun area is generally very large, output pin is just far like this, between pin, be not suitable for placing other circuit, otherwise easily cause asymmetry problem, will between pin, form so the vacant area of bulk and form unnecessary waste.Therefore, for guaranteeing the optimization of the accurate and chip area of signal model, with regard to the necessary cabling to Balun, be optimized, under the prerequisite allowing in design, Balun is optimized, accurate extracting parameter is correct with assurance design afterwards, the consistency of test result after raising Design and manufacture, and then the market competitiveness of raising chip.
Summary of the invention
The deficiency existing for overcoming above-mentioned prior art, the present invention's object is to provide a kind of balanced-unbalanced transformer and optimization method thereof, it is adjusted by the delivery outlet to Balun, can reach the object of optimizing device layout in chip, reducing device or the outer cabling of module and raising chip accuracy.
For reaching above-mentioned and other object, the invention provides a kind of balanced-to-unblanced transformer, this balanced-to-unblanced transformer is in core Embedded, and the outlet of this balanced-to-unblanced transformer is unsymmetric structure.
Further, to take the inductance precision that meets this balanced-to-unblanced transformer design be prerequisite in the design of the outlet difference angle of this balanced-to-unblanced transformer.
Further, the design of the outlet difference angle of this balanced-to-unblanced transformer need meet optimization chip device layout and circuit design demand.
For reaching above-mentioned and other object, the invention provides a kind of optimization method of balanced-to-unblanced transformer, this balanced-to-unblanced transformer is in core Embedded, and the method comprises the steps:
Step 1, is designed to unsymmetric structure by the outlet of this balanced-to-unblanced transformer;
Step 3, carries out Electromagnetic Simulation to this balanced-to-unblanced transformer, extracts parasitic parameter; And
Step 4, carries out software emulation according to the parasitic parameter obtaining by this balanced-to-unblanced transformer substitution software, verifies and confirms whether designed balanced-to-unblanced transformer meets design requirement, and obtains required balance-imbalance converter.
If the balanced-to-unblanced transformer that this step 4 obtains does not meet design requirement, adjust the outlet difference angle of this balanced-to-unblanced transformer, and repeat this step 1 to this step 4, until the balanced-to-unblanced transformer that this step 4 obtains meets design requirement.
Compared with prior art, a kind of balanced-to-unblanced transformer of the present invention and optimization method thereof are by being adjusted into unsymmetrical by the delivery outlet of balanced-to-unblanced transformer, make its outside cabling can be different, can by turn round or the mode such as mask placement device by the two-way output squeezing of balanced-to-unblanced transformer to compared with small size, between pin, can be applicable to placing other circuit, reach the object of optimizing device layout in chip, reducing device or the outer cabling of module and raising chip accuracy.
Accompanying drawing explanation
Fig. 1 is the rough schematic view of the balanced-to-unblanced transformer of prior art;
Fig. 2 is the rough schematic view of the preferred embodiment of a kind of balanced-to-unblanced transformer of the present invention;
Fig. 3 is the schematic diagram of the two-way LQ value of balanced-unbalanced transformer in prior art;
Fig. 4 is the two-way LQ value schematic diagram of the preferred embodiment of a kind of balanced-unbalanced transformer of the present invention;
Fig. 5 is the flow chart of steps of the optimization method of a kind of balanced-to-unblanced transformer of the present invention.
Embodiment
Below, by specific instantiation accompanying drawings embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by content disclosed in the present specification.The present invention also can be implemented or be applied by other different instantiation, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications and change not deviating under spirit of the present invention.
Fig. 2 is the rough schematic view of the preferred embodiment of a kind of balanced-to-unblanced transformer of the present invention.As shown in Figure 2, a kind of balanced-to-unblanced transformer of the present invention, in core Embedded, the present invention is optimized for target with chip area, designing under the prerequisite that can tolerate (as met the inductance parameters precision of balanced-to-unblanced transformer (Balun) design, this specific embodiment is positive and negative 15%, but because different circuit requirements is different, so said inductance parameters precision is not limited to above-mentioned positive and negative 15% here), balanced-to-unblanced transformer (Balun) outlet is adjusted, make its outlet be adjusted into unsymmetric structure, outlet differs can be between 0～180 degree, meet optimization chip device layout and circuit design demand simultaneously.
In preferred embodiment of the present invention, the present invention is according to design requirement, for integrated inductor in chip, optimize cabling, after designing Balun, by simulation software, it is carried out to Electromagnetic Simulation, accurately extract its parasitic parameter, and then its substitution software is carried out to software emulation, to be met the Balun of demand, reach the object that improves chip performance and save area.
Take shown in Fig. 2, differ as the Balun of 90 degree be example, start is as shown in the Balun (as Fig. 1) that is designed to differ 180 degree, by carrying after parameter with electromagnetism simulation software, obtain result shown in Fig. 3, wherein 2 inductance of Balun are almost without any difference, meet design requirement, yet, in Fig. 3, two-way LQ value is very symmetrical, the LQ value symmetry of Fig. 3 show to need peripheral wiring and device in full accord, can not to certain line, carry out abnormity design separately, and find in the layout of module (layout), because chip internal module is numerous, for the space of each module assignment of cost-saving very limited, if be that the Balun of 180 degree puts layout according to differing, space is disorderly taken very large, cabling is not convenient for walking yet, so the present invention's preferred embodiment is used instead and differed is the Balun of 90 degree, by Electromagnetic Simulation software emulation, carry after ginseng, obtain result shown in Fig. 4, the LQ value of the present invention's Balun is asymmetric shows that outside cabling can be different, can by turn round or the mode such as mask placement device by two-way output squeezing to compared with small size, and keep the parameter of two-way in full accord at the last port of two-way output, be put in the circuit of actual use Balun and also can meet design requirement, so the present invention's preferred embodiment finally determines that with differing be the Balun of 90 degree.
Electromagnetic Simulation software is a lot, such as Aistic, and HFSS, Momentum, EMX etc., the Realization of Simulation process of different simulation softwares is different, and result is much the same, because these simulation softwares are all prior aries, at this, does not repeat one by one.
Fig. 5 is the flow chart of steps of the optimization method of a kind of balanced-to-unblanced transformer of the present invention.As shown in Figure 5, the optimization method of a kind of balanced-to-unblanced transformer of the present invention, comprises the steps:
At this, it should be noted that, if the last Balun obtaining does not still meet design requirement, adjust outlet difference angle, repeat above-mentioned steps, until obtain the Balun that meets design requirement
Visible, a kind of balanced-to-unblanced transformer of the present invention and optimization method thereof are by differing the delivery outlet of balanced-to-unblanced transformer to be adjusted into unsymmetric structure, make its outside cabling can be different, can by turn round or the mode such as mask placement device by the two-way output squeezing of balanced-to-unblanced transformer to compared with small size, between pin, can be applicable to placing other circuit, reach the object of optimizing device layout in chip, reducing device or the outer cabling of module and raising chip accuracy.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any those skilled in the art all can, under spirit of the present invention and category, modify and change above-described embodiment.Therefore, the scope of the present invention, should be as listed in claims.
Claims (6)
1. a balanced-to-unblanced transformer, in core Embedded, is characterized in that: the outlet of this balanced-to-unblanced transformer is unsymmetric structure.
2. balanced-to-unblanced transformer as claimed in claim 1, is characterized in that: it is positive and negative 15% that the design of the outlet difference angle of this balanced-to-unblanced transformer should meet inductance precision.
3. balanced-to-unblanced transformer as claimed in claim 2, is characterized in that: the outlet difference angle of this balanced-to-unblanced transformer is between 0～180 degree.
4. balanced-to-unblanced transformer as claimed in claim 2, is characterized in that: the outlet difference angle of this balanced-to-unblanced transformer is 90 degree.
5. an optimization method for balanced-to-unblanced transformer, this balanced-to-unblanced transformer is in core Embedded, and the method comprises the steps:
Step 1, is designed to unsymmetric structure by the outlet of this balanced-to-unblanced transformer;
Step 2, for integrated inductor in chip, optimizes cabling; And
Step 3, carries out Electromagnetic Simulation to this balanced-to-unblanced transformer, extracts parasitic parameter; And
Step 4, carries out software emulation according to the parasitic parameter obtaining by this balanced-to-unblanced transformer substitution software, verifies and confirms whether designed balanced-to-unblanced transformer meets design requirement, and obtains required balance-imbalance converter.
6. the optimization method of balanced-to-unblanced transformer as claimed in claim 5, it is characterized in that: if the balanced-to-unblanced transformer that this step 4 obtains does not meet design requirement, adjust the outlet difference angle of this balanced-to-unblanced transformer, and repeat this step 1 to this step 4, until the balanced-to-unblanced transformer that this step 4 obtains meets design requirement.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210254316.4A CN103579730A (en) | 2012-07-20 | 2012-07-20 | Balun and optimizing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210254316.4A CN103579730A (en) | 2012-07-20 | 2012-07-20 | Balun and optimizing method thereof |
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| CN103579730A true CN103579730A (en) | 2014-02-12 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06283912A (en) * | 1993-03-30 | 1994-10-07 | Shimada Phys & Chem Ind Co Ltd | Waveguide/microstrip line converter |
| CN1204130A (en) * | 1997-06-17 | 1999-01-06 | Tdk株式会社 | Iron-core material iron-core and transformer for balancing-non-balancing transformer |
| JP2007165944A (en) * | 2005-12-09 | 2007-06-28 | Yazaki Corp | Evaluation board for balanced connector |
| CN102543943A (en) * | 2010-12-09 | 2012-07-04 | 台湾积体电路制造股份有限公司 | Transformer with bypass capacitor and manufacturing method thereof |
-
2012
- 2012-07-20 CN CN201210254316.4A patent/CN103579730A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06283912A (en) * | 1993-03-30 | 1994-10-07 | Shimada Phys & Chem Ind Co Ltd | Waveguide/microstrip line converter |
| CN1204130A (en) * | 1997-06-17 | 1999-01-06 | Tdk株式会社 | Iron-core material iron-core and transformer for balancing-non-balancing transformer |
| JP2007165944A (en) * | 2005-12-09 | 2007-06-28 | Yazaki Corp | Evaluation board for balanced connector |
| CN102543943A (en) * | 2010-12-09 | 2012-07-04 | 台湾积体电路制造股份有限公司 | Transformer with bypass capacitor and manufacturing method thereof |
Non-Patent Citations (2)
| Title |
|---|
| 宋蓓: "单片集成螺旋变压器及巴伦的设计与优化", 《中国优秀硕士学位论文全文数据库 工程科技辑》, no. 4, 15 April 2007 (2007-04-15), pages 042 - 74 * |
| 王腾星: "片上集成螺旋变压器和巴伦的优化设计", 《硕士学位论文》, 21 April 2012 (2012-04-21) * |
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Application publication date: 20140212 |