CN103578958A - Semiconductor grid structure and forming method thereof - Google Patents

Semiconductor grid structure and forming method thereof Download PDF

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Publication number
CN103578958A
CN103578958A CN201310553722.5A CN201310553722A CN103578958A CN 103578958 A CN103578958 A CN 103578958A CN 201310553722 A CN201310553722 A CN 201310553722A CN 103578958 A CN103578958 A CN 103578958A
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layer
gesn
semiconductor gate
gesns
gate structure
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赵梅
刘磊
王敬
梁仁荣
许军
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Tsinghua University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention provides a semiconductor grid structure and a forming method thereof. The method comprises the following steps that a Ge layer is provided to serve as a surface substrate; a Sn layer is formed on the Ge layer, and an interface between the Ge layer and the Sn layer is a GeSn layer; the Sn layer is removed to expose the GeSn layer; sulfidizing is carried out on the GeSn layer to form a GeSnSx passivation layer; a grid stacking structure is formed on the GeSnSx passivation layer. According to the semiconductor grid structure and the forming method, electrical properties of the Ge-based grid stacking structure can be improved, for example, the interface trap density and grid leakage current density are low, and the semiconductor grid structure has the advantages of being easy and convenient to use and low in cost.

Description

Semiconductor gate structure and forming method thereof
Technical field
The present invention relates to field of semiconductor manufacture, be specifically related to a kind of semiconductor gate structure and forming method thereof.
Background technology
Semiconductor Ge has higher electronics and hole mobility, is expected to realize under very small dimensions the transistor that performance is higher, and this makes it be considered the channel material of advanced device and receives a large amount of concerns.But, when Ge is applied in metal-oxide semiconductor fieldeffect transistor (MOSFET), must face the selection problem of gate-dielectric.The oxide of Ge has thermal instability, and water-soluble, and electric property is poor, and desirable Si/SiO in traditional Si base device 2interfacial characteristics is different.Thereby should adopt high-k dielectric to overcome this difficulty for Ge base MOSFET device, and realize the attenuate of equivalent oxide thickness simultaneously.
Yet by high-k dielectric Direct precipitation behind the Ge surface of cleaning with rare HF, conventionally show higher interface charge trap density and very poor leak current characteristic, this is mainly to be caused by interfacial characteristics poor between high-k dielectric and Ge, between Ge and high-k dielectric, sometimes also can interact interfacial characteristics is worsened more, so the interface passivation problem between high-k dielectric and Ge substrate is to realize the key of advanced Ge MOS device always.
People have proposed a lot of methods and have solved this problem, for example, between Ge and high-k dielectric, increase GeO 2, GeO xn y, the boundary layer such as AlN with realize Ge surface passivation and with the isolation of high-k dielectric, but in these methods or the improvement of its interface charge trap density and leak current characteristic still not ideal enough, or often its interfacial layer thickness is larger while realizing interface passivation effect, and dielectric constant is generally not high, thereby affected reducing of equivalent oxide thickness, be not suitable for the device application under very small dimensions.
Summary of the invention
The present invention one of is intended to solve the problems of the technologies described above at least to a certain extent or a kind of useful choice of technology is at least provided.
For this reason, one object of the present invention is to propose a kind of GeSnS of having xpassivation layer, the semiconductor gate Structure formation method that electrical properties is good.
Another object of the present invention is to propose a kind of GeSnS of having xpassivation layer, the semiconductor gate structure that electrical properties is good.
Semiconductor gate Structure formation method according to the embodiment of the present invention, comprises the following steps: provide and take Ge layer as surperficial substrate; On described Ge layer, form Sn layer, wherein, the interface between described Ge layer and described Sn layer is GeSn layer; Remove described Sn layer to expose described GeSn layer; Described GeSn layer is carried out to vulcanizing treatment to form GeSnS xpassivation layer; And at described GeSnS xon passivation layer, form grid stacked structure.
According to the semiconductor gate Structure formation method of the embodiment of the present invention, can improve the electric property of grid stacked structure on Ge base, for example low interface trap density and extremely low grid leakage current density, have advantages of simple and easy to do, cost is low.
In addition, according to the semiconductor gate Structure formation method of the embodiment of the present invention, can also there is following additional technical feature:
In one embodiment of the invention, before removing described Sn layer, further comprise: by annealing in process, strengthen described GeSn layer.
In one embodiment of the invention, described vulcanizing treatment is: annealing sulfuration in sulphur steam, so that described GeSn layer segment or all become GeSnS xpassivation layer.
In one embodiment of the invention, the temperature of described annealing sulfuration is 100-400 ℃.
In one embodiment of the invention, described vulcanizing treatment is: be immersed in and in the solution that contains sulphion, carry out wet-chemical sulfuration, so that described GeSn layer segment or all become GeSnS xpassivation layer.
In one embodiment of the invention, described in, contain one or more the combination including in the solution of sulphion in ammonium sulfide, hydrogen sulfide, vulcanized sodium.
In one embodiment of the invention, utilize and GeSn and Sn to be had to high corrosion select the solution of ratio to clean to remove described Sn layer to expose described GeSn layer.
The thickness of the described GeSn layer remaining after described cleaning in one embodiment of the invention, is 0.5-40nm.
In one embodiment of the invention, the described Ge of take layer comprises as surperficial substrate: the substrate that pure Ge substrate or top layer are Ge film.
Semiconductor gate structure according to the embodiment of the present invention, can comprise: take Ge layer as surperficial substrate; Be positioned at the GeSn layer on described Ge layer; Be positioned at the GeSnS on described GeSn layer xpassivation layer; And be positioned at described GeSnS xgrid stacked structure on passivation layer.
According to the semiconductor gate structure of the embodiment of the present invention, can improve the electric property of grid stacked structure on Ge base, for example low interface trap density and extremely low grid leakage current density, have advantages of simple in structure, cost is low.
In addition, according to the semiconductor gate structure of the embodiment of the present invention, can also there is following additional technical feature:
In one embodiment of the invention, described GeSn layer is first on described Ge layer, to form Sn layer, then the interface self-assembling formation between described Ge layer and described Sn layer or strengthened and obtained by annealing in process.
In one embodiment of the invention, described GeSnS xpassivation layer is that the sulfuration of partly or entirely annealing in sulphur steam of described GeSn layer obtains.
In one embodiment of the invention, the temperature of described annealing sulfuration is 100-400 ℃.
In one embodiment of the invention, described GeSnS xpassivation layer is that being partly or entirely immersed in of described GeSn layer carried out wet-chemical sulfuration and obtained in the solution that contains sulphion.
In one embodiment of the invention, described in, contain one or more the combination including in the solution of sulphion in ammonium sulfide, hydrogen sulfide, vulcanized sodium.
In one embodiment of the invention, the thickness of described GeSn layer is 0.5-40nm.
In one embodiment of the invention, the described Ge of take layer comprises as surperficial substrate: the substrate that pure Ge substrate or top layer are Ge film.
Additional aspect of the present invention and advantage in the following description part provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Accompanying drawing explanation
Above-mentioned and/or additional aspect of the present invention and advantage accompanying drawing below combination obviously and is easily understood becoming the description of embodiment, wherein:
Fig. 1 is the flow chart of the semiconductor gate Structure formation method of the embodiment of the present invention;
Fig. 2 is the structural representation of the semiconductor gate structure of the embodiment of the present invention;
Fig. 3 is Ge/GeSnS x/ HfO 2the Cg-Vg curve of the mos capacitance of/Al structure; With
Fig. 4 is Ge/GeSnS x/ HfO 2the Jg-Vg characteristic curve of the MOS structure of/Al structure.
Embodiment
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has the element of identical or similar functions from start to finish.Below by the embodiment being described with reference to the drawings, be exemplary, be intended to for explaining the present invention, and can not be interpreted as limitation of the present invention.
In the present invention, unless otherwise clearly defined and limited, First Characteristic Second Characteristic it " on " or D score can comprise that the first and second features directly contact, also can comprise that the first and second features are not directly contacts but contact by the other feature between them.And, First Characteristic Second Characteristic " on ", " top " and " above " comprise First Characteristic directly over Second Characteristic and oblique upper, or only represent that First Characteristic level height is higher than Second Characteristic.First Characteristic Second Characteristic " under ", " below " and " below " comprise First Characteristic under Second Characteristic and tiltedly, or only represent that First Characteristic level height is less than Second Characteristic.
As shown in Figure 1, the semiconductor gate Structure formation method according to the embodiment of the present invention, comprises the steps:
S1. provide and take Ge layer as surperficial substrate.
Particularly, what provide take Ge layer as surperficial substrate can be the substrate that pure Ge substrate or top layer are Ge film, for example, on Si matrix, have the substrate on Ge film top layer.
S2. on Ge layer, form Sn layer, wherein, the interface between Ge layer and Sn layer is GeSn layer.
Conventionally can adopt the techniques such as magnetron sputtering, electron beam evaporation on Ge layer, to form Sn layer.In these techniques, underlayer temperature can be controlled between room temperature to 200 ℃.In technical process, due to the diffusion of atom between bi-material interface, at Ge/Sn interface self-assembling formation GeSn layer.In a preferred embodiment of the invention, can also strengthen this GeSn layer by annealing in process.The temperature range of annealing is 50-200 ℃, and temperature is higher, and the GeSn layer forming is thicker.
The GeSn layer diffuseing to form is a kind of solid solution, has the crystal structure identical with Ge, and has fine characteristic of semiconductor, as GeSn has the hole mobility higher than Ge.Therefore, Ge surface forms GeSn layer and conventionally can not worsen the performance of Ge device.
S3. remove Sn layer to expose GeSn layer.
Particularly, utilize and GeSn and Sn to be had to high corrosion select the solution of ratio to clean to remove Sn layer to expose GeSn layer.Common cleaning solution comprises watery hydrochloric acid, dilute sulfuric acid, ammoniacal liquor or sodium hydroxide solution.The thickness of the GeSn layer remaining after cleaning is 0.5-40nm, and preferably, GeSn layer thickness is 0.5-10nm.
S4. GeSn layer is carried out to vulcanizing treatment to form GeSnS xpassivation layer.
Particularly, vulcanizing treatment can be annealing sulfuration in sulphur steam, so that GeSn layer segment or all become GeSnS xpassivation layer.Because GeSn layer has good characteristic of semiconductor, even if at Ge layer and GeSnS xbetween passivation layer, have unvulcanized GeSn layer, conventionally not only can not worsen the performance of Ge device, also may improve device performance.
Particularly, the temperature of annealing sulfuration is 100-400 ℃, and optimization temperature range is 200-300 ℃.
Vulcanizing treatment can also be carried out wet-chemical sulfuration for being immersed in the solution that contains sulphion, so that GeSn layer becomes GeSnS xpassivation layer.In the solution that contains sulphion, can be one or more the aqueous solution of combination in ammonium sulfide, hydrogen sulfide, vulcanized sodium.For example, can choose the ammonium sulfide solution of 0.1-20wt.%, reaction temperature can be chosen 20-80 ℃.
S5. at GeSnS xon passivation layer, form grid stacked structure.
Particularly, form gate electrode layer after dielectric layer can first be formed, to form grid stacked structure.In one embodiment of the invention, dielectric layer is high k material HfO 2, Al 2o 3or ZrO 2, gate electrode layer is TiN or TaN.It should be noted that, except above for example, the selection of the material of dielectric layer and gate electrode layer with mate and can arrange in pairs or groups flexibly other according to actual conditions, this belongs to the scope of general knowledge as well known to those skilled in the art.
According to the semiconductor gate Structure formation method of the embodiment of the present invention, sputtering for Sn metal level on Ge surface first, then with wet processings such as watery hydrochloric acid, remove upper strata Sn layer and obtain GeSn layer, this ultra-thin GeSn layer partly or entirely changes GeSnS into by vulcanizing treatment xpassivation layer, thus the electric property of grid stacked structure on Ge base improved, for example low interface trap density and extremely low grid leakage current density, this method also has advantages of simple and easy to do.
As shown in Figure 2, the semiconductor gate structure according to the embodiment of the present invention, comprising: take Ge layer 100 as surperficial substrate; Be positioned at the GeSn layer 200 on Ge layer 100; Be positioned at the GeSnS on GeSn layer 200 x passivation layer 300; And be positioned at GeSnS xgrid stacked structure 400(on passivation layer 300 comprises gate medium 410 and gate electrode 420).
Wherein, the Ge layer 100 of take comprises as surperficial substrate: the substrate that pure Ge substrate or top layer are Ge film, for example, have the substrate on Ge film top layer on Si matrix.
Wherein, GeSn layer 200 can be by form Sn layer (this Sn layer is finally sacrificed, therefore do not draw in Fig. 2) on Ge layer 100, then the interface self-assembling formation between Ge layer 100 and Sn layer or strengthened and obtained by annealing in process.The temperature range of annealing can be 50-200 ℃, and temperature is higher, and the GeSn layer 200 forming is thicker.Because the GeSn layer diffuseing to form is a kind of solid solution, there is the crystal structure identical with Ge and there is fine characteristic of semiconductor (as GeSn has the hole mobility higher than Ge), so the GeSn layer that Ge surface forms not only can not worsen the performance of Ge device conventionally, also may improve device performance.
Wherein, GeSnS xpassivation layer 300 is that the surface part sulfuration of GeSn layer 200 obtains.
In one embodiment of the invention, this GeSnS xpassivation layer 300 can be the surface part of GeSn layer 200 in sulphur steam, anneal sulfuration obtain.For example, in temperature is the sulphur steam of 100-500 ℃, anneal, optimization temperature range is 200-400 ℃.
In one embodiment of the invention, this GeSnS xpassivation layer 300 can be also that the surface part of GeSn layer 200 is immersed in and in the solution that contains sulphion, carries out wet-chemical sulfuration and obtain.In the solution that contains sulphion, can be one or more the aqueous solution of combination in ammonium sulfide, hydrogen sulfide, vulcanized sodium.For example, can choose the ammonium sulfide solution of 0.1-20wt.%, reaction temperature can be chosen 20-80 ℃.
It should be noted that, with GeSnS xthe top section of the GeSn layer 200 that passivation layer 300 contacts can be to utilize GeSn and Sn to be had to high corrosion to select the solution (for example watery hydrochloric acid, dilute sulfuric acid, ammoniacal liquor or sodium hydroxide solution etc.) of ratio to clean after removing the Sn layer on GeSn layer 200 to come out.Alternatively, the thickness of the GeSn layer 200 remaining after cleaning is 0.5-40nm, and in the semiconductor gate structure finally obtaining, the thickness of GeSn layer 200 is 0.5-40nm.
Wherein, grid stacked structure 400 generally includes dielectric layer 410 and gate electrode layer 420.In one embodiment of the invention, dielectric layer can be high k material HfO 2, Al 2o 3or ZrO 2, gate electrode layer can be TiN or TaN.It should be noted that, except above giving an example, the material of dielectric layer and gate electrode layer can be selected flexibly and mate according to actual conditions, and this belongs to the scope of general knowledge as well known to those skilled in the art.
Semiconductor gate structure according to the embodiment of the present invention, has GeSnS xpassivation layer, simultaneously at Ge and GeSnS xbetween be also formed with high performance GeSn semiconductor layer, GeSn and GeSnS xthe thickness of layer is controlled, thereby improves the electric property of grid stacked structure on Ge base, for example low interface trap density and extremely low grid leakage current density, and the semiconductor gate structure of this embodiment also has simple in structure, lower-cost advantage.
For making those skilled in the art understand better the present invention, it is as follows that inventor sets forth a specific embodiment in conjunction with Fig. 3-Fig. 4: in the following embodiments, and by introducing ultra-thin GeSnS xlayer comes the interface between passivation high-k dielectric and Ge substrate.Sputtering for Sn on Ge substrate, then removes top Sn layer with rare HCl, then GeSn layer is vulcanized, and obtains GeSnS xlayer.This technology can obtain the ultra-thin GeSnS of one deck xlayer, thick about 1nm.Found that, with the Ge/HfO without this passivation layer 2mos capacitance device is compared, and introduces GeSnS xthe mos gate stacked structure of layer has better electric property.Measurement result shows, Ge/GeSnS x/ HfO 2the equivalent oxide thickness of mos capacitance (EOT) and interface state density (D it) be respectively 2.4nm and 5.3 * 10 11cm -2eV -1.Particularly:
First, the substrate providing is the N-shaped Ge wafer of mixing (100) face of Sb, and resistivity is 0.09 Ω cm.With after rare HF (1:50) and deionized water circulation flushing Ge substrate, Sn magnetron sputtering, on Ge substrate, is then immersed wafer in rare HCl (10%) 3 minutes, remove top Sn layer, on Ge surface, leave the ultra-thin GeSn layer of one deck.This layer of ultra-thin GeSn layer can change into GeSnS to realize surperficial vulcanizing treatment wafer to be immersed in to concentration again and to be in 20% ammonium sulfide solution 30 minutes xlayer.Subsequently, with four pairs of (ethyl-methyl ammonia) hafniums (TEMAH) and water, as presoma, by ALD, deposit the HfO that 5.5nm is thick 2layer.Finally, steam gate electrode Al and graphically obtain mos capacitance.The characterization method of this mos capacitance is mainly comprised to capacitance-voltage (Cg-Vg) characteristic curve and leakage current density-voltage (Jg-Vg) characteristic curve of measuring this mos capacitance with Agilent B1500A semiconductor device analyzer, analyze its electrology characteristic.
Fig. 3 is Ge/GeSnS x/ HfO 2the Cg-Vg curve of/Al mos capacitance.To Ge/GeSnS x/ HfO 2/ Al electric capacity sample, Cg-Vg curve occurs in reversal zone with the sharp-pointed abrupt slope of few warpage, shows that interface state density is lower.Hence one can see that, the GeSnS introducing in high-k dielectric structure on Ge substrate xlayer can play good passivation effect.Through conductance measurement and analysis, Ge/GeSnS x/ HfO 2the interface state density of/Al electric capacity sample is about 5.3 * 10 11cm -2eV -1.
Fig. 4 is Ge/GeSnS x/ HfO 2the Jg-Vg characteristic curve of/Al MOS structure.Ge/GeSnS x/ HfO 2the leakage current density of/Al sample in-1～1V voltage range all lower than 2.2 * 10 -7a/cm 2.Generally speaking, the present invention is by introducing the ultra-thin GeSnS of one deck xlayer, carries out electricity passivation to interface between high-k dielectric and Ge substrate.GeSnS wherein xpreparation method as follows: on Ge substrate, sputtering for Sn layer obtains GeSn layer, with watery hydrochloric acid, removes Sn layer, and GeSn layer generates GeSnS through vulcanizing treatment xlayer.This compares with the high k material of Direct precipitation on Ge substrate, Ge/GeSnS x/ HfO 2the D of/Al mos capacitance itreduce with leakage current density, be respectively 5.3 * 10 11eV -1cm -2with 2.2 * 10 -7a/cm 2hence one can see that, the GeSnS introducing in high-k dielectric structure on Ge substrate xlayer can play good passivation effect.
In flow chart or any process of otherwise describing at this or method describe and can be understood to, represent to comprise that one or more is for realizing module, fragment or the part of code of executable instruction of the step of specific logical function or process, and the scope of the preferred embodiment of the present invention comprises other realization, wherein can be not according to order shown or that discuss, comprise according to related function by the mode of basic while or by contrary order, carry out function, this should be understood by embodiments of the invention person of ordinary skill in the field.
In the description of this specification, the description of reference term " embodiment ", " some embodiment ", " example ", " concrete example " or " some examples " etc. means to be contained at least one embodiment of the present invention or example in conjunction with specific features, structure, material or the feature of this embodiment or example description.In this manual, the schematic statement of above-mentioned term is not necessarily referred to identical embodiment or example.And the specific features of description, structure, material or feature can be with suitable mode combinations in any one or more embodiment or example.
Although illustrated and described embodiments of the invention above, be understandable that, above-described embodiment is exemplary, can not be interpreted as limitation of the present invention, those of ordinary skill in the art can change above-described embodiment within the scope of the invention in the situation that not departing from principle of the present invention and aim, modification, replacement and modification.

Claims (17)

1. a semiconductor gate Structure formation method, is characterized in that, comprises the following steps:
Provide and take Ge layer as surperficial substrate;
On described Ge layer, form Sn layer, wherein, the interface between described Ge layer and described Sn layer is GeSn layer;
Remove described Sn layer to expose described GeSn layer;
Described GeSn layer is carried out to vulcanizing treatment to form GeSnS xpassivation layer; And
At described GeSnS xon passivation layer, form grid stacked structure.
2. semiconductor gate Structure formation method as claimed in claim 1, is characterized in that, further comprises: by annealing in process, strengthened described GeSn layer before removing described Sn layer.
3. the semiconductor gate Structure formation method as described in claim 1 and 2, is characterized in that, described vulcanizing treatment is: annealing sulfuration in sulphur steam, so that described GeSn layer segment or all become GeSnS xpassivation layer.
4. semiconductor gate Structure formation method as claimed in claim 3, is characterized in that, the temperature of described annealing sulfuration is 100-400 ℃.
5. the semiconductor gate Structure formation method as described in claim 1 and 2, is characterized in that, described vulcanizing treatment is: be immersed in and in the solution that contains sulphion, carry out wet-chemical sulfuration, so that described GeSn layer segment or all become GeSnS xpassivation layer.
6. semiconductor gate Structure formation method as claimed in claim 5, is characterized in that, described in contain sulphion solution in include one or more the combination in ammonium sulfide, hydrogen sulfide, vulcanized sodium.
7. semiconductor gate Structure formation method as claimed in claim 1, is characterized in that, utilizes GeSn and Sn to be had to high corrosion to select the solution of ratio to clean to remove described Sn layer to expose described GeSn layer.
8. semiconductor gate Structure formation method as claimed in claim 7, is characterized in that, the thickness of the described GeSn layer remaining after described cleaning is 0.5-40nm.
9. semiconductor gate Structure formation method as claimed in claim 1, is characterized in that, the described Ge of take layer comprises as surperficial substrate: the substrate that pure Ge substrate or top layer are Ge film.
10. a semiconductor gate structure, is characterized in that, comprising:
Take Ge layer as surperficial substrate;
Be positioned at the GeSn layer on described Ge layer;
Be positioned at the GeSnS on described GeSn layer xpassivation layer; And
Be positioned at described GeSnS xgrid stacked structure on passivation layer.
11. semiconductor gate structures as claimed in claim 10, is characterized in that, described GeSn layer is first on described Ge layer, to form Sn layer, then the interface self-assembling formation between described Ge layer and described Sn layer or strengthened and obtained by annealing in process.
12. semiconductor gate structures as described in claim 10 or 11, is characterized in that described GeSnS xpassivation layer is that the sulfuration of partly or entirely annealing in sulphur steam of described GeSn layer obtains.
13. semiconductor gate structures as claimed in claim 12, is characterized in that, the temperature of described annealing sulfuration is 100-400 ℃.
14. semiconductor gate structures as described in claim 10 or 11, is characterized in that described GeSnS xpassivation layer is that being partly or entirely immersed in of described GeSn layer carried out wet-chemical sulfuration and obtained in the solution that contains sulphion.
15. semiconductor gate structures as claimed in claim 14, is characterized in that, described in contain sulphion solution in include one or more the combination in ammonium sulfide, hydrogen sulfide, vulcanized sodium.
16. semiconductor gate structures as claimed in claim 10, is characterized in that, the thickness of described GeSn layer is 0.5-40nm.
17. semiconductor gate structures as claimed in claim 10, is characterized in that, the described Ge of take layer comprises as surperficial substrate: the substrate that pure Ge substrate or top layer are Ge film.
CN201310553722.5A 2013-11-08 2013-11-08 Semiconductor grid structure and forming method thereof Pending CN103578958A (en)

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Publication number Priority date Publication date Assignee Title
CN103811304A (en) * 2014-02-25 2014-05-21 清华大学 GeSn layer and forming method thereof

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