CN103577742A - Circuit and electronic label of AES (Advanced Encryption Standard) algorithm resistant to differential power analysis - Google Patents
Circuit and electronic label of AES (Advanced Encryption Standard) algorithm resistant to differential power analysis Download PDFInfo
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- CN103577742A CN103577742A CN201310508053.XA CN201310508053A CN103577742A CN 103577742 A CN103577742 A CN 103577742A CN 201310508053 A CN201310508053 A CN 201310508053A CN 103577742 A CN103577742 A CN 103577742A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
Abstract
The invention belongs to the technical field of radio frequency identification, and particularly discloses a circuit and an electronic label of an AES (Advanced Encryption Standard) algorithm resistant to differential power analysis. The electronic label structurally comprises an analog front end, a demodulator circuit, a digital base band, a memory module and an AES safety module resistant to the differential power analysis, wherein the label downwards inherits the ISO8000-6C standard; in addition, a plurality of safety relevant instructions are added for the safety communication; aiming at the differential power analysis of the safety label, the masking circuit optimization is carried out on the AES algorithm module on a safety engine; the masking algorithm circuit XOR-processes the to-be-processed input by using one group or a plurality of groups of masking data; in the whole computation process, the input participates in the computation through the data subjected to the XOR-processing by the masking data, namely, the masked data rather than directly participate in the computation; in the system, the measures of random operation migration are applied to the label, so that the electronic label has higher safety when subjected to the contact-type power analysis.
Description
Technical field
The invention belongs to REID field, be specifically related to a kind of electronic tag and the design of a kind of AES security module, relate in particular to the design of a kind of electronic tag of resisting differential power consumption analysis and the AES security module of resisting differential power consumption analysis.
Background technology
Radio-frequency (RF) identification (RFID) is a kind of automatic identification technology that carries out noncontact duplex channel by electromagnetic wave, the ultimate system of radio-frequency (RF) identification comprises electronic tag (hereinafter to be referred as label) and read write line, is a kind of contactless automatic recognition system swift and convenient to operate.This system can be identified the target of a plurality of motions simultaneously, and can work in various complex environments, and its application can improve the automaticity that enterprise manufactures effectively.Electronic label technology is used for supply chain management at present, asset management, and the fields such as electronics license, and just towards more diversification, more wide application prospect, advancing.
The propelling of RFID technology makes people's life become convenient, but along with the development of rfid system in the application of the emerging fields such as anti-drug counterfeiting, health care, the privacy that RFID technology may cause and safety problem are subject to paying close attention to more and more widely.For example, there is not the problem of privacy in the medicine that posts electronic tag in logistics progress, but when patient has bought this medicine and carried, patient's the right of privacy is just likely invaded in unauthorized reading.In prior art, the existing solution for electronic security tag focus mostly on cryptographic algorithm, security protocol and with the combination of electronic labelling system, but a kind of attack for circuit itself is just becoming the significant threat of safety label: power consumption analysis.This attack utilizes contact type probe, and the power consumption curve while surveying also analyzing tags work, smells with this security information of visiting safety label inside, such as key, password etc.
Summary of the invention
The object of the present invention is to provide a kind of novel electronic tag and corresponding security module, strengthen power consumption analysis resistivity, thereby solve the security decline problem of one piece of safety electronic label when for power consumption analysis.
The object of the invention is to be achieved through the following technical solutions:
The invention provides the aes algorithm circuit of a kind of resisting differential power consumption analysis (DPA), its basic structure is replaced (Subbyte) module, row mixing (Mixcolumn) module, line translation (ShiftRow) module, cipher key spreading (KeyExpansion) module, interface (Interface) module, randomizer module (RNG), masking data memory module (MaskReg) and a plurality of data selector (MUX) by state machine (Control) module, word and is combined.
The method that usage data of the present invention is sheltered (MASK SCHEME) is sheltered aes algorithm, has played the effect that power consumption analysis is resisted.This masking algorithm circuit has been used one or more groups masking data (Mask) to carry out XOR with needing input to be processed (Data), in whole calculating process, input can not participated in computing directly, but by the data after masking data XOR, shelter rear data (Masked Data) and participate in calculating.
Input signal is connected with the first data selector (MUX) through interface module (Interface), after be connected to line translation module (ShiftRow), through the second data selector (MUX), be connected with word replacement module (Subbyte) again, export the 3rd data selector (MUX) to and be connected with row mixing (Mixcolumn) module, finally through the 4th data selector (MUX), be connected to another input of the first data selector (MUX) foremost; Randomizer (RNG) is connected to produce random masking data with masking data storer (MaskReg) module, and masking data is connected to line translation (ShiftRow) module and completes masked operation; Interface module (Interface) has been connected input, output services with state machine (Control) module, line translation module (ShiftRow), complete the connection of whole circuit.
In described module, the modules different from existing standard aes algorithm circuit theory are: (Subbyte) module and line translation (ShiftRow) module replaced in state machine (Control) module, word, and have increased random number generator (RNG) and the memory module (MaskReg) of generation masking data (Mask).
Described state machine (Control) module, control circuit is with regard to an enciphering/deciphering computation requirement of taking turns for DATA, take two inputs (respectively for Masked Data and Mask) successively to carry out twice independently AES enciphering/deciphering computation process, provide the signal of differentiation, and rely on this result of calculation of twice finally at output terminal, to restore needed encryption and decryption result, reach in whole process the object that algorithm circuit is not directly processed DATA.
(Subbyte) module replaced in described word, the expression formula of using following identical transformation to obtain:
Substitute core in script aes algorithm and get contrary part, in formula, M is masking data (Mask), and A gets ifft circuit to need input to be processed (DATA), and subscript-1 is for getting inverse operation, and subscript 2 is square operation.In addition,, if the signal providing according to state machine (Control) module, what decision circuitry was just being processed is Mask data, skips above-mentioned core and gets inverse operation, directly carries out AES linear transformation operation.If otherwise process be Masked Data normal process to reach, facilitate circuit in the object of output terminal reduction.
Described line translation (ShiftRow) module, the signal during the judgement Mask Data/Mask providing according to state machine (Control) module processes, chooses different inputs and operates.
Described random number generator (RNG) module and masking data memory module (MaskReg), calculating the front several clocks that start, work in coordination, and the random masking data (Mask) of enough figure places is stored in MaskReg.
The invention still further relates to the safety electronic label of a kind of resisting differential power consumption analysis (DPA), comprise modulation module (Mod), decoder module (Decode), check code module (CRC16), output control module (OCU), random number generation module (PRNG), back-end memory module, also comprise:
Security module (Crypto_Engine), possesses the characteristic of the anti-DPA of algorithm level, for data are carried out to enciphering/deciphering.
Control module (Control), for the input signal transmitting by other modules, state and the action of judgement label, and generate peripheral control signal;
Memory module (Interface & PROM), the content of storage comprises, the data of taking inventory key (Access_Password) that comprise that safety is recognized the needed key in aspect and ISO18000-6C defined;
Safety chip, in the time of need to using security engine (Crypto_Engine) to carry out encryption and decryption operation, chip is used clock randomization operation, by inner random number generation module (PRNG) at each rising edge clock, by certain probability, produce the clock delay signal for security engine, by clock of the operating delay of security engine, reach the object that upsets power consumption curve in sequential.
Advantage of the present invention comprises, electronic tag of the present invention is inherited the standard of ISO18000-6C downwards.The present invention meets the hardware requirement of one piece of safety label.In addition, in algorithm level, the present invention is directed to the operation of sheltering of aes algorithm module, making it have this masking algorithm circuit has used one or more groups masking data (Mask) to carry out XOR with needing input to be processed (Data), in whole calculating process, input can not participated in computing directly, but by the data after masking data XOR, shelter rear data (Masked Data) and participate in calculating, the security while greatly having strengthened in the face of differential power consumption analysis.On system-level, label has been taked to the measure of random operation skew.This measure makes time that the present invention upsets operation on passing through with when improving security, has reduced the average power consumption of label when security engine is worked.
Certainly, implement arbitrary product of the present invention and might not need to reach above-described all advantages simultaneously.
Accompanying drawing explanation
Fig. 1 is the aes algorithm structure of resisting differential power consumption analysis of the present invention.
Fig. 2 is the aes algorithm encryption and decryption flow process of resisting differential power consumption analysis of the present invention.
Fig. 3 is that the aes algorithm Subbyte core of resisting differential power consumption analysis of the present invention is got contrary part-structure.
Fig. 4 is the aes algorithm state machine sequential chart of resisting differential power consumption analysis of the present invention.
Fig. 5 is the structural representation of the electronic tag of resisting differential power consumption analysis of the present invention.
Obviously, above-mentioned accompanying drawing is only some embodiment of the application, for those of ordinary skills, is not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Embodiment
Accompanying drawing below in conjunction with in embodiment, is further described technical solution of the present invention, and obviously, described embodiment is only the application's part embodiment, rather than whole embodiment.Embodiment based in the application, those of ordinary skills are not making the every other embodiment obtaining under creative work prerequisite, all belong to the scope of the application's protection.
The specific embodiment of the present invention, will describe from sheltering two aspects such as structure, safety label structure of aes algorithm.
1, shelter the structure of aes algorithm:
Aes algorithm circuit provided by the invention, possesses enciphering/deciphering function, and has used the shared calculation process of enciphering/deciphering, as shown in Figure 2.In figure, each module all refers to the content of operation in aes algorithm requirement.ISR refers to line translation operation,
IMC refers to row married operation, and ISB refers to word replacement operation, and AEK refers to key add operation, and KE refers to cipher key spreading operation.
The present invention, on the basis of rudimentary algorithm function, has increased the characteristic of data masking.This masking algorithm circuit has been used one or more groups masking data (Mask) to carry out XOR with needing input to be processed (Data), in whole calculating process, input can not participated in computing directly, but by the data after masking data XOR, shelter rear data (Masked Data) and participate in calculating.For use being sheltered to the resulting result of rear data (Masked Data), reduce, AES circuit in the present invention has been used two inputs (respectively for Masked Data and Mask) successively to carry out twice independently AES enciphering/deciphering computation process, provide the signal of differentiation simultaneously, and rely on this result of calculation of twice finally at output terminal, to restore needed encryption and decryption result.In whole process, algorithm circuit is not directly processed DATA, has therefore strengthened the defensive ability/resistance ability of differential power consumption analysis.Make this algorithm have stronger resistance to differential power consumption analysis.
The circuit structure of this algorithm as shown in Figure 1.
This algorithm circuit is by following module composition:
(a) state machine module (Control): the input signal that this module is transmitted by external input signal and modules, state and the action of judgement AES, and generate peripheral control signal.State machine used in the present invention and the required data to be processed of corresponding each clock are as shown in Figure 4.
In figure, horizontal line below refers to the mark of state machine, and horizontal line top refers to the module in current time work.In figure, MC refers to row married operation, and SBOX refers to word replacement operation, and ADK refers to the key add operation in aes algorithm, and AFFINE represents the word replacement operation after identical replacement.KE represents cipher key spreading operation.In the design, use 128 bit wides, be divided into altogether 4 groups of 32 bit wides.After module, mark the group number that digital 1-4 representative is being processed when front module.
(b) word is replaced (Subbyte): this module is according to the requirement of algorithm standard rules, and every clock completes the word replacement operation of 8.Subbyte module described in this module, the expression formula of using following identical transformation to obtain
substitute core in script aes algorithm and get contrary part (in formula, M is masking data (Mask), and A gets ifft circuit to need input to be processed (DATA), and subscript-1 is for getting inverse operation, and subscript 2 is square operation).In addition,, if the signal providing according to Control module, what decision circuitry was just being processed is Mask data, skips above-mentioned core and gets inverse operation, directly carries out AES linear transformation operation.If otherwise process be Masked Data normal process to reach, facilitate circuit in the object of output terminal reduction.This module core is got contrary design partly as shown in Figure 3.
In figure, A refers to input data (DATA), and M refers to masking data (MASK), square, the calculating operation on the galois field described in multiplication and the equal corresponding A ES algorithm of addition.
(c) row mixing module (Mixcolumn): this module is according to the requirement of algorithm standard rules, and every clock completes the row married operation of 32.
(d) line translation module (ShiftRow): this module is according to the requirement of algorithm standard rules, and every clock completes the line translation operation of 32 is deposited every calculating intermediate quantity of taking turns simultaneously.
(e) cipher key expansion module (KeyExpansion): this module, according to the requirement of algorithm standard rules, when calculating beginning, is carried out round key extended operation to initial key.
(f) interface module (Interface): this module is controlled and resolved input/output signal.
(g) random number generation module (PRNG): this module produces random number.
(h) masking data memory module (MaskReg): this module has stored masking data (MASK).By random number generation module, be the source of masking data, the preparation of masking data need to complete before calculating starts.
2, the structure of label:
The electronic tag of anti-power consumption analysis provided by the invention, inherits the ordinary electronic tag feature of ISO18000-6C standard-required downwards.When this label safety chip need to be used security engine (Crypto_Engine) to carry out encryption and decryption operation, chip can be used clock randomization operation, by inner random number generation module (PRNG) at each rising edge clock, by certain probability, produce the clock delay signal for security engine, by clock of the operating delay of security engine, reach the object that upsets power consumption curve in sequential.
The structure of this label can be divided into AFE (analog front end), with digital baseband two parts.
The digital baseband structure of this label as shown in Figure 5.
Comprising following module:
(a) control module (Control): the input signal that this module is transmitted by other modules, state and the action of judgement label, and generate peripheral control signal.
(b) demodulation module (Demod): this module is by counting to carry out digital demodulation to the rising edge of input PIE signal.
(c) decoder module (Decode): this module is decoded to the complete signal of demodulation.
(d) check code module (CRC16): needed CRC16 cyclic check code when this module generation signal returns.
(e) modulation module (Mod): this module is modulated label return signal.
(f) output control module (OCU): this module is controlled output signal.
(g) random number generation module (PRNG): this module produces random number, by this module, produces a clock delay signal by certain probability, and the operation of whole security engine is postponed.
(h) the cryptographic algorithm module of anti-power consumption analysis (AES & AES_CTRL): the enciphering/deciphering of these resume module data.In this example, use aes algorithm, applicability just of the present invention considers it can is also other masking algorithm.If this module receives from outside clock delay signal, by clock of the operating delay of whole security engine.
(i) back-end memory module: all necessary datas of this module stores standard C 1G2 electronic tag.(as EPC code, TID code and PC etc.) this module adopts EEPROM or ROM to generate more.Except the data of basic I SO 18000-6C agreement regulation storage;
Also storing and the safety certification/relevant key of communicating by letter simultaneously.
(j) RF front-end module: coordinate with control module, complete radio frequency reception and analog demodulator.
Be noted that each embodiment in this instructions all adopts the mode of going forward one by one to describe, each embodiment stresses is the difference with other embodiment, between each embodiment identical similar part mutually referring to.
Above a kind of method that can be exchanged into safety label provided by the present invention is described in detail, applied specific case herein principle of the present invention and embodiment are set forth, the explanation of above embodiment is just for helping to understand method of the present invention and core concept thereof; , for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as the restriction to the application meanwhile.
Claims (10)
1. an aes algorithm circuit for resisting differential power consumption analysis, is characterized in that: its basic structure is replaced (Subbyte) module, row mixing (Mixcolumn) module, line translation (ShiftRow) module, cipher key spreading (KeyExpansion) module, interface (Interface) module, randomizer module (RNG), masking data memory module (MaskReg) and a plurality of data selector (MUX) by state machine (Control) module, word and combined;
The connected mode of its circuit: input signal is connected with the first data selector (MUX) through interface module (Interface), after be connected to line translation module (ShiftRow), through the second data selector (MUX), be connected with word replacement module (Subbyte) again, export the 3rd data selector (MUX) to and be connected with row mixing (Mixcolumn) module, finally through the 4th MUX, be connected to another input of the first data selector (MUX) foremost; Randomizer (RNG) is connected to produce random masking data with masking data storer (MaskReg) module, and masking data is connected to line translation (ShiftRow) module and completes masked operation; Interface module (Interface) be connected with state machine (Control) module, line translation module (ShiftRow) input, output services.
2. the aes algorithm circuit of resisting differential power consumption analysis according to claim 1, it is characterized in that: this algorithm circuit is used one or more groups masking data (Mask) to carry out XOR with needing input to be processed (Data), in whole calculating process, computing is not participated in input directly, but by the data after masking data XOR, shelter rear data (Masked Data) and participate in calculating.
3. the aes algorithm circuit of resisting differential power consumption analysis according to claim 1, it is characterized in that: described state machine (Control) module, control circuit is with regard to an enciphering/deciphering computation requirement of taking turns for DATA, take respectively for Masked Data and two inputs of Mask, successively carry out twice independently AES enciphering/deciphering computation process, provide the signal of differentiation, and rely on this result of calculation of twice finally at output terminal, to restore needed encryption and decryption result.
4. the aes algorithm circuit of resisting differential power consumption analysis according to claim 1, is characterized in that: (Subbyte) module, the expression formula of using following identical transformation to obtain replaced in described word
substitute core in script aes algorithm and get contrary part, wherein M is masking data (Mask), and A gets ifft circuit to need input to be processed (DATA), and subscript-1 is for getting inverse operation, and subscript 2 is square operation; In addition, if the signal providing according to state machine (Control) module, that decision circuitry is just being processed is Mask, skips above-mentioned core and gets inverse operation, directly carries out AES linear transformation operation; Otherwise normal process, reaches fan-out factor according to the object of reduction with this.
5. the aes algorithm circuit of resisting differential power consumption analysis according to claim 1, it is characterized in that: described line translation (ShiftRow) module, signal during the judgement Mask Data/Mask providing according to state machine (Control) module processes, chooses different inputs and operates.
6. the aes algorithm circuit of resisting differential power consumption analysis according to claim 1, it is characterized in that: described random number generator (RNG) and masking data memory module (MaskReg), calculating the front several clocks that start, cooperatively interact, the random masking data (Mask) of enough figure places is stored in masking data memory module (MaskReg).
7. the electronic tag of a resisting differential power consumption analysis, comprise security module (Crypto_Engine), control module (Control), RF front-end module, modulation module (Mod), decoder module (Decode), check code module (CRC16), output control module (OCU), random number generation module (PRNG), back-end memory module, it is characterized in that, also comprise:
Demodulation module (Demod), be connected with RF front-end module, data after analog demodulator are carried out to asynchronous digital demodulation, security module (AES & AES_CTRL), modulation module (Mod), control module (Control), decoder module (Decode), check code module (CRC16), output control module (OCU) is all connected to data path BUS with random number generation module (PRNG) and completes interconnection, data path BUS is also connected to the memory module (Interface & PROM) of rear end simultaneously, complete the connection of whole circuit,
Safety chip, in the time of need to using security engine (Crypto_Engine) to carry out encryption and decryption operation, safety chip is used clock randomization operation, by inner random number generation module (PRNG) at each rising edge clock, by certain probability, produce the clock delay signal for security engine, by clock of the operating delay of security engine, reach the object that upsets power consumption curve in sequential.
8. the electronic tag of resisting differential power consumption analysis according to claim 7, is characterized in that: described security module (Crypto_Engine), possesses the characteristic of the anti-DPA of algorithm level, for data are carried out to enciphering/deciphering.
9. the electronic tag of resisting differential power consumption analysis according to claim 7, is characterized in that: described control module (Control), for the input signal transmitting by other modules, judges state and the action of label, and generate peripheral control signal.
10. the electronic tag of resisting differential power consumption analysis according to claim 7, it is characterized in that: the content of described memory module (Interface & PROM) storage comprises, the needed key of safety authentication protocol and ISO18000-6C defined comprise the necessary data of taking inventory key (Access_Password).
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| CN105894079A (en) * | 2016-04-22 | 2016-08-24 | 上海东软载波微电子有限公司 | Clock scrambling circuit |
| CN106228224A (en) * | 2016-07-11 | 2016-12-14 | 天津中兴智联科技有限公司 | A kind of electronic tag of compatible multi-protocols |
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Application publication date: 20140212 |