CN103986571A - Intelligent card multinucleated processor system and defense difference power consumption analysis method thereof - Google Patents
Intelligent card multinucleated processor system and defense difference power consumption analysis method thereof Download PDFInfo
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Abstract
The invention brings forward an intelligent card multinucleated processor system and a defense difference power consumption analysis method thereof. The system employs multinucleated microprocessors for processing parallel encryption and decryption algorithms and data, each microprocessor works under the condition of completely mutually asynchronous clock signals, the work power consumption of each microprocessor is mutually interference power consumption, during processing of other non-encryption-and-decryption algorithm tasks, the multinucleated processors can also be simultaneously switched on for operation, i.e., the same performance or even performance better than that of a single-nucleus intelligent card can be realized by use of smaller power consumption, and the effect for defending against difference power consumption analysis attacks can be achieved.
Description
Technical field
The present invention relates to semiconductor and computer technology, relate in particular to a kind of method of smart card multi-core processor system and defence differential power consumption analysis thereof.
Background technology
Along with the development of very lagre scale integrated circuit (VLSIC) and computer technology, information security is from traditional politics, economy, and the field such as military is generalized in daily life.Because information security technology is guaranteed the safety preservation of information and transmits, therefore, high performance smart card is very universal in the world, as identity card, and bank card, Mobile phone card etc.
Modern electronic equipment is made up of integrated circuit, and information security technology also depends on corresponding integrated circuit (as crypto chip) as hardware carrier.Generally adopt at present security information by encrypting the strategy of carrying out cryptographic algorithm on device; reach the object of protection information safety; but; in execution cryptographic algorithm process, physical device always will leak the various information relevant to cryptographic system itself, such as running time, energy consumption, electromagnetic radiation etc.Assailant utilizes these marginal information attacks to encrypt device just can obtain key, and this process is called bypass attack (Side Channel Attack, SCA).Bypass attack method is divided into time series analysis, power consumption analysis and electromagnetic radiation and analyzes 3 classes.In bypass information, because the testability of power consumption is the strongest, the simplest, the also the most applicable analysis of power consumption curve of the instrument of testing power consumption, power consumption analysis attack is applied at most in actual attack.Power consumption analysis attack has simple power consumption analysis (Simple Power Analysis, SPA) to attack, and differential power consumption analysis (Differential Power Analysis, DPA) is attacked.In many power consumption analysis lie attack options, Differential power attack analysis technology is proved to be full blast and is the one the most easily realizing, due to its easy operating and very effective, the safety of crypto module is formed to significant threat.The main path of opposing Differential power attack analysis is broadly divided into two classes: be 1. the fluctuation that as far as possible reduces power consumption curve, reduce the information content in power consumption curve, adopt the method that reduces signal to noise ratio to reach the object of defending Differential power attack analysis; 2. be the correlation that as far as possible upsets power consumption curve and data, we have two kinds of modes to realize the correlation that upsets power consumption curve and data, the first is that we increase extra data in the time carrying out enciphering and deciphering algorithm, power consumption curve and data dependence are destroyed, and the second is to adopt to increase random noise and redundancy power consumption.These two kinds of fail safes that approach can improve crypto chip, make assailant be difficult to carry out Differential power attack analysis or need to gather more power consumption curve sample.
Along with the development of smart card, contactless smart card is more and more.Contactless smart card is to come for smart card power supply by field intensity, complete the read-write operation of data by the transmission of radio wave, like this work power consumption of smart card is required just higher, if we take to increase redundancy power consumption and defend this method of Differential power attack analysis, we need to increase extra redundancy power consumption, will make like this power consumption of whole smart card increase, thereby cause the waste of power consumption.General smart card all adopts monokaryon microprocessor architecture, carry out the enciphering and deciphering algorithm of deal with data with hardware on sheet or software, in order to defend Differential power attack analysis, adopt which kind of mode all can introduce extra circuit or functional module, its effect is to upset original data encrypting and deciphering power consumption curve chart.In essence, for the circuit adding or functional module, from taking the area of chip and the power consumption that work produces, only just meaningful in the time of defence differential power consumption analysis, other times are all wastes, and the area that has increased chip has also increased the power consumption of smart card.
Chinese patent (publication number: CN102983964A) discloses a kind of digital encryption standard of resisting differential power consumption analysis and has improved one's methods and install, and 64 plaintexts is carried out to 16 of digital encryption standard and take turns and in the S box function treatment step of computing, make the following new S box function being represented by SM-Box.The present invention, in conjunction with the S box function of different random number transformation, has destroyed the correlation between true key information and power consumption curve, brings great difficulty to reach to power consumption analysis obtaining information to resist the object of power consumption analysis.The present invention is simultaneously in conjunction with concealing technique, before cryptographic calculation, to expressly covering in advance, and carries out random number in taking turns computing and covers every, effectively prevented information leakage and attacked, and improved the ability of its resisting differential power consumption analysis attack.
Chinese patent (publication number: CN102970131A) discloses one can effectively resist technology and the circuit implementation structure thereof of by power consumption analysis (simple power consumption analysis SPA and differential power consumption analysis DPA) or electromagnetic radiation analysis (DEMA) technology, module, chip and the smart card card etc. of employing grouping enciphering and deciphering algorithm being attacked to obtain encryption and decryption computing key.In high security application of IC cards; such as but not limited to; in the applications such as electronic ID card, fiscard, social security card; the present invention can protect grouping algorithm module, chip and smart card card etc. effectively, prevents that encryption and decryption computing key from being decoded and obtaining by power consumption analysis or electromagnetic radiation analytical technology.The present invention can also, in continuous cryptographic calculation, improve the efficiency of cryptographic calculation, has ensured the execution efficiency of cryptographic calculation in improving the security protection intensity of grouping algorithm module, chip and smart card card etc.The present invention has good novelty, practicality and validity.
Above-mentioned existing invention all cannot solve because increased redundancy power consumption and defend Differential power attack analysis and cause that the power consumption of whole smart card increases, causing the circuit and the time of functional module outside defence differential power consumption analysis that add is all a kind of function waste, and increase the area of chip, increased the power consumption of smart card.
Summary of the invention
The present invention proposes a kind of method of smart card multi-core processor system and defence differential power consumption analysis thereof, native system uses multi-core microprocessor to process parallel enciphering and deciphering algorithm and data, each microprocessor is worked under asynchronous completely each other clock signal, each microprocessor work power consumption is disturbed power consumption each other, in the time processing other non-enciphering and deciphering algorithm tasks, polycaryon processor also can be opened operation simultaneously, can reach identical or exceed the performance of monokaryon smart card by less power consumption, and play the effect of defence Differential power attack analysis.
The invention provides a kind of smart card multi-core processor system, wherein, comprising:
The microprocessor that several are parallel, and each described microprocessor is all connected with an enciphering and deciphering algorithm function sub-modules both-way communication;
One clock generation module, this clock generating module is connected with described master microprocessor communication;
Wherein, described clock generating module sends several asynchronous clock signals to each described microprocessor, and each described microprocessor is processed the connected enciphering and deciphering algorithm function sub-modules of operation according to the clock signal of its reception.
Above-mentioned smart card multi-core processor system, wherein, a random number generation module is connected with described clock generating module communication;
Described random number generation module output random number sequence is to described clock generating module, and the random number sequence that this clock generating module receives according to it is carried out frequency division, phase deviation to source clock, to produce described several asynchronous clock signals.
Above-mentioned smart card multi-core processor system, wherein, described several asynchronous clock signals are corresponding one by one with described microprocessor, and phase place and frequency between any two described asynchronous clock signals is all not identical.
Above-mentioned smart card multi-core processor system, wherein, described smart card multi-core processor system is also provided with smart card memory;
Described smart card memory is connected with described clock generating module and described microprocessor respectively, and is also provided with external communication interface in its junction.
Above-mentioned smart card multi-core processor system, wherein, described multi-core processor system also comprises a common storage, and this common storage is connected with each described microprocessor communication respectively, and each described microprocessor also all both-way communication be connected with a local storage.
Above-mentioned smart card multi-core processor system, wherein, described enciphering and deciphering algorithm function sub-modules parallel arranged, and be all arranged in described local storage or described smart card memory.
Above-mentioned smart card multi-core processor system, wherein, realizes described enciphering and deciphering algorithm function sub-modules by hardware implementation mode, software realization mode or software-hardware synergism implementation.
The present invention also provides a kind of method of using polycaryon processor defence differential power consumption analysis, wherein, be applied on the smart card multi-core processor system described in above-mentioned any one, and this smart card multi-core processor system is provided with several microprocessors, and in these several microprocessors, include a primary processor, described method comprises:
Described primary processor sends enable signal to clock generating module;
Described clock generating module produces several asynchronous clock signals and uses to described several microprocessors;
Each described microprocessor is processed the connected enciphering and deciphering algorithm function sub-modules of operation according to the clock signal of its reception;
Wherein, when described several microprocessors are in the time processing connected enciphering and deciphering algorithm function sub-modules decipherment algorithm function sub-modules, the power consumption curve between any two microprocessors is all not identical.
The method of above-mentioned utilization polycaryon processor defence differential power consumption analysis, wherein, comprises a primary processor and several from processor in described several microprocessors, described method also comprises:
Described primary processor sends enable signal to random number generation module and clock generating module, and it is come into operation;
Described random number generation module produces random number sequence to described clock generating module;
The random number sequence that described clock generating module receives according to it is carried out frequency division, phase deviation to source clock, to produce several asynchronous clock signals.
The method of above-mentioned utilization polycaryon processor defence differential power consumption analysis, wherein, at least comprises clock source in described clock generating module, allocator module and phase shift module;
Described clock source produces a clock source successively by described allocator module and described phase shift module or successively by described phase shift module and described allocator module;
Described allocator module and described phase shift module are carried out after frequency division and phase deviation described clock source according to the random number sequence of its reception, export several asynchronous clock signals each other.
The method of above-mentioned utilization polycaryon processor defence differential power consumption analysis, wherein, described allocator module is carried out frequency division again to source clock, and changes its duty ratio.
The method of above-mentioned utilization polycaryon processor defence differential power consumption analysis, wherein, realizes described enciphering and deciphering algorithm function sub-modules by hardware implementation mode, software realization mode or software-hardware synergism implementation.
The present invention has following technical advantage:
1, the present invention processes parallel enciphering and deciphering algorithm and data by multi-core microprocessor, can reach identical or exceed the performance of monokaryon smart card by less power consumption.
2, multi-core microprocessor of the present invention is worked under asynchronous completely each other clock signal signal, and the work power consumption of each microprocessor disturbs power consumption effectively to defend Differential power attack analysis each other.
3, the present invention can realize on deep submicron process, and hardware area reduces greatly, and the frequency of smart card system work also increases greatly.
Brief description of the drawings
The accompanying drawing that forms a part of the present invention is used to provide a further understanding of the present invention, and schematic description and description of the present invention is used for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 is the structure chart of multi-core processor system of the present invention;
Fig. 2 is clock generating modular structure figure mono-;
Fig. 3 is clock generating modular structure figure bis-;
Fig. 4 is the first phase shift module structure chart;
Fig. 5 is three clock signal figure that while moving parallel enciphering and deciphering algorithm functional module (1) for the first time, the first phase shift module produces;
Fig. 6 is three clock signal figure that while moving parallel enciphering and deciphering algorithm functional module (1) for the second time, the first phase shift module produces;
Fig. 7 is three clock signal figure that while moving parallel enciphering and deciphering algorithm functional module (1) for the third time, the first phase shift module produces;
Fig. 8 is the second phase shift module structure chart;
Fig. 9 is three clock signal figure that while moving parallel enciphering and deciphering algorithm functional module (1) for the first time, the second phase shift module produces;
Figure 10 is three clock signal figure that while moving parallel enciphering and deciphering algorithm functional module (1) for the second time, the second phase shift module produces;
Figure 11 is three clock signal figure that while moving parallel enciphering and deciphering algorithm functional module (1) for the third time, the second phase shift module produces;
Figure 12 is clock signal frequency division module structure chart;
Figure 13 is three clock signal figure that while moving parallel enciphering and deciphering algorithm functional module (1) for the first time, under first method, allocator module produces;
Figure 14 is three clock signal figure that while moving parallel enciphering and deciphering algorithm functional module (1) for the second time, under first method, allocator module produces;
Figure 15 is three clock signal figure that while moving parallel enciphering and deciphering algorithm functional module (1) for the third time, under first method, allocator module produces;
Figure 16 is three clock signal figure that while moving parallel enciphering and deciphering algorithm functional module (1) for the first time, under second method, allocator module produces;
Figure 17 is three clock signal figure that while moving parallel enciphering and deciphering algorithm functional module (1) for the second time, under second method, allocator module produces;
Figure 18 is three clock signal figure that while moving parallel enciphering and deciphering algorithm functional module (1) for the third time, under second method, allocator module produces;
Figure 19 is three clock signal figure that while moving parallel enciphering and deciphering algorithm functional module (1) for the first time, clock signal generating module produces under first method;
Figure 20 is three clock signal figure that while moving parallel enciphering and deciphering algorithm functional module (1) for the second time, clock signal generating module produces under first method;
Figure 21 is three clock signal figure that while moving parallel enciphering and deciphering algorithm functional module (1) for the third time, clock signal generating module produces under first method;
Figure 22 is three clock signal figure that while moving parallel enciphering and deciphering algorithm functional module (1) for the first time, clock signal generating module produces under second method;
Figure 23 is three clock signal figure that while moving parallel enciphering and deciphering algorithm functional module (1) for the second time, clock signal generating module produces under second method;
Figure 24 is three clock signal figure that while moving parallel enciphering and deciphering algorithm functional module (1) for the third time, clock signal generating module produces under second method;
Figure 25 is that monokaryon microprocessor is realized enciphering and deciphering algorithm functional module structure figure with software form;
Figure 26 is that monokaryon microprocessor is realized enciphering and deciphering algorithm functional module structure figure with example, in hardware;
Figure 27 is that multi-core microprocessor is realized parallel enciphering and deciphering algorithm functional module (1) structure chart with software form;
Figure 28 is that multi-core microprocessor is realized parallel enciphering and deciphering algorithm functional module (1) figure with example, in hardware;
Figure 29 is concrete operations flow process of the present invention;
Figure 30 is embodiment 6 system construction drawings;
Figure 31 is embodiment 6 operational flowcharts;
Figure 32 is that system is moved the power consumption curve chart while walking abreast enciphering and deciphering algorithm functional module (1) for the first time;
Figure 33 is that system is moved the power consumption curve chart while walking abreast enciphering and deciphering algorithm functional module (1) for the second time;
Figure 34 is that system is moved the power consumption curve chart while walking abreast enciphering and deciphering algorithm functional module (1) for the third time.
Embodiment
In conjunction with following specific embodiments and the drawings, the present invention is described in further detail.Implement process of the present invention, condition, experimental technique etc., except the content of mentioning specially below, be universal knowledege and the common practise of this area, the present invention is not particularly limited content.
Embodiment mono-
The present invention proposes a kind of multi-core microprocessor system, its multi-core microprocessor structure chart, as shown in Figure 1.Wherein (1) is parallel enciphering and deciphering algorithm functional module, it is made up of N (several) enciphering and deciphering algorithm function sub-modules, be respectively enciphering and deciphering algorithm function sub-modules 1(2-1), enciphering and deciphering algorithm function sub-modules 2(2-2) to enciphering and deciphering algorithm function sub-modules N(2-N), (3) be multi-core microprocessor, formed by N (several) microprocessor, be respectively microprocessor 1(4-1), microprocessor 2(4-2) to microprocessor N(4-N), each microprocessor respectively both-way communication connects enciphering and deciphering algorithm function sub-modules, and each enciphering and deciphering algorithm function sub-modules of parallel processing, be microprocessor 1(4-1) the responsible enciphering and deciphering algorithm function sub-modules 1(2-1 that processes), microprocessor 2(4-2) the responsible enciphering and deciphering algorithm function sub-modules 2(2-2 that processes), microprocessor N(4-N) the responsible enciphering and deciphering algorithm function sub-modules N(2-N that processes), (5) be random number generation module, communication is connected random number generation module (5) with multi-core processor system, multi-core processor system arrives random number generation module (5) at the front enable signal that sends of the parallel enciphering and deciphering algorithm functional module (1) of each run, make it produce random number sequence, the random number sequence producing according to random number generation module (5), clock generating module (6) produces completely asynchronous N (several) clock signal, be respectively clock signal 1, clock signal 2 to clock signal N.When in multi-core processor system, (3) multi-core microprocessor is processed the parallel enciphering and deciphering algorithm functional module (1) of operation, N asynchronous clock signal be respectively as the work clock of N microprocessor, this N output services clock completely asynchronous in phase place and frequency (wherein N>=1 and be integer).
In the present invention, multi-core microprocessor is worked under completely asynchronous clock signal, and the asynchronous working time, clock generating module (6) produced by random number generation module (5).Wherein clock generating module (6) is by clock source (6-1), phase shift module (6-2) and allocator module (6-3) composition, as shown in Figure 2, wherein phase shift module (6-2) can be carried out phase deviation by the clock signal of input, the random number sequence that side-play amount is produced by random number generation module (5) determines, allocator module (6-3) can be carried out frequency division again by the clock signal of input, and can change the duty ratio of clock signal, the random number that wherein divider ratio and duty ratio are produced by random number sequence generation module (5) determines, phase shift module (6-2) and allocator module (6-3) order of connection are also interchangeable, as shown in Figure 3.The randomness of random number sequence producing due to random number generation module (5), ensureing that N(is some) individual clock signal is asynchronous each other, in the time of the parallel enciphering and deciphering algorithm functional module (1) of multi-core microprocessor (3) operation, N(is some) power consumption that produces of individual microprocessor disturbs each other, and the disturbed condition of each run is all different, completely random, thus reach the object of defending Differential power attack analysis.
Embodiment bis-
Fig. 4 is the first phase shift module structure chart; As shown in Figure 4, clock signal generating module is exported N phase place asynchronous clock signal mutually altogether, each clock signal is by some by M() individual field effect transistor and M(some) the individual resistance circuit that all different resistance composes in parallel produces, if field effect transistor conducting, resistance in parallel is inoperative, on the contrary, when the state of field effect transistor in closing, the clock signal phase on this clock signal phase offset path can be offset, and side-play amount is the resistance of closing field effect transistor parallel connection with this.Wherein each fet gate control end on each clock signal phase offset path is some from the M(of random number generation module (5) respectively) position random number output, being that every field effect transistor on clock signal phase offset path is some with M() the position random number sequence order of connection can be identical, and also can be different.In the time that the order of connection is identical, on every clock signal phase offset path, the resistance of each corresponding resistor must be different, for example: resistance 1_1 and resistance 1_2 and resistance 1_3 are different to resistance 1_N, by that analogy, resistance M_1 and resistance M_2 and resistance M_3 are different to resistance M_N; The phase place of each clock signal of guarantee is asynchronous like this, in the time that the order of connection is different, each corresponding resistance on each clock signal phase offset path can be identical, for example: RNS1_1 on working signal 1 phase deviation path, RNS2_1 is RN1 to M position random number sequence corresponding to RNSM_1, RN2 is to RNM, and on clock signal 2 phase deviation paths RNS1_2, RNS2_2 is RN4 to M position random number sequence corresponding to RNSM_2, RN6 ... to RN1.So when the random number of random number generation module (5) output one time M position, the field effect transistor opening and closing on each clock signal phase offset path is different, therefore the resistance of the resistance of each clock signal process is also different, i.e. phase deviation difference.System enables random number generation module (5) in the parallel front meeting of enciphering and deciphering algorithm functional module (1) of execution, random number generation module (5) produces a M position random number sequence and acts on phase shift module (6-2), the random number producing according to random number sequence, corresponding field effect transistor conducting or disconnection in phase shift module (6-2), thereby make source clock through different resistance, produce different phase places, the clock signal phase difference of output.(M is positive integer)
Particularly, the present embodiment is that three core microprocessor architectures (supposing now M=3, i.e. 3 random number sequences of random number generation module (5) output) are example, three microprocessors are worked under three mutual asynchronous clock signals, be made as respectively clock signal 1, clock signal 2, clock signal 3.We suppose the resistance 1_1 connecting on clock signal 1 offset path, resistance 2_1, and the phase deviation that resistance 3_1 produces is respectively 5 °, 10 ° and 15 °; The resistance 1_2 connecting on clock signal 2 offset paths, resistance 2_2, the phase deviation that resistance 3_2 produces is respectively 10 °, 15 ° and 5 °; The resistance 1_3 connecting on clock signal 3 offset paths, resistance 2_3, the phase deviation that resistance 3_3 produces is respectively 15 °, 20 ° and 10 °.
While carrying out parallel enciphering and deciphering algorithm functional module (1) for the first time, suppose that the random number sequence that random number generation module (5) produces is 010.In the network of clock signal 1, field effect transistor 1_1 and field effect transistor 3_1 disconnect, field effect transistor 2_1 conducting, and now source clock is through resistance 1_1 and resistance 3_1, and the phase deviation of generation is 20 °, and the phase deviation of clock signal 1 relative source clock is 20 °.In the network of the clock signal 2 of output, field effect transistor 1_2 and field effect transistor 3_2 disconnect, field effect transistor 2_2 conducting, and now source clock is through resistance 1_2 and resistance 3_2, and the phase deviation of generation is 15 °, and clock signal 2 relative source clock phase skews are 15 °.In the network of clock signal 3, field effect transistor 1_3 and field effect transistor 3_3 disconnect, field effect transistor 2_3 conducting, and now source clock is through resistance 1_3 and resistance 3_3, and the phase deviation of generation is 25 °, and clock signal 3 relative source clock phase skews are 25 °; Fig. 5 is three clock signal figure that while moving parallel enciphering and deciphering algorithm functional module (1) for the first time, the first phase shift module produces.While carrying out parallel enciphering and deciphering algorithm functional module (1) for the second time, suppose that the random number sequence that random number generation module (5) produces is 011.In the network of clock signal 1, field effect transistor 1_1 disconnects, field effect transistor 2_1 and field effect transistor 3_1 conducting, and now source clock is through resistance 1_1, and the phase deviation of generation is 5 °, and the phase deviation of clock signal 1 relative source clock is 5 °.In the network of clock signal 2, field effect transistor 1_2 disconnects, field effect transistor 2_2 and field effect transistor 3_2 conducting, and now source clock is through resistance 1_2, and the phase deviation of generation is 10 °, and the phase deviation of clock signal 2 relative source clocks is 10 °.In the network of clock signal 3, field effect transistor 1_3 disconnects, field effect transistor 2_3 and field effect transistor 3_3 conducting, now source clock is through resistance 1_3, the phase deviation producing is 15 °, the phase deviation of clock signal 3 relative source clocks is 15 °, and Fig. 6 is three clock signal figure that while moving parallel enciphering and deciphering algorithm functional module (1) for the second time, the first phase shift module produces.
While carrying out parallel enciphering and deciphering algorithm functional module (1) for the third time, suppose that the random number sequence that random number generation module (5) produces is 100.In the network of clock signal 1, field effect transistor 2_1 and field effect transistor 3_1 disconnect, field effect transistor 1_1 conducting, and now source clock is through resistance 2_1 and resistance 3_1, and the phase deviation of generation is 25 °, and the phase deviation of clock signal 1 relative source clock is 25 °.In the network of clock signal 2, field effect transistor 2_2 and field effect transistor 3_2 disconnect, field effect transistor 1_2 conducting, and now source clock is through resistance 2_2 and resistance 3_2, and the phase deviation of generation is 20 °, and the phase deviation of clock signal 2 relative source clocks is 20 °.In the network of clock signal 3, field effect transistor 2_3 and field effect transistor 3_3 disconnect, field effect transistor 1_3 conducting, now source clock is through resistance 2_3 and resistance 3_3, the phase deviation producing is 30 °, the phase deviation of clock signal 3 relative source clocks is 30 °, concrete clock signal and the phase deviation of generation, as shown in Figure 7.
Three the relative source of clock signal clock phase drift condition that when three parallel enciphering and deciphering algorithm functional modules (1) of operation, phase shift module (6-2) produces are as shown in table 1:
Table 1
As can be seen from the table, due to the randomness of random number sequence, each execution while walking abreast enciphering and deciphering algorithm functional module (1), the phase place of three clock signals is random.When the parallel enciphering and deciphering algorithm functional module (1) of adjacent twice execution, the work clock signal phase of identical microprocessor is also random, and therefore clock signal is that mutual phase place is asynchronous.
Embodiment tri-
Fig. 8 is the second phase shift module structure chart; As shown in Figure 8, export N clock signal, described N clock signal is through the network generation that composed in parallel by M field effect transistor and M resistance, wherein each resistance can be the same or different, be connected to the control signal in each fet gate on each clock signal phase offset path and export from the M position random number of random number generation module (5), and the order of connection can be identical on every clock signal phase offset path.System enables N random number generation module (5) in the parallel front meeting of enciphering and deciphering algorithm functional module (1) of each execution, random number generation module (5) successively produces N M position random number sequence, be taken up in order of priority and act on N clock signal output network, owing to acting on the M position random number sequence difference of each clock signal, the conducting of field effect transistor and disconnection are also different, the resistance number difference of process, finally causes the time delay of clock signal also different.
The present embodiment is example by three core microprocessor architectures (supposing now M=3), and three microprocessors are worked under the asynchronous clock signal control of three mutual phase places, are respectively clock signal 1, clock signal 2, clock signal 3.We suppose that the phase deviation that source clock signal produces through each resistance is 10 °.
When operation for the first time walks abreast enciphering and deciphering algorithm functional module (1), three random number sequences that random number generation module (5) successively produces are 010,101,100, these three random number sequences act on respectively clock signal 1 phase deviation path, clock signal 2 phase deviation paths, clock signal 3 phase deviation paths.In the network of clock signal 1, field effect transistor 1_1 and field effect transistor 3_1 disconnect, field effect transistor 2_1 conducting, and source clock, through two resistance, produces the phase deviation of 20 °, and therefore clock signal 1 relative source clock has the phase deviation of 20 °.In the network of clock signal 2, field effect transistor 2_2 disconnects, field effect transistor 1_2 and field effect transistor 3_2 conducting, and source clock, through a resistance, produces the phase deviation of 10 °, and now clock signal 2 relative source clocks have the phase deviation of 10 °.In the network of clock signal 3, field effect transistor 2_3 and field effect transistor 3_3 disconnect, field effect transistor 1_3 conducting, source clock is through two resistance, produce the phase deviation of 20 °, now clock signal 3 relative source clocks have the phase deviation of 20 °, and concrete clock signal and the phase deviation of generation are as shown in Figure 9.
When operation for the second time walks abreast enciphering and deciphering algorithm functional module (1), three random number sequences that random number generation module (5) successively produces are 100,101,110, these three random number sequences act on respectively clock signal 1 phase deviation path, clock signal 2 phase deviation paths, clock signal 3 phase deviation paths.In the network of clock signal 1, field effect transistor 2_1 and field effect transistor 3_1 disconnect, field effect transistor 1_1 conducting, and source clock, through two resistance, produces the phase deviation of 20 °, and therefore clock signal 1 relative source clock has the phase deviation of 20 °.In the network of clock signal 2, field effect transistor 2_2 disconnects, field effect transistor 1_2 and field effect transistor 3_2 conducting, and source clock, through a resistance, produces the phase deviation of 10 °, and now clock signal 2 relative source clocks have the phase deviation of 10 °.In the network of clock signal 3, field effect transistor 3_3 disconnects, field effect transistor 1_3 and field effect transistor 2_3 conducting, source clock is through a resistance, produce the phase deviation of 10 °, now clock signal 3 relative source clocks have the phase deviation of 10 °, and concrete clock signal and the phase deviation of generation are as shown in figure 10.
When operation for the third time walks abreast enciphering and deciphering algorithm functional module (1), three random number sequences that random number generation module (5) successively produces are 011,100,010, these three random number sequences act on respectively clock signal 1 phase deviation path, clock signal 2 phase deviation paths, clock signal 3 phase deviation paths.In the network of clock signal 1, field effect transistor 1_1 disconnects, field effect transistor 2_1 and field effect transistor 3_1 conducting, and source clock, through a resistance, produces the phase deviation of 10 °, and therefore clock signal 1 relative source clock has the phase deviation of 10 °.In the network of clock signal 2, field effect transistor 2_2 and field effect transistor 3_2 disconnect, field effect transistor 1_2 conducting, and source clock, through two resistance, produces the phase deviation of 20 °, and now clock signal 2 relative source clocks have the phase deviation of 20 °.In the network of clock signal 3, field effect transistor 1_3 and field effect transistor 3_3 disconnect, field effect transistor 2_3 conducting, and source clock, through two resistance, produces the phase deviation of 20 °, and now clock signal 3 relative source clocks have the phase deviation of 20 °.Concrete clock signal and the phase deviation of generation are as shown in figure 11.
Three the relative source of clock signal clock signal phase drift condition that when three operation enciphering and deciphering algorithm functional modules (1), phase shift module (6-2) produces are as shown in table 2:
Table 2
As can be seen from Table 2, due to the randomness of random number sequence, each execution while walking abreast enciphering and deciphering algorithm functional module (1), the phase place of three clock signals is random.When the parallel enciphering and deciphering algorithm functional module (1) of adjacent twice execution, the phase place of identical microprocessor work clock signal is also random, and therefore clock signal is that mutual phase place is asynchronous.
Embodiment tetra-
Figure 12 is clock signal frequency division module structure chart, as shown in figure 12, the random number sequence that allocator module (6-3) produces according to random number generation module (5), by input clock signal transfer to N frequency and duty ratio all different clock signal export.Now give an actual example and introduce two kinds of methods of allocator module (6-3) clocking.
The present embodiment is example by three core microprocessors, and the operation principle of these two kinds of clockings of clock signal frequency division module is described respectively.
First method is that random number generation module (5) produces a random number sequence in the time of the parallel enciphering and deciphering algorithm functional module (1) of each execution.Suppose that the random number sequence that random number generation module (5) produces is at 010 o'clock, clock signal 1, clock signal 2, clock signal 3 is respectively 1/2nd, 1/3rd, 1/4th of original clock signal frequency, and duty ratio is respectively 20%, 30%, and 40%; The random number sequence that random number generation module (5) produces is 011 o'clock, clock signal 1, and clock signal 2, clock signal 3 is respectively 1/3rd, 1/4th, 1/5th of original clock signal frequency, and duty ratio is respectively 30%, 40%, and 50%; The random number sequence that random number generation module (5) produces is 100 o'clock, clock signal 1, and clock signal 2, clock signal 3 is respectively 1/4th, 1/5th, 1/6th of original clock signal frequency, and duty ratio is respectively 40%, 50%, and 60%.Suppose that input clock signal frequency is 120M hertz.
When operation for the first time walks abreast enciphering and deciphering algorithm functional module (1), the random number sequence that random number generation module (5) produces is 010, clock signal 1, clock signal 2, the frequency of clock signal 3 is respectively 60M hertz, 40M hertz, 30M hertz, duty ratio is respectively 20%, 30%, and 40%.Concrete clock signal and frequency and duty ratio situation are as shown in Figure 13.
When operation for the second time walks abreast enciphering and deciphering algorithm functional module (1), the random number sequence that random number generation module (5) produces is 011, clock signal 1, clock signal 2, the frequency of clock signal 3 is respectively 40M hertz, 30M hertz, 24M hertz, duty ratio is respectively 30%, 40%, and 50%.Concrete clock signal and frequency and duty ratio situation are as shown in Figure 14.
When operation for the third time walks abreast enciphering and deciphering algorithm functional module (1), the random number sequence that random number generation module (5) produces is 100, clock signal 1, clock signal 2, the frequency of clock signal 3 is respectively 30M hertz, 24M hertz, 20M hertz, duty ratio is respectively 40%, 50%, and 60%.Concrete clock signal and frequency and duty ratio situation are as shown in Figure 15.
In the time carrying out parallel enciphering and deciphering algorithm functional module (1) three times, frequency and the duty ratio of three clock signals that allocator module produces are as shown in table 3:
Table 3
When each run walks abreast enciphering and deciphering algorithm module (1) as can be seen from Table 3, clock signal 1, clock signal 2, the frequency of clock signal 3 and duty ratio are all different, when the parallel enciphering and deciphering algorithm module (1) of adjacent twice operation, the frequency of identical clock signal and duty ratio are not identical yet.
When second method is the parallel enciphering and deciphering algorithm functional module (1) of each execution, random number generation module (5) successively produces N M position random number sequence.Suppose that the random number sequence that random number generation module (5) successively produces is at 010,101,100 o'clock, clock signal 1, clock signal 2, the frequency of clock signal 3 is respectively 1/2nd, 1/5th, 1/4th of input clock signal, duty ratio is respectively 20%, 50%, and 40%; The random number sequence that random number generation module (5) successively produces is 100,101,110 o'clock, clock signal 1, clock signal 2, the frequency of clock signal 3 is respectively 1/4th, 1/5th, 1/6th of input clock signal, duty ratio is respectively 40%, 50%, and 60%; The random number sequence that random number generation module (5) produces is 011,100,010 o'clock, clock signal 1, clock signal 2, the frequency of clock signal 3 is respectively 1/3rd, 1/4th, 1/2nd of input clock signal, duty ratio is respectively 30%, 40%, and 20%.The frequency of supposing input clock signal is 120M hertz.
When operation for the first time walks abreast enciphering and deciphering algorithm functional module (1), the random number sequence that random number generation module (5) successively produces is 010,101,100, clock signal 1, clock signal 2, the frequency of clock signal 3 is respectively 60M hertz, 24M hertz, 30M hertz, duty ratio is respectively 20%, 50%, and 40%.Concrete clock signal and frequency and duty ratio situation are as shown in figure 16.
When operation for the second time walks abreast enciphering and deciphering algorithm functional module (1), the random number sequence that random number generation module (5) successively produces is 100,101,110, clock signal 1, clock signal 2, the frequency of clock signal 3 is respectively 30M hertz, 24M hertz, 20M hertz, duty ratio is respectively 40%, 50%, and 60%.Concrete clock signal and frequency and duty ratio situation are as shown in figure 17.
When operation for the third time walks abreast enciphering and deciphering algorithm functional module (1), the random number sequence that random number generation module (5) successively produces is 011,100,010, clock signal 1, clock signal 2, the frequency of clock signal 3 is respectively 40M hertz, 30M hertz, 60M hertz, duty ratio is respectively 30%, 40%, and 20%.Concrete clock signal and frequency and duty ratio situation are as shown in figure 18.
In the time carrying out parallel enciphering and deciphering algorithm functional module (1) three times, frequency and the duty ratio of three clock signals that allocator module (6-3) produces are as shown in table 4:
Table 4
When each run walks abreast enciphering and deciphering algorithm module (1) as can be seen from Table 4, clock signal 1, clock signal 2, the frequency of clock signal 3 and duty ratio are all different, when the parallel enciphering and deciphering algorithm module (1) of adjacent twice execution, the frequency of identical clock signal and duty ratio are asynchronous (the random number output by random number generation module (5) determine).
Embodiment five
By the result of phase shift module (6-2) and allocator module (6-3) altogether, the present embodiment shows that the clock signal that clock signal generating module (6) produces is complete asynchronous clock signal to the present embodiment.
The present embodiment is still taking three core microprocessors (supposing M=3) as example.In the first situation, three microprocessors are worked under three mutual asynchronous clock signals, are made as respectively clock signal 1, clock signal 2, clock signal 3.We establish on clock signal 1 phase deviation path, resistance 1_1, and resistance 2_1, the phase deviation that resistance 3_1 produces is respectively 5 °, 10 ° 15 °; On clock signal 2 phase deviation paths, resistance 1_2, resistance 2_2, the phase deviation that resistance 3_2 produces is respectively 10 °, and 15 °, 5 °; On clock signal 3 phase deviation paths, resistance 1_3, resistance 2_3, the phase deviation that resistance 3_3 produces is respectively 15 °, and 20 °, 10 °.Suppose that the random number sequence that random number generation module (5) produces is at 010 o'clock, clock signal 1, clock signal 2, clock signal 3 is respectively 1/2nd, 1/3rd, 1/4th of original clock signal frequency, and duty ratio is respectively 20%, 30%, and 40%; The random number sequence that random number generation module (5) produces is 011 o'clock, clock signal 1, and clock signal 2, clock signal 3 is respectively 1/3rd, 1/4th, 1/5th of original clock signal frequency, and duty ratio is respectively 30%, 40%, and 50%; The random number sequence that random number generation module (5) produces is 100 o'clock, clock signal 1, and clock signal 2, clock signal 3 is respectively 1/4th, 1/5th, 1/6th of original clock signal frequency, and duty ratio is respectively 40%, 50%, and 60%.Suppose that input clock signal frequency is 120M hertz.
While carrying out parallel enciphering and deciphering algorithm functional module (1) for the first time, suppose that the random number sequence that random number generation module (5) produces is 010.From phase shift module (6-2), clock signal 1, clock signal 2, the phase deviation that clock signal 3 relative source clock signals produce is respectively 20 °, and 15 °, 25 °.From allocator module (6-3), clock signal 1, clock signal 2, the frequency of clock signal 3 is respectively 60M hertz, 40M hertz, 30M hertz, duty ratio is respectively 20%, 30%, and 40%.Concrete clock signal phase and frequency duty ratio situation are as shown in figure 19.
While carrying out parallel enciphering and deciphering algorithm functional module (1) for the second time, suppose that the random number sequence that random number generation module (5) produces is 011.From phase shift module (6-2), clock signal 1, clock signal 2, the phase deviation that clock signal 3 relative source clock signals produce is respectively 5 °, and 10 °, 15 °.From allocator module (6-3), clock signal 1, clock signal 2, the frequency of clock signal 3 is respectively 40M hertz, 30M hertz, 24M hertz, duty ratio is respectively 30%, 40%, and 50%.Concrete clock signal phase and frequency duty ratio situation are as shown in figure 20.
While carrying out parallel enciphering and deciphering algorithm functional module (1) for the third time, suppose that the random number sequence that random number generation module (5) produces is 100.From phase shift module (6-2), clock signal 1, clock signal 2, the phase deviation that clock signal 3 relative source clock signals produce is respectively 25 °, and 20 °, 30 °.From allocator module (6-3), clock signal 1, clock signal 2, the frequency of clock signal 3 is respectively 30M hertz, 24M hertz, 20M hertz, duty ratio is respectively 40%, 50%, and 60%.Concrete clock signal phase and frequency duty ratio situation are as shown in figure 21.
In the second situation, three microprocessors are worked under three mutual asynchronous clock signal controls, are respectively clock signal 1, clock signal 2, clock signal 3.We suppose that the phase deviation that source clock signal produces through each resistance is 10 °.Suppose that the random number sequence that random number generation module (5) successively produces is at 010,101,100 o'clock, clock signal 1, clock signal 2, the frequency of clock signal 3 is respectively 1/2nd, 1/5th, 1/4th of input clock signal, duty ratio is respectively 20%, 50%, and 40%; The random number sequence that random number generation module (5) successively produces is 100,101,110 o'clock, clock signal 1, clock signal 2, the frequency of clock signal 3 is respectively 1/4th, 1/5th, 1/6th of input clock signal, duty ratio is respectively 40%, 50%, and 60%; The random number sequence that random number generation module (5) successively produces is 011,100,010 o'clock, clock signal 1, clock signal 2, the frequency of clock signal 3 is respectively 1/3rd, 1/4th, 1/2nd of input clock signal, duty ratio is respectively 30%, 40%, and 20%.The frequency of supposing input clock signal is 120M hertz.
When operation for the first time walks abreast enciphering and deciphering algorithm functional module (1), three random number sequences that random number generation module (5) successively produces are 010,101,100, from phase shift module (6-2), clock signal 1, clock signal 2, the phase deviation that clock signal 3 relative source clock signals produce is respectively 20 °, and 10 °, 20 °.From allocator module (6-3), clock signal 1, clock signal 2, the frequency of clock signal 3 is respectively 60M hertz, 24M hertz, 30M hertz, duty ratio is respectively 20%, 50%, and 40%.Concrete clock signal phase and frequency duty ratio situation are as shown in figure 22.
When operation for the second time walks abreast enciphering and deciphering algorithm functional module (1), three random number sequences that random number generation module (5) successively produces are 100,101,110, from phase shift module (6-2), clock signal 1, clock signal 2, the phase deviation that clock signal 3 relative source clock signals produce is respectively 20 °, and 10 °, 10 °.From allocator module (6-3), clock signal 1, clock signal 2, the frequency of clock signal 3 is respectively 30M hertz, 24M hertz, 20M hertz, duty ratio is respectively 40%, 50%, and 60%.Concrete clock signal phase and frequency duty ratio situation are as shown in figure 23.
When operation for the third time walks abreast enciphering and deciphering algorithm functional module (1), three random number sequences that random number generation module (5) successively produces are 011,100,010, from phase shift module (6-2), clock signal 1, clock signal 2, the phase deviation that clock signal 3 relative source clock signals produce is respectively 10 °, and 20 °, 20 °.From allocator module (6-3), clock signal 1, clock signal 2, the frequency of clock signal 3 is respectively 40M hertz, 30M hertz, 60M hertz, duty ratio is respectively 30%, 40%, and 20%.Concrete clock signal phase and frequency duty ratio situation are as shown in figure 24.
Embodiment 6
The system of general defence Differential power attack analysis adopts monokaryon microprocessor, and enciphering and deciphering algorithm functional module adopts coprocessor or pure hardware or pure software to realize.Figure 25 is that monokaryon microprocessor is realized enciphering and deciphering algorithm functional module structure figure with software form; Now enciphering and deciphering algorithm functional module (1) realizes with software, this single core processor system is by microprocessor (2), local storage (3) forms, enciphering and deciphering algorithm functional module (1) is stored in local storage (3), in the time that microprocessor (2) is carried out enciphering and deciphering algorithm functional module (1), from local storage (3), call.Figure 26 is that monokaryon microprocessor is realized enciphering and deciphering algorithm functional module structure figure with example, in hardware; Now enciphering and deciphering algorithm functional module (1) adopts pure hardware to realize, system is by microprocessor (2), local storage (3) and enciphering and deciphering algorithm functional module (1) composition, to realize enciphering and deciphering algorithm different from adopting software, while adopting pure hardware to realize, enciphering and deciphering algorithm is not stored in local storage (3).
For the smart card in the present embodiment, we adopt multi-core microprocessor to process structure, realize described enciphering and deciphering algorithm function sub-modules by hardware implementation mode, software realization mode or software-hardware synergism implementation.Figure 27 is that multi-core microprocessor is realized parallel enciphering and deciphering algorithm functional module (1) structure chart with software form; As shown in figure 27, we are divided into N separate part at the enciphering and deciphering algorithm functional module (1) that will walk abreast, and each microprocessor is carried out a part wherein.System is microprocessor 1(4-1 by multi-core microprocessor (3)), microprocessor 2(4-2), to microprocessor N(4-N), local storage (7), random number generation module (5), clock signal generating module (6) forms, and now enciphering and deciphering algorithm is stored in local storage (7).
Figure 28 is that multi-core microprocessor is realized parallel enciphering and deciphering algorithm functional module (1) figure with example, in hardware; Multi-core processor system is microprocessor 1(4-1 by multi-core microprocessor (3)), microprocessor 2(4-2), to microprocessor N(4-N), local storage (7), random number generation module (5), clock signal generating module (6) forms, and now enciphering and deciphering algorithm is realized by hardware, and operation clock signal is respectively clock signal 1, clock signal 2 to clock signal N.Figure 29 is concrete operations flow process of the present invention; As shown in figure 29, be concrete operating procedure of the present invention below:
Step 1: multi-core processor system is before preparing to call parallel enciphering and deciphering algorithm functional module, multi-core processor system sends enable signal, make random number generation module and clock signal generating module produce N asynchronous clock signal each other, be respectively clock signal 1, clock signal 2, clock signal 3, to clock signal N, as microprocessor 1, microprocessor 2, the work clock signal of microprocessor 3 to microprocessor N;
Step 2: microprocessor 1, microprocessor 2. microprocessors 3 to microprocessor N are respectively in asynchronous each other clock signal 1, clock signal 2, clock signal 3 is worked under clock signal N, process respectively N parallel enciphering and deciphering algorithm function sub-modules, be enciphering and deciphering algorithm submodule 1, enciphering and deciphering algorithm function sub-modules 2, enciphering and deciphering algorithm function sub-modules 3 to enciphering and deciphering algorithm function sub-modules N;
Step 3: after the complete parallel enciphering and deciphering algorithm functional module of system call, system can exit asynchronous work mode, processes other work.
Particularly, the smart card in the present embodiment adopts three core microprocessors, and Figure 30 is embodiment 6 system construction drawings; Figure 31 is embodiment 6 operational flowcharts; As shown in figure 30, multi-core microprocessor system is made up of three microprocessors, is respectively (1) microprocessor 1, (2) microprocessor 2, (3) microprocessor 3, wherein microprocessor 1(1) be master microprocessor, microprocessor 2(2) and microprocessor 3(3) be from microprocessor.Master microprocessor (1) can the external communication interface of access intelligent card (4), random number generation module (5), smart card memory (7), wherein the external communication interface of smart card (4) can be 7816 interfaces etc., in smart card memory (7), storing parallel enciphering and deciphering algorithm functional module, (also can be stored in local storage) parallel enciphering and deciphering algorithm functional module is divided into three parts, be respectively enciphering and deciphering algorithm function sub-modules 1, enciphering and deciphering algorithm function sub-modules 2 and enciphering and deciphering algorithm function sub-modules 3.Local storage 1(8), local storage 2(9), local storage 3(10) be respectively microprocessor 1(1), microprocessor 2(2) and microprocessor 3(3) local storage, can not be by other microprocessor access.Common storage (11) can, by each microprocessor access, wherein deposited shared data.Microprocessor 1(1), microprocessor 2(2) and microprocessor 3(3) work clock signal be respectively clock signal 1, clock signal 2 and clock signal 3, produced by (6) clock signal generating module, the phase place that it is concrete and frequency produce random number sequence by random number generation module (5) and determine, and random number generation module (5) also can be by master microprocessor (1) access, concrete job step as shown in figure 31:
Step 1: microprocessor (1) will be stored in the parallel enciphering and deciphering algorithm function sub-modules 1 on smart card memory (7), enciphering and deciphering algorithm submodule 2 and enciphering and deciphering algorithm submodule 3 are put into respectively local storage 1(8), local storage 2(9), local storage 3(10) in;
Step 2: microprocessor 1(1) enable random number generation module (5) produce random number sequence, thereby make clock signal generating module (6) produce all different three asynchronous clock signals of phase place and frequency, be respectively clock signal 1, clock signal 2, clock signal 3;
Step 3: microprocessor 1(1) produce enable signal and make microprocessor 2(2) and microprocessor 3(3) effective, microprocessor 1(1), microprocessor 2(2) and microprocessor 3(3) in clock signal 1, clock signal 2 and clock signal are processed enciphering and deciphering algorithm function sub-modules 1, enciphering and deciphering algorithm function sub-modules 2 and enciphering and deciphering algorithm function sub-modules 33 times;
Step 4: parallel enciphering and deciphering algorithm operation is complete, microprocessor 1(1) close microprocessor 2(2) and microprocessor 3(3);
Step 5: microprocessor 1(1) control clock signal generating module (6), close clock signal 2 and clock signal 3 is exported;
Step 6: multi-core microprocessor is processed other tasks.
Embodiment seven
The concrete validity that adopts three core microprocessor system explanation the present invention to defend Differential power attack analysis in the present embodiment.Parallel enciphering and deciphering algorithm functional module is divided into three parts, be respectively enciphering and deciphering algorithm function sub-modules 1, enciphering and deciphering algorithm function sub-modules 2 and enciphering and deciphering algorithm function sub-modules 3, microprocessor 1(1) operation enciphering and deciphering algorithm function sub-modules 1, microprocessor 2(2) operation enciphering and deciphering algorithm function sub-modules 2, microprocessor 3 is processed enciphering and deciphering algorithm submodule 3, and here we realize enciphering and deciphering algorithm with software.Three microprocessors are worked under three asynchronous clock signals, i.e. microprocessor 1(1) at 1 time work of clock signal, microprocessor 2(2) at 2 times work of clock signal, microprocessor 3(3) in 3 times work of clock signal.Clock signal generating module (6) produces three asynchronous clock signals according to first method, and when each run walks abreast enciphering and deciphering algorithm functional module, random number generation module (5) only produces a random number sequence.We suppose that source clock signal frequency is 120M hertz, from the analysis about clock signal generating module (6) above, under first method, the random number sequence that random number generation module produces is 010, clock signal 1, clock signal 2, the phase deviation that clock signal 3 relative source clock signals produce is respectively 20 °, and 15 °, 25 °, clock signal 1, clock signal 2, the frequency of clock signal 3 is respectively 60M hertz, 40M hertz, 30M hertz, duty ratio is respectively 20%, 30%, 40%; The random number sequence that random number generation module produces is 011, clock signal 1, clock signal 2, the phase deviation that clock signal 3 relative source clock signals produce is respectively 5 °, and 10 °, 15 °, clock signal 1, clock signal 2, the frequency of clock signal 3 is respectively 40M hertz, 30M hertz, 24M hertz, duty ratio is respectively 30%, 40%, and 50%; The random number sequence that random number generation module produces is 100, clock signal 1, clock signal 2, the phase deviation that clock signal 3 relative source clock signals produce is respectively 25 °, and 20 °, 30 °, clock signal 1, clock signal 2, the frequency of clock signal 3 is respectively 30M hertz, 24M hertz, 20M hertz, duty ratio is respectively 40%, 50%, and 60%.Microprocessor 1(1) second of clock signal 1, the 4th rising edge produces larger power consumption while processing enciphering and deciphering algorithm submodule 1, microprocessor 2(2) at first of clock signal 2, the 3rd rising edge produces larger power consumption while processing enciphering and deciphering algorithm submodule 2, microprocessor 3(3) clock signal 3 first, when second rising edge processing enciphering and deciphering algorithm submodule 3, produce larger power consumption.
When operation for the first time walks abreast enciphering and deciphering algorithm functional module, the random number sequence that random number generation module (5) produces is 010, so three asynchronous clock signals that clock signal generating module (6) produces are clock signal 1, clock signal 2, the phase deviation that clock signal 3 relative source clock signals produce is respectively 20 °, 15 °, 25 °, clock signal 1, clock signal 2, the frequency of clock signal 3 is respectively 60M hertz, 40M hertz, 30M hertz, duty ratio is respectively 20%, 30%, 40%, so power consumption curve chart when operation for the first time walks abreast enciphering and deciphering algorithm shown in figure 32, we can find out 3 peak values on system power dissipation figure.
When operation for the second time walks abreast enciphering and deciphering algorithm functional module, the random number sequence that random number generation module (5) produces is 011, so three asynchronous clock signals that clock signal generating module (6) produces are clock signal 1, clock signal 2, the phase deviation that clock signal 3 relative source clock signals produce is respectively 5 °, 10 °, 15 °, clock signal 1, clock signal 2, the frequency of clock signal 3 is respectively 40M hertz, 30M hertz, 24M hertz, duty ratio is respectively 30%, 40%, 50%, power consumption curve chart when parallel running enciphering and deciphering algorithm as shown in Figure 33 for the second time, we can find out 3 peak values on system power dissipation figure.
When operation for the third time walks abreast enciphering and deciphering algorithm functional module, the random number sequence that random number generation module (5) produces is 100, so three asynchronous clock signals that clock signal generating module (6) produces are clock signal 1, clock signal 2, the phase deviation that clock signal 3 relative source clock signals produce is respectively 25 °, 20 °, 30 °, clock signal 1, clock signal 2, the frequency of clock signal 3 is respectively 30M hertz, 24M hertz, 20M hertz, duty ratio is respectively 40%, 50%, 60%, power consumption curve chart when operation for the third time walks abreast enciphering and deciphering algorithm as shown in figure 34, we can find out 4 peak values on system power dissipation figure.
By that analogy, due to the random number sequence difference of random number generation module (5) generation on sheet, make the clock signal that on sheet, clock signal module (6) produces completely asynchronous, thereby make the curve difference of each microprocessor power consumption in the time carrying out enciphering and deciphering algorithm function sub-modules, last total power consumption curve is also different, there is the number of peak value, amplitude and position are all different, even if gather so many again that power consumption curve gathers, also cannot crack out user's key information, therefore the present invention has the ability of good defence Differential power attack analysis.
The present invention proposes a kind of method of smart card multi-core processor system and defence differential power consumption analysis thereof, multi-core processor system uses multi-core microprocessor to come the parallel enciphering and deciphering algorithm of parallel processing and data, each multi-core microprocessor is worked under asynchronous completely each other clock signal, each microprocessor work power consumption is disturbed power consumption each other, in the time processing other non-enciphering and deciphering algorithm tasks, polycaryon processor also can be opened operation simultaneously, can reach identical or exceed the performance of monokaryon smart card by less power consumption.Although the smart card of monokaryon microprocessor architecture relatively, the present invention has increased area, but these areas are not redundancy, all can participate in running while comprising enciphering and deciphering algorithm or other mode of operations any, and the power consumption producing in the time that data encrypting and deciphering is worked neither redundancy, spend on data encrypting and deciphering for each joule, and there is the ability of defence Differential power attack analysis.
These are only preferred embodiment of the present invention; not thereby limit embodiments of the present invention and protection range; to those skilled in the art; the scheme that being equal to of should recognizing that all utilizations specification of the present invention and diagramatic content make replaces and apparent variation obtains, all should be included in protection scope of the present invention.
Claims (12)
1.
?a kind of smart card multi-core processor system, is characterized in that, comprising:
The microprocessor that several are parallel, and each described microprocessor is all connected with an enciphering and deciphering algorithm function sub-modules both-way communication;
One clock generation module, this clock generating module is connected with described master microprocessor communication;
Wherein, described clock generating module sends several asynchronous clock signals to each described microprocessor, and each described microprocessor is processed the connected enciphering and deciphering algorithm function sub-modules of operation according to the clock signal of its reception.
2. smart card multi-core processor system as claimed in claim 1, is characterized in that, a random number generation module is connected with described clock generating module communication;
Described random number generation module output random number sequence is to described clock generating module, and the random number sequence that this clock generating module receives according to it is carried out frequency division, phase deviation to source clock, to produce described several asynchronous clock signals.
3. smart card multi-core processor system as claimed in claim 1, is characterized in that, described several asynchronous clock signals are corresponding one by one with described microprocessor, and phase place and frequency between any two described asynchronous clock signals is all not identical.
4. smart card multi-core processor system as described in any one in claim 1～3, is characterized in that, described smart card multi-core processor system is also provided with smart card memory;
Described smart card memory is connected with described clock generating module and described microprocessor respectively, and is also provided with external communication interface in its junction.
5. smart card multi-core processor system as claimed in claim 4, it is characterized in that, described multi-core processor system also comprises a common storage, this common storage is connected with each described microprocessor communication respectively, and each described microprocessor also all both-way communication be connected with a local storage.
6. smart card multi-core processor system as claimed in claim 5, is characterized in that described enciphering and deciphering algorithm function sub-modules parallel arranged, and is all arranged in described local storage or described smart card memory.
7. smart card multi-core processor system as claimed in claim 1, is characterized in that, realizes described enciphering and deciphering algorithm function sub-modules by hardware implementation mode, software realization mode or software-hardware synergism implementation.
8. one kind is used the method for polycaryon processor defence differential power consumption analysis, it is characterized in that, be applied in the claims 1～7 on the smart card multi-core processor system described in any one, and this smart card multi-core processor system is provided with several microprocessors, and in these several microprocessors, include a primary processor, described method comprises:
Described primary processor sends enable signal to clock generating module;
Described clock generating module produces several asynchronous clock signals and uses to described several microprocessors;
Each described microprocessor is processed the connected enciphering and deciphering algorithm function sub-modules of operation according to the clock signal of its reception;
Wherein, when described several microprocessors are in the time processing connected enciphering and deciphering algorithm function sub-modules decipherment algorithm function sub-modules, the power consumption curve between any two microprocessors is all not identical.
9. the method for using as claimed in claim 8 polycaryon processor defence differential power consumption analysis, is characterized in that, comprises a primary processor and several from processor in described several microprocessors, and described method also comprises:
Described primary processor sends enable signal to random number generation module and clock generating module, and it is come into operation;
Described random number generation module produces random number sequence to described clock generating module;
The random number sequence that described clock generating module receives according to it is carried out frequency division, phase deviation to source clock, to produce several asynchronous clock signals.
10. the method for using as claimed in claim 9 polycaryon processor defence differential power consumption analysis, is characterized in that, at least comprises clock source, allocator module and phase shift module in described clock generating module;
Described clock source produces a clock source successively by described allocator module and described phase shift module or successively by described phase shift module and described allocator module;
Described allocator module and described phase shift module are carried out after frequency division and phase deviation described clock source according to the random number sequence of its reception, export several asynchronous clock signals each other.
11. use the method for polycaryon processor defence differential power consumption analysis as claimed in claim 10, it is characterized in that, described allocator module is carried out frequency division again to source clock, and changes its duty ratio.
12. use the method for polycaryon processor defence differential power consumption analysis as claimed in claim 8, it is characterized in that, realize described enciphering and deciphering algorithm function sub-modules by hardware implementation mode, software realization mode or software-hardware synergism implementation.
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| CN105894079A (en) * | 2016-04-22 | 2016-08-24 | 上海东软载波微电子有限公司 | Clock scrambling circuit |
| CN106850214A (en) * | 2017-03-13 | 2017-06-13 | 上海新储集成电路有限公司 | A kind of parallel encipher-decipher method |
| CN107302432A (en) * | 2017-06-30 | 2017-10-27 | 何安平 | A kind of crypto chip based on asynchronous data-path |
| CN108075877A (en) * | 2016-11-15 | 2018-05-25 | 华为技术有限公司 | A kind of security system and terminal chip |
| CN109257395A (en) * | 2018-12-07 | 2019-01-22 | 四川长虹电器股份有限公司 | The system for resisting bypass attack |
| CN113505095A (en) * | 2021-07-30 | 2021-10-15 | 上海壁仞智能科技有限公司 | System-on-chip and integrated circuit with multi-core out-of-phase processing |
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| CN104460825A (en) * | 2014-11-25 | 2015-03-25 | 上海高性能集成电路设计中心 | Multi-core processor clock distribution device |
| CN105894079A (en) * | 2016-04-22 | 2016-08-24 | 上海东软载波微电子有限公司 | Clock scrambling circuit |
| CN105894079B (en) * | 2016-04-22 | 2019-03-15 | 上海东软载波微电子有限公司 | Clock scrambling circuit |
| CN108075877A (en) * | 2016-11-15 | 2018-05-25 | 华为技术有限公司 | A kind of security system and terminal chip |
| CN108075877B (en) * | 2016-11-15 | 2022-04-29 | 华为技术有限公司 | Safety system and terminal chip |
| CN106850214A (en) * | 2017-03-13 | 2017-06-13 | 上海新储集成电路有限公司 | A kind of parallel encipher-decipher method |
| CN107302432A (en) * | 2017-06-30 | 2017-10-27 | 何安平 | A kind of crypto chip based on asynchronous data-path |
| CN107302432B (en) * | 2017-06-30 | 2020-06-09 | 何安平 | Password chip based on asynchronous data path |
| CN109257395A (en) * | 2018-12-07 | 2019-01-22 | 四川长虹电器股份有限公司 | The system for resisting bypass attack |
| CN113505095A (en) * | 2021-07-30 | 2021-10-15 | 上海壁仞智能科技有限公司 | System-on-chip and integrated circuit with multi-core out-of-phase processing |
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