CN103561118B - A kind of interface message processing means - Google Patents

Abstract

The invention belongs to wired digital communication system, it is specifically related to a kind of interface message processing means, after purpose is that the information all kinds of navigator produced processes, being supplied to each information by network system and show that realizing marine navigation information with control station shows and boats and ships manipulation, network system is by interconnective two Ethernet switches of netting twine.The present invention has eight serial line interfaces and a CAN interface for receiving navigator signal; and send into Ethernet switch after the navigator signal of reception is converted to ethernet signal with former navigator signal communications protocol format; the present invention and two Ethernet switches are connected respectively by the most active and standby netting twine; there is disconnected cable protection function; when the Ethernet switch fault that disconnected cable or main push-towing rope are connected occurs, rapidly business can be switched to standby cable.

Description

A kind of interface message processing means

Technical field

The invention belongs to wired digital communication system, be specifically related to a kind of interface message processing means.

Background technology

The various kinds of equipment that some high-end product the most external has realized comprehensive bridge by IP network peculiar to vessel interconnects and letter Breath share and Seamless integration-, and domestic composite ship bridge system product also in development elementary step, most of equipment and Function has relative independentability, lacks network information transfer and the shared platform of integration, and degree of integration is the highest.

Summary of the invention

It is an object of the invention to overcome above-mentioned deficiency, it is provided that a kind of interface message processing means, higher with degree of integration Realize integrated network information transmission and information sharing.

For realizing above-mentioned technical purpose, the scheme that the present invention provides is: a kind of interface message processing means, including CPU mould Block, node number arrange module, serial ports expansion module, P serial interface module, CPLD module, CAN interface module and relay mould Block, wherein 1≤P≤16, P is natural number, and the internal address bus of CPU module, the signal of internal data bus pass through total respectively Line buffer gives address, data/address bus after driving, and CPU module couples serial ports expansion mould by address, data, control bus Block, CPU module arranges module and P serial interface module, CPU mould by controlling bus and data/address bus joint period respectively After the control bus of block and address bus are connected into CPLD module, CPLD resume module the new control signal obtained, then and data Bus connects CAN interface module together, and CPU module is by coupling two Ethernet interfaces, serial ports expansion mould after relay module Block is connected with P the serial interface module signal of telecommunication.

And, described node number arranges module and includes Q road dial switch and buffer chip, wherein 1≤Q≤8, and Q is certainly So number, dial switch one end, each road ground connection, the other end couples the data input pin of buffer chip after concatenating pull-up resistor respectively, In the dial switch of Q road, each road is separately provided on off operating mode, and the data output end of buffer chip couples CPU by data/address bus Module.

And, described serial ports expansion module all includes that the generic asynchronous serial communication chip of R sheet independence, every chip can prop up Holding the serial communication of X road independence, wherein X=1 or 2 or 4 or 8, R=2P/X, wherein R, P are natural number, every road transmission of chip With receiving unit, all there is independent serioparallel exchange and parallel-serial conversion.

And, described serial interface module is RS232 interface module, this RS232 interface module include a piece of independent can Support the RS232 electrical level transferring chip of two-way serial ports, eight road dial switch and buffer chip, eight dial switch Zhong Ge roads, road Switch one end ground connection, the other end couples buffer chip data input pin, in eight road dial switches after concatenating pull-up resistor respectively Each road is separately provided on off operating mode, and eight circuit-switched data outfans of buffer chip couple CPU module by data/address bus respectively, CPU module couples with buffer chip Enable Pin by controlling bus.

And, described serial interface module is RS422/485 interface module, and this RS422/485 interface module includes two panels The RS422/485 electrical level transferring chip of a road serial ports, eight road dial switch and buffer chip can be supported, in eight road dial switches Each way switch one end ground connection, the other end concatenates respectively and connects buffer chip data input pin after pull-up resistor, eight tunnels dialing In switch, each road is separately provided on off operating mode, and eight circuit-switched data outfans of buffer chip are coupled by data/address bus respectively CPU module, CPU module couples with buffer chip Enable Pin by controlling bus.

And, described relay module includes signal drive circuit, optocoupler drive circuit and two dpdt relays, The Ethernet switch-over control signal of CPU module output couples two inputs of signal drive circuit, passes through signal drive circuit Two outfans after driving couple the input of optocoupler drive circuit respectively, two outputs after optocoupler drive circuit drives End couples the coil of two relays respectively and controls anode, and the coil of two relays controls negative terminal ground connection respectively.

And, described CPU module include cpu chip, reset circuit, main memory circuit, program storing circuit, clock circuit, Ethernet circuit and bus buffer, cpu chip couples with clock circuit, the reset circuit signal of telecommunication respectively, and cpu chip is by control Bus processed, internal address bus and internal data bus are with main memory circuit, program storing circuit and the bus buffer signal of telecommunication even Connect, after cpu chip couples with the ethernet circuit signal of telecommunication, it is provided that an internal 100M Ethernet interface and described relay module Connect；Described CAN interface module is by the CAN controller chip of a piece of support one road CAN interface and supports driving of a road CAN interface Dynamic transceiver composition.

And, described cpu chip is address, data/address bus multiplex chip, and described CAN controller chip is address, number According to bus-sharing chip.During the once read-write of cpu chip, data wire output data, address wire OPADD, and CAN controller The read-write of chip makes two bites at a cherry, and the trailing edge sampling address/data lines at certain pin (address latch signal foot) obtained before this Address, then the trailing edge sampling address/data lines at another pin (data enable signal pins) obtains data, in the present invention A read or write of CAN controller chip is realized with the operation of twice cpu chip.By cpu chip by drive after Minimum 8 position datawires corresponding 8 address/data lines being connected into CAN controller chip respectively.By the read-write of cpu chip, certain Certain high address line after sheet choosing and driving is connected into CPLD module, obtains a series of new signal and be connected into CAN after conversion Controller chip: chip selection signal, address latch signal, data enable signal and read-write.

And, described address, data/address bus multiplex chip and described address, multiplexed data bus chip with the use of Method is, realizes a write operation of CAN controller chip continuously with the write operation of twice cpu chip, continuously with a CPU The read operation of the write operation of chip and a cpu chip realizes a read operation of CAN controller chip.Wherein for the first time The write operation of cpu chip realizes in address to be operated write CAN controller chip, and the write operation of cpu chip realizes for the second time Writing data in CAN controller chip, the read operation of cpu chip for the second time realizes reading data from CAN controller chip Go out.

The present invention can realize the collection of the navigation through electronic information that full ship is handled about navigation, and is converted into Ethernet letter Number, it is supplied to each information with IP data packet form by composite ship bridge network system and shows shared with control station.

Accompanying drawing explanation

Fig. 1 is present device and network system connection block diagram.

Fig. 2 is present device module composition frame chart.

Fig. 3 is the CPU module composition frame chart of present device.

Fig. 4 is that the node number of present device arranges module composition frame chart.

Fig. 5 is serial interface module embodiment one composition frame chart of present device.

Fig. 6 is serial interface module embodiment two composition frame chart of present device.

Fig. 7 is the CAN interface module composition frame chart of present device.

Fig. 8 is the relay module composition frame chart of present device.

Detailed description of the invention

Below in conjunction with the accompanying drawings and embodiment the invention will be further described.

The present embodiment provides a kind of interface message processing means, as it is shown in figure 1, this interface message processing means J1 has eight Individual serial line interface and a CAN interface, be used for receiving navigator signal, and set with former navigation by the navigator signal of reception Standby signal communications protocol format sends into Ethernet switch S1 or S2, at the interface message of the present invention after being converted to ethernet signal Reason device J1 and Ethernet switch S1 is connected by Ethernet main push-towing rope, and Ethernet switch S2 is by Ethernet for cable even Connecing, interface message processing means J1 is connected with Ethernet switch S1 under normal circumstances, when Ethernet main push-towing rope breaks cable or Ethernet During switch S1 fault, interface message processing means J1, by controlling relay module action, disconnects with Ethernet main push-towing rope, simultaneously It is connected for cable with Ethernet, rapidly business is switched to standby cable, is connected with Ethernet switch S2.

As in figure 2 it is shown, the interface message processing means of the present invention includes that CPU module 1, node number arrange module 2, serial ports expands Exhibition 3,4 serial interface module 4A, 4B, 4C, 4D, CPLD modules 5 of module, CAN interface module 6 and relay module 7.

As it is shown on figure 3, CPU module by cpu chip, reset circuit, main memory circuit, program storing circuit, clock circuit, with Too net circuit and bus buffer composition, cpu chip is connected with clock circuit, the reset circuit signal of telecommunication, and cpu chip is by controlling Bus, internal address bus, internal data bus are connected with main memory circuit, program storing circuit and the bus buffer signal of telecommunication, Cpu chip is connected with the ethernet circuit signal of telecommunication, it is provided that an internal 100M Ethernet interface is connected with described relay module, Ethernet circuit is made up of Ethernet chip and Ethernet transformator.

The internal address bus of CPU module, the signal of internal data bus give after being driven by bus buffer address, Data/address bus, CPU module by address, data, control bus connect serial ports expansion module 3, CPU module by control bus and Data/address bus connecting joint period arranges module 2,4 serial interface modules 4A, 4B, 4C, 4D, the control bus of CPU module and ground Location bus is connected into CPLD module 5, by obtaining new control signal after CPLD resume module, then connects together with data/address bus CAN interface module 6.

Cpu chip selects MPC866, and reset circuit chip selects MAX706, and main memory circuit chip selects 2 HY57V561620, Ethernet chip selects RTL8201, program storing circuit chip selection SST39VF040, clock circuit chip Using 10MHZ crystal oscillator, bus buffer circuit chip selects 2 74FCT163245, respectively as internal address bus and inside The buffer of data/address bus.By the I/O port PA10(pin J17 of cpu chip) it is defined as Ethernet switch-over control signal, CPU core Sheet makes this I/O port pin become output port by arranging internal register value, it is provided that switch-over control signal.

As shown in Figure 4, node number arranges module and is made up of 4 road dial switch 9-1 and buffer chip 9-2, buffer core Sheet uses 74FCT3245, and each way switch one end ground connection in 4 road dial switch 9-1, the other end connects after concatenating pull-up resistor respectively Connecing buffer chip 9-2 data input pin, in 4 road dial switches, each road is separately provided on off operating mode；Buffer chip 9-2 4 circuit-switched data outfans connect CPU module 1 by data/address bus respectively, and the 5th the chip selection signal CSn5 that CPU module 1 provides is with slow Rush device chip 9-2 Enable Pin to be connected；The state on the 4 each roads of road dial switch is manually set, is combined into 16 data, formed 16 node numbers, are read by CPU module 1；Node number is corresponding with the IP address of interface message processing means, setting by node number Putting, system can be accessed by multiple interface message processing means.

Serial ports expansion module is made up of the generic asynchronous serial communication chip ST16C554 of two panels independence, and every chip can prop up Holding the serial communication of 4 tunnel independences, every road unit of transmission and reception of chip both provides independent serioparallel exchange and parallel-serial conversion, To realize the synchronization of asynchronous serial data receiver, serial ports expansion module is connected with 4 serial interface module signals of telecommunication, by CPU mould The associative operation of block realizes reception and the transmission of RS232/RS422/485 serial data.

Serial interface module is divided into two types: RS232 interface module and RS422/485 interface module.As it is shown in figure 5, RS232 interface module is by RS232 electrical level transferring chip 10,8 road dial switch 11 and of a piece of independent two-way supported serial ports Buffer chip 12 forms, and wherein RS232 electrical level transferring chip 10 uses MAX3232, buffer chip 12 to use 74FCT3245.Each way switch one end ground connection in 8 road dial switches, the other end connects buffer after concatenating pull-up resistor respectively Chip data input, in 8 road dial switches, each road is separately provided on off operating mode；No. 8 outfans of buffer chip data Connecting CPU module by data/address bus respectively, CPU module is connected with buffer chip Enable Pin by controlling bus；Pass through hands The dynamic state arranging the 8 each roads of road dial switch, is combined into various data, CPU module reads, and is dialled by self-defined several roads The implication of switch data, allows CPU module obtain the speed set by the type of serial interface module and serial ports；As shown in Figure 6, By two panels, RS422/485 interface module can support that RS422/485 electrical level transferring chip 13A of a road serial ports, 13B, 8 tunnel dialing are opened Pass 14 and buffer chip 15 form, and wherein RS422/485 electrical level transferring chip uses MAX488, and buffer chip uses 74FCT3245, each way switch one end ground connection in 8 road dial switches, the other end connects buffer after concatenating pull-up resistor respectively Chip data input, in 8 road dial switches, each road is separately provided on off operating mode；No. 8 outfans of buffer chip data Connecting CPU module by data/address bus respectively, CPU module is connected with buffer chip Enable Pin by controlling bus；Pass through hands The dynamic state arranging the 8 each roads of road dial switch, is combined into various data, CPU module reads, and is dialled by self-defined several roads The implication of switch data, allows CPU module obtain the speed set by the type of serial interface module and serial ports；The present invention determines The implication of 8 dial switch data of justice is as follows:

Two types serial interface module can exchange use completely, selects corresponding according to the serial line interface type of external equipment Serial interface module, according to the serial line interface speed of external equipment, the respective counts of dial switch in serial interface module is set According to；By reading the data of dial switch, CPU module can obtain the type of each serial interface module in interface message processing means And the speed set by each serial ports.According to the speed set by each serial ports, CPU module is by generic asynchronous serial communication chip The numerical value of DLL with the DLM depositor of ST16C554 carries out being correspondingly arranged thus realizes the correct of the various speed of serial ports and communicate.

CPLD module 5 is made up of CPLD chip EMP7256, and it is by the control bus of CPU module 1 and address bus Reason, obtains meeting the control signal of CAN interface module timing requirements, and these control signals are connected into CAN interface module, and data are total Line completes the read-write of CAN controller chip 16 together.

As it is shown in fig. 7, CAN interface module by a piece of CAN controller chip 16 supporting a road CAN interface and supports one The driving transceiver 17 of road CAN interface forms, and wherein CAN controller chip 16 uses SJA1000, the driving transmitting-receiving of CAN interface Device 17 uses PCA82C250, and the multiplexing address of CAN controller chip 16/data/address bus AD0 to AD7 is respectively with CPU module Least-significant byte data/address bus B_H_D0 to B_H_D7 correspondence is connected；Through CPLD module 5 process after obtain when meeting CAN interface module The control signal that sequence requires is connected with CAN controller chip 16, realizes CPU module 1 to CAN controller core together with data/address bus The read-write of sheet 16.

As specific embodiment, the pattern of CAN controller chip 16 is set to Motorola pattern, CPU by the present invention In module 1 cpu chip MPC866 provide the 6th chip selection signal CSn6, read-write RD/WRn and drive after address wire B_H_A20 is connected into CPLD.Through CPLD process after output meet CAN controller chip 16 timing requirements signal CAN_CSn, CAN_E, CAN_RD/WRn and CAN_AS are connected into the CSn(pin 4 of CAN controller chip respectively), RD/E (pin 5), WR(draw Foot 6) and ALE/AS(pin 3).Concrete logical relation is as follows:

CAN_CSn = CSn6 & B_H_A20;

CAN_E = !(CSn6 & B_H_A20);

CAN_RD/WRn = CSn6 & RD/WRn;

CAN_AS = !(CSn6 AND (!B_H_A20) AND RD/WRn );

Implementing principle is to realize a write operation of SJA1000 continuously with the write operation of twice MPC866, continuously A read operation of SJA1000 is realized with the write operation of a MPC866 and the read operation of a MPC866.Wherein for the first time The write operation of MPC866 realizes in register address to be operated write SJA1000, after once realize the read-write of data.

Once do one illustrate with as a example by reading the scratchpad register of a SJA1000 writing.Wherein, this scratchpad register Address in SJA1000 is that the 6th the chip selection signal CSn6 that 0x09, MPC866 provide is mapped as in the address of MPC866 The address that 0x09400000, CSn6 gate and address wire B_H_A20 is corresponding when being high is mapped as 0x09400800, and test code is such as Under:

void CAN_RdWrtest ( char data)

{

char i;

pSJA1000data = (char *)(0x09400000);

pSJA1000addr = (char *)(0x09400800);

* pSJA1000addr = 0x09;/ * Article 1 instructs, and write address */

* pSJA1000data = data;/ * Article 2 instruct, write data */

* pSJA1000addr = 0x09;/ * Article 3 instructs, and write address */

i = * pSJA1000data;/ * Article 4 instructs, and reading data */

}。

When performing Article 1 instruction, the least-significant byte B_H_D0 to B_H_D7 of data/address bus will appear from 0x09, i.e. SJA1000 AD0 to AD7 will appear from 0x09, occur on CAN_CSn, CAN_E, CAN_RD/WRn and CAN_AS meeting timing requirements simultaneously Signal, upper for AD0 to AD7 data 0x09 occurred are latched as its address by such SJA1000.

When performing Article 2 instruction, the least-significant byte B_H_D0 to B_H_D7 of data/address bus will appear from data data, i.e. The AD0 to AD7 of SJA1000 will appear from data data, occurs on CAN_CSn, CAN_E, CAN_RD/WRn and CAN_AS simultaneously Meeting the signal of timing requirements, upper for AD0 to the AD7 data occurred are latched as its data by such SJA1000, and write depositor In.

Same principle, perform Article 3 statement by address 0x09 write SJA1000 in, perform Article 4 statement by data from Address be 0x09 depositor in read.

As shown in Figure 8, relay module is by signal drive circuit 18, optocoupler drive circuit 19 and two DPDT relays Device 20A, 20B form, and the Ethernet switch-over control signal of CPU module output is connected to two inputs of signal drive circuit, Two outfans after being driven by signal drive circuit are respectively connecting to the input of optocoupler drive circuit, drive electricity through optocoupler Two outfans after the driving of road are connected to the coil of the first relay 20A and second two relays of relay 20B respectively and control Anode, the coil of said two relay controls negative terminal ground connection respectively.

In relay module, the Ethernet of the intermediate contact connection CPU module that the first relay first switchs 20A_1 receives Signal negative terminal, the normally-closed contact of first relay the first switch connects main push-towing rope and receives signal negative terminal, and the first relay first switchs Normally opened contact connect standby cable and receive signal negative terminal, the intermediate contact of the first relay second switch 20A_2 connects CPU module Ethernet receives signal anode, and the normally-closed contact of the first relay second switch connects main push-towing rope and receives signal anode, the first relay The normally opened contact of device second switch connects standby cable and receives signal anode, and the second relay first switchs the intermediate contact of 20B_1 even The Ethernet connecing CPU module sends signal negative terminal, and the normally-closed contact of second relay the first switch connects main push-towing rope transmission signal and bears End, the normally opened contact of second relay the first switch connects standby cable and sends signal negative terminal, the second relay second switch 20B_2's Intermediate contact connects the Ethernet of CPU module and sends signal anode, and the normally-closed contact of the second relay second switch connects main push-towing rope Sending signal anode, the normally opened contact of the second relay second switch connects standby cable and sends signal anode.

By relay module, described interface message processing means and two Ethernet switches by the most active and standby net Line connects respectively, when the Ethernet switch-over control signal of described CPU module output is low, and CPU mould in interface message processing means The Ethernet interface of block connects the Ethernet switch being connected with main push-towing rope, and CPU module is by reading Ethernet in ethernet circuit The Ethernet switch state that the buffer status detecting real-time of chip is connected with main push-towing rope, when main push-towing rope occurs disconnected cable or main push-towing rope to be connected During the Ethernet switch fault connect, the buffer status in Ethernet chip changes, and CPU module will after obtaining this information The Ethernet switch-over control signal of its output is set to height, controls the intermediate contact of all switches of relay module repeat circuit with often Closed contact disconnects, and makes intermediate contact and normally opened contact connect, the Ethernet interface of CPU module is connected be connected with standby cable with Too network switch.

The above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art For Yuan, under the premise without departing from the principles of the invention, it is also possible to make some improvement or deformation, these improve or deformation also should It is considered as protection scope of the present invention.

Claims (8)

1. an interface message processing means, it is characterised in that: include that CPU module, node number arrange module, serial ports expansion mould Block, P serial interface module, CPLD module, CAN interface module and relay module, wherein 1≤P≤16, P is natural number, The internal address bus of CPU module, the signal of internal data bus give address, data by bus buffer after being driven respectively Bus, CPU module couples serial ports expansion module by address, data, control bus, and CPU module is by controlling bus and data Bus joint period respectively arranges module and P serial interface module, and the control bus of CPU module and address bus are connected into After CPLD module, CPLD resume module the new control signal obtained, then connect CAN interface module, CPU together with data/address bus Module is by coupling two Ethernet interfaces after relay module, serial ports expansion module is with P the serial interface module signal of telecommunication even Connect；Described node number arranges module and includes Q road dial switch and buffer chip, wherein 1≤Q≤8, and Q is natural number, and each road is dialled Number switch one end ground connection, the other end couples the data input pin of buffer chip, Q road dial switch after concatenating pull-up resistor respectively In each road be separately provided on off operating mode, the data output end of buffer chip couples CPU module by data/address bus.

A kind of interface message processing means the most according to claim 1, it is characterised in that: described serial ports expansion module is all wrapped Including the generic asynchronous serial communication chip of R sheet independence, R is natural number, and every chip can support the serial communication of X road independence, its Middle X=1 or 2 or 4 or 8, every road unit of transmission and reception of chip all has independent serioparallel exchange and parallel-serial conversion.

A kind of interface message processing means the most according to claim 1, it is characterised in that: described serial interface module is RS232 interface module, this RS232 interface module include a piece of independent two-way supported serial ports RS232 electrical level transferring chip, Eight road dial switch and buffer chip, each way switch one end ground connection in eight road dial switches, the other end concatenates pull-up respectively Coupling buffer chip data input pin after resistance, in eight road dial switches, each road is separately provided on off operating mode, buffer core Eight circuit-switched data outfans of sheet couple CPU module by data/address bus respectively, and CPU module is by controlling bus and buffer chip Enable Pin couples.

A kind of interface message processing means the most according to claim 1, it is characterised in that: described serial interface module is RS422/485 interface module, this RS422/485 interface module includes that two panels can support that the RS422/485 level of a road serial ports turns Changing chip, eight road dial switch and buffer chip, each way switch one end ground connection in eight road dial switches, the other end is gone here and there respectively Connecting buffer chip data input pin after connecting pull-up resistor, in eight road dial switches, each road is separately provided on off operating mode, slow The eight circuit-switched data outfans rushing device chip couple CPU module by data/address bus respectively, and CPU module is by controlling bus and buffering Device chip Enable Pin couples.

A kind of interface message processing means the most according to claim 1, it is characterised in that: described relay module includes letter Number drive circuit, optocoupler drive circuit and two dpdt relays, the Ethernet switch-over control signal connection of CPU module output Connecing two inputs of signal drive circuit, two outfans after being driven by signal drive circuit are coupled optocoupler respectively and drive The input of circuit, two outfans after optocoupler drive circuit drives couple the coil of two relays respectively and are just controlling End, the coil of two relays controls negative terminal ground connection respectively.

A kind of interface message processing means the most according to claim 1, it is characterised in that: described CPU module includes CPU core Sheet, reset circuit, main memory circuit, program storing circuit, clock circuit, ethernet circuit and bus buffer, cpu chip is respectively Coupling with clock circuit, the reset circuit signal of telecommunication, cpu chip is by controlling bus, internal address bus and internal data bus Being connected with main memory circuit, program storing circuit and the bus buffer signal of telecommunication, cpu chip couples with the ethernet circuit signal of telecommunication After, it is provided that an internal 100M Ethernet interface is connected with described relay module；Described CAN interface module is by a piece of support one The driving transceiver composition of the CAN controller chip of road CAN interface and support one road CAN interface.

A kind of interface message processing means the most according to claim 6, it is characterised in that: described cpu chip is address, number According to bus multiplex chip, described CAN controller chip is address, multiplexed data bus chip.

A kind of interface message processing means the most according to claim 7, it is characterised in that: described address, data/address bus are non- Multiplexing chip and described address, multiplexed data bus chip with the use of method be, continuously with the write operation of twice cpu chip Realize a write operation of CAN controller chip, continuously with write operation and the reading behaviour of a cpu chip of a cpu chip Make to realize a read operation of CAN controller chip.