CN103546394B - Communication device - Google Patents
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- CN103546394B CN103546394B CN201310514176.4A CN201310514176A CN103546394B CN 103546394 B CN103546394 B CN 103546394B CN 201310514176 A CN201310514176 A CN 201310514176A CN 103546394 B CN103546394 B CN 103546394B
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Abstract
The invention provides a communication device which comprises a CPU, a first logic device, a second logic device, a PCIE, an Switch and a service interface card. The first logic device and the second logic device comprise cache units and analysis units respectively. After receiving a message sent by the CPU, the first logic device strips control information, stores the data information in a first cache area, and analyzes the BD corresponding to a structure of the control information. When the first cache area is full, the data information in the first cache area and the corresponding BD is sent to the second logic device. After the second logic device receives the data information, one or more data messages are restored according to the BD and are sent through the service interface card. After the data messages are sent, a confirmed BD message is replied to the first logic device. The communication device reduces the quantity of TLP messages and improves effective data bandwidth of a PCIE bus.
Description
Technical field
The present invention relates to communication technology, more particularly to a kind of communicator.
Background technology
Currently, in order to support the popularization and diversified application of network, the high speed of communication equipment, efficiently, extensibility
Increasingly paid close attention to by people.Due to bus with good compatibility, transmission speed is fast the features such as, user is met well various
The demand of change.Wherein PCI-Express (hereinafter referred to as PCIE) bussing technique can provide high bandwidth to meet system
Demand, so as to extensively be applied by people.But the effective bandwidth utilization rate of PCIE buses does not reach higher transmission speed than relatively low
Rate.
Common PCIE bus structures are as shown in figure 1, cpu chip is by being internally integrated a root controller Root
A Complex or external Root Complex, through a piece of or multi-disc exchange chip PCIE Switch, both can be with
Multiple PCIE Endpoint terminal units are connected, it is also possible to be connected with the equipment of multiple traditional PCI/PCI-X interfaces, be use
Family expands abundant business interface.The TLP that data interaction between CPU and PCIE terminal units passes through PCIE specification defineds
Message is carrying out.As shown in Fig. 2 the control information expense of a TLP message is 24 bytes.Such as, CPU sets to some PCIE
The standby data for writing 4 bytes, what is finally transmitted in PCIE buses will be the TLP messages of 28 bytes, wherein, it is real
Valid data are the Data parts shown in Fig. 2, only 4 byte.As can be seen here, when there is this frequency between CPU and PCIE device
During numerous scrappy data interaction, the bandwidth availability ratio of PCIE then can be reduced, because the expense of TLP control information account for very big portion
The bandwidth divided.
Generally, cpu chip is integrated with a PCIE controller as Root Complex for people, directly with a PCIE
The upstream port Up Stream of Switch is connected.PCIE Switch also go out multiple downstream port Down Stream, each Down
Stream can connect one piece of Service Interface Card with PCIE interfaces.Structured flowchart is as shown in Figure 3：CPU and specific business connect
The reception and transmission of message are realized between mouth card in the way of BD.The content of BD is as shown in figure 4, each BD8 byte.Herein,
Unification is referred to as descending to the message direction of transfer of Service Interface Card CPU, and business interface is snapped into the message direction of transfer of CPU
It is referred to as up.
The corresponding all BD of itself order caching were sent to Service Interface Card by CPU before uplink message is received, when connecing
When receiving uplink message：Service Interface Card receives a message, and to CPU a up TLP message is sent, and is with 64 byte messages
Example, TLP messages total length is 24+64=88 bytes；Service Interface Card correspond to one to the corresponding BD of one message of CPU write
Up TLP messages, TLP messages total length is 24+8=32 bytes；Afterwards, CPU responds one free time BD of Service Interface Card,
Correspond to a descending TLP message 24+8=32 byte.
When downlink message is sent：CPU to interface card writes a busy BD, and CPU sends a descending TLP report
Text, total length of data is 24+8=32 bytes；Interface card parses the message address and length information of this BD, initiates to CPU
Read request, correspond to a up TLP message, 24 bytes；CPU responds this read request returned packet data, correspond to one
Individual descending TLP messages, TLP messages total length is 24+64=88 bytes；Interface card has been sent after message to one transmission of CPU write
BD is completed, a up TLP message is correspond to, TLP messages total length is 24+8=32 bytes.
By taking the transmitting-receiving flow process of one time recited above 64 byte messages as an example, real valid data bandwidth is up with
Each 64 byte of row, consumes altogether the byte of downlink bandwidth 152, and the byte of upstream bandwidth 176, for the ease of calculating, upstream bandwidth is also omited
152 bytes are counted as, then valid data bandwidth only accounts for the 64/152=42% of total bandwidth.
As can be seen here, the PCIE links of even one 5G × 4Lane, its physics total bandwidth has 20G, through 10b/8b
Decoded actual physical bandwidth is 16G.But when small messages as transmitting 64 bytes, can only achieve 6.72G bps'
Speed.The surface speed forwarding of the interface of 8Gbps or 10Gbps rate levels cannot be supported.
The content of the invention
In view of this, the present invention provides a kind of communicator, including CPU, and described device further includes the first logic device
Part, the second logical device, PCIE Switch and Service Interface Card, wherein second logical device is on Service Interface Card, the
One logical device is connected by point-to-point bus with CPU, and the first logical device and the second logical device pass through PCIE Switch
It is connected, the first logical device and the second logical device all include buffer unit and resolution unit, wherein the first logical device
Buffer unit includes the first buffer zone and the second buffer zone；The buffer unit of the first logical device receives CPU transmissions
After downlink data message, control information is peeled off, data message is had into the first buffer zone, resolution unit parses control information,
Construct the second buffer zone that corresponding descending transmission buffer descriptor BD is stored in buffer unit；When first buffer zone is filled with,
Data message in first buffer zone is sent to into the buffer unit of the second logical device, and data message is corresponding descending
The buffer unit that BD is sent to the second logical device by BD messages is sent, wherein, the BD messages include more than one BD；The
The buffer unit of two logical devices is received after data message, is reduced data message according to the BD information of descending transmission BD messages
One or more data messages are sent by Service Interface Card；After being sent completely, reply one and confirm BD messages to the first logic device
Part, wherein, the confirmation BD messages include the confirmation BD for one above BD.
Description of the drawings
Fig. 1 is a kind of building-block of logic of communicator；
Fig. 2 is the structural representation of TLP messages；
Fig. 3 is the building-block of logic of another kind of communicator；
Fig. 4 is the content schematic diagram of BD；
Fig. 5 is a kind of building-block of logic of communicator of the embodiment of the present invention；
Fig. 6 is the building-block of logic of embodiment of the present invention another kind communicator；
Fig. 7 is the building-block of logic of another communicator of the embodiment of the present invention.
Specific embodiment
In order to solve this problem, a kind of communicator is embodiments provided.Fig. 5 is refer to, the present invention is implemented
Example provides a kind of communicator, including CPU11, the first logical device 12, PCIESwitch13, the second logical device 14 and business
Interface card 15.Wherein the first logical device 12 is connected by point-to-point bus with CPU11, and the second logical device 14 connects in business
On mouth card 15, the first logical device 12 and the second logical device 14 are respectively by the Up in PCIE buses and PCIE Switch13
Stream with Down Stream are connected, and the first logical device 12 includes resolution unit 121 and buffer unit 122, wherein described
Buffer unit includes the first buffer zone 1221 and the second buffer zone 1222.Second logical device includes the He of resolution unit 141
Buffer unit 142.
It is by point-to-point bus such as SPI4 between first logical device 12 and CPU11（System Packet
Interface Level4）Be connected, its feature be both sides without the need for addressing operation by by data-message transmission to opposite end.It is described
Data message is transmitted in the form of data flow, the control information of data message（As message length, SOP/EOP mark and
VALID is identified）It is included in the header SOP/ telegram ends EOP of data flow is indicated.
In the process of downlink message, when the buffer unit 122 of the first logical device 12 receives the descending of CPU11 transmissions
Data message, because the first logical device 12 is connected with the second logical device 14 by PCIE buses, the data of its transmission
Message is carried on TLP messages.Also need to BD messages during the data-message transmission to describe the control information of data message.If
Data message is sent to into the second logical device 14, then need the corresponding BD messages of data message.Therefore the first logic device
Part 12 peels off the control information of the data message in first indicating from the header SOP/ telegram ends EOP of data message（As message length,
SOP/EOP is identified and VALID marks）, then be there is into the first buffer zone 1221, the parsing of resolution unit 121 institute in data message
The control information stated, such as message length, SOP/EOP marks and VALID identification informations, according to the control information construction that parsing is obtained
Corresponding descending transmission BD is stored in the second buffer zone 1222 of buffer unit 122.
When the first buffer zone 1221 is filled with, the data message in the first buffer zone 1221 is sent to into the second logic
The buffer unit 142 of device 14, and the corresponding descending transmission BD of data message is sent to into the second logical device by BD messages
14 buffer unit 142.
It should be noted that：The BD messages are corresponding comprising all data messages in first buffer zone 1221
BD, because the first buffer zone 1221 can at least accommodate a data message, then also includes one in a corresponding BD message
BD above.Such as CPU issues three data messages and is cached in the first buffer zone 1221 to the first logical device 12, correspondence
The first logical device 12 can construct three descending transmission BD, and each BD is 8 bytes, and when now, the first buffer zone 1221 is filled with
When, sent by a BD message, then sending the BD of three data messages needs altogether 8 × 3+24=48 bytes.But it is existing
Have in technology and typically send three BD messages, then need（8+24）× 3=96 bytes.As can be seen here only in the transmission of BD messages
On, the present invention can just lift 50 percent effective bandwidth utilization rate.
The buffer unit 142 of the second logical device 14 is received after data message, is believed according to the BD of descending transmission BD messages
Breath（Including message length, SOP/EOP marks and VALID identification informations）Data message is reduced into into one or more numbers
According to message, described reduction is typically the message length and SOP/EOP mark first in BD information and is cut data message
Point, obtain each data message.Then sent by Service Interface Card 15.After being sent completely, the second logical device 14 is replied
One confirms BD messages to the first logical device, wherein, the confirmation BD messages include the confirmation for one above BD
BD。
As can be seen here, by the buffer unit 122 of the first logical device 12, the fully loaded of TLP messages in PCIE buses is realized
Transmission.The quantity of descending TLP messages is reduced, the valid data bandwidth of PCIE buses is improved.
In embodiments of the present invention, described logical device can be made up of multiple elements to realize logic function,
Can also be programmable logical device, illustrate by taking on-site programmable gate array FPGA as an example in the present embodiment, then first
Logical device is FPGA1, and the second logical device is FPGA2.FPGA1,2 usual built-in random access memory ram blocks or external RAM
Block come realize cache message.Because FPGA1 connects CPU, the message of transmitting-receiving is relatively more, needs larger buffer unit, therefore,
FPGA1 would generally the larger RAM of external some capacity as its buffer unit.But FPGA2 serves Service Interface Card, relatively
Portfolio is less, in order to cost-effective FPGA2 may an only built-in less RAM, certainly, FPGA2 can also be built-in one
Larger RAM.Therefore the size of the RAM capacity of FPGA2 is directed to, FPGA1 is also somewhat different to the mode that FPGA2 sends message, one
As be divided into master slave system and Peer.
For FPGA1,2 caching difference generally adopt master slave system, specifically, spatial cache is big than larger situation
Based on FPGA1, the little FPGA2 of spatial cache be from.Because FPGA2 does not possess sufficiently large spatial cache, it is impossible to which storage is a large amount of
Data message, so data can only be read from the caching of FPGA1.Its specific embodiment is：When first buffer zone of FPGA1
When being filled with, first BD messages corresponding with RAM1 are issued into FPGA2, FPGA2 sends reading according to BD information to the RAM1 of FPGA1 please
Ask, FPGA1 response read requests return the data message of corresponding RAM1.
For FPGA1, the smaller situation of 2 caching difference, Peer is generally adopted, specifically, as the RAM1 of FPGA1
When being filled with, the data message of RAM1 is write in FPGA2RAM by PCIE buses, and the corresponding BD messages of data message are sent out
Give FPGA2.Which is convenient compared to master slave system, the process due to eliminating read request, makes information transfer more
Plus it is quick.
Refer to Fig. 6, the embodiment of the present invention provides another kind of communicator, including CPU21, the first logical device 22,
PCIE Switch23, the second logical device 24 and Service Interface Card 25.Wherein the first logical device 22 is by point-to-point bus
It is connected with CPU21, the second logical device 24 on Service Interface Card 25, distinguish by the first logical device 22 and the second logical device 24
It is connected with the Up Stream and Down Stream on PCIE Switch23 by PCIE buses, the first logical device 22 is wrapped
Resolution unit 221 and buffer unit 222 are included, the second logical device includes resolution unit 241 and buffer unit 242.It is wherein described
Buffer unit 242 include the 4th buffer zone 2421 and the 5th buffer zone 2422.
In the process to upstream data, the buffer unit 242 of the second logical device 24 receives Service Interface Card 25
After the uplink data messages sent, control information is first peeled off, data message is put into into the 4th buffer zone 2421, resolution unit 241
After parsing control information, construct up transmission BD and be stored in the 5th buffer zone 2422, when the 4th buffer zone 2421 is filled with, by the
Data message and corresponding up transmission BD in four buffer zones 2421 is sent to the first logical device 22 by BD messages
Buffer unit 222, wherein, the BD messages include more than one BD.
The buffer unit 222 of the first logical device 22 is received after data message, according to up transmission BD information by data
Information reverting is sent to CPU21 into one or more data messages.
In the present embodiment, TLP reports in PCIE buses will be realized by the buffer unit 242 of the second logical device 24
The fully loaded transmission of text, reduces the quantity of up TLP messages, improves the valid data bandwidth of PCIE buses.
Refer to Fig. 7, the embodiment of the present invention provides another communicator, including CPU31, the first logical device 32,
PCIE Switch33, the second logical device 34 and Service Interface Card 35.Wherein the first logical device 32 is by point-to-point bus
It is connected with CPU31, the second logical device 34 on Service Interface Card 35, distinguish by the first logical device 32 and the second logical device 34
It is connected with the Up Stream and Down Stream on PCIE Switch33 by PCIE buses, the first logical device 32 is wrapped
Resolution unit 321 and buffer unit 322 are included, wherein the buffer unit includes the first buffer zone 3221 and the second buffer zone
3222.Second logical device includes resolution unit 341 and buffer unit 342.Wherein described buffer unit 342 is slow including the 4th
Deposit the buffer zone 3422 of region 3421 and the 5th.
First logical device 32 further comprises the 3rd buffer zone 3223, and mutual with the first buffer zone 3221
For standby, the data message for receiving is stored in the first buffer zone 3221 by first logical device 32, when the first buffer zone
3221 when being filled with, then by remaining data information memory to the 3rd buffer zone 3223, and further store follow-up message, when
Data message in first buffer zone 3221 send after as the 3rd buffer zone 3223 standby buffer zone, the two
Alternating backups each other.
Second logic device 34 further comprises the 6th buffer zone 3423, and mutual with the 4th buffer zone 3421
For standby, the data message for receiving is stored in the 4th buffer zone 3421 by second logic device 34, when the 4th buffer zone
3421 when being filled with, and by remaining data information memory to the 6th buffer zone 3423, and follow-up message is further stored, when
Data message in four buffer zones 3421 send after as the 6th buffer zone 3423 standby buffer zone, the two friendship
For backuping each other.
Assume in system initialization, the payload capacity Pay load size of a TLP in PCIE buses（TLP
size）For 256 bytes, MTU MTU is 1500 bytes, according to the formula for rounding up：
((MTU+TLP size-1)/TLP size) × TLP size, calculate the first caching of the first logical device 32
The size in region 3221 is 1536 bytes.
It is 512 bytes to assume that CPU31 sends first data flow, and the first logical device 32 is stored in first and delays data message
Region 3221 is deposited, is not filled with, and construct its corresponding descending transmission BD message and be stored in the second buffer zone 3222, in PCIE buses
Any operation is not initiated；
It is 512 bytes that CPU sends second data flow, and the first logical device 32 continues data message to be stored in the first caching
Region 3221, is not filled with（It is now 1024 bytes）, and construct its corresponding descending transmission BD and continue to be stored in the second buffer zone
Still do not operate in 3222, PCIE buses；
CPU sends the 3rd data flow for 1024 bytes, and the first logical device 32 continues data message to be stored in first and delays
Region 3221 is deposited, and constructs its corresponding descending transmission BD and be stored in the second buffer zone 3222.Now the first buffer zone 3221
It is filled with then the first logical device 32 to send out 512 bytes before the first two message and the 3rd message of the first buffer zone 3221
Go out；Then a TLP message is sent in PCIE buses again, comprising the corresponding descending transmission BD of the first two data message.In addition, the
There is the 3rd buffer zone 3223 remaining 512 byte of the 3rd data flow and construct its corresponding descending in one logical device
BD is sent to be stored in the second buffer zone 3222, if the first logical device 32 no longer receives new message, by the 3rd buffer area
The data message of 512 bytes in domain 3223 builds a corresponding BD message of TLP messages and sends together.Second patrols
Collect device 34 to receive after TLP messages, data message is stored in buffer unit 342 according to descending transmission BD cutting datas, often reduce
A complete data message, starts interface and is sent to Service Interface Card 35.
In order to ensure that data message is transmitted in time, can be respectively directed in buffer unit deposit the buffer area of data message
In domain, such as Fig. 7, the first buffer zone 3221, the 3rd buffer zone 3223, the 4th buffer zone 3421 and the 6th buffer zone
3423 this kind of data cache region arrange an intervalometer.Start when the data cache region starts to receive data
One intervalometer, when a length of N number of system clock cycle of intervalometer.If before timer expiry, the data of buffer zone are deposited
It is full, then the data of buffer zone and corresponding BD messages are sent, and delete intervalometer；If in timer expiry
When, buffer zone is not also filled with, then start PCIE buses yet and the middle data and corresponding BD of buffer zone are sent, and then deletes
Except intervalometer.
Wherein, the intervalometer when a length of buffer zone size and PCIE buses transmission rate ratio, and
For N times of the clock cycle, N is integer.The calculating of N meets following principle：
N/Sysclock Frequency>RAM size/Line Rate, that is to say, that when the transmission rate of data flow it is low
When general linear speed, the corresponding requirement to effective bandwidth utilization rate in PCIE buses is also reduced, and this when can adopt
Original mode is transmitted in PCIE buses, that is, allow the message that a TLP message is carried to be less than TLP size.Such setting
The device is allowd according to the practical situation of communication system to adjust data transfer mode, so as to realize it is various in the case of height
Effect transmission.
Scheme according to the embodiment of the present invention transmits the performance of 64 byte parcels in PCIE buses：
Sending direction, often sends 24 messages（26 × 64=1536, constitutes a RAM block, correspondence 1536/256=6
TLP size）, 6 TLP messages of descending generation；Then 24 descending transmission BD produce a TLP message；Downlink message length
1536 bytes, downlink data total length 6 ×（256+24）+（24 × 8+24）=1896 bytes, accordingly, confirm BD messages
Take upstream bandwidth 24 × 8+24=216 bytes；
Direction is received, similar, every 1536 byte of uplink message takes the byte of upstream bandwidth 1896；
Finally, the valid data bandwidth availability ratio of PCIE buses is when 64 byte parcels are transmitted：1536/（1896+216)=
72%.Compared to former scheme, for the PCIE buses of a 20G bandwidth, parcel transmission performance can be lifted to 11.6G from 6.72G.
As can be seen here, by the FPGA with RAM block, discontinuous stream compression on address is changed into and continuously count on address
According to stream, the fully loaded transmission of TLP messages in PCIE buses is realized.The quantity of TLP messages is reduced, the effective of PCIE buses is improved
Data bandwidth.
Presently preferred embodiments of the present invention is the foregoing is only, not to limit the present invention, all essences in the present invention
Within god and principle, any modification, equivalent substitution and improvements done etc. should be included within the scope of protection of the invention.
Claims (9)
1. a kind of communicator, including CPU, it is characterised in that：Described device further includes the first logical device, the second logic
Device, PCIE Switch and Service Interface Card, wherein second logical device is on Service Interface Card, the first logical device
It is connected with CPU by point-to-point bus, the first logical device and the second logical device are connected by PCIE Switch, the
One logical device and the second logical device all include buffer unit and resolution unit, wherein the buffer unit bag of the first logical device
Include the first buffer zone and the second buffer zone；
The buffer unit of the first logical device is received after the downlink data message of CPU transmissions, peels off control information, and data are believed
There is the first buffer zone in breath, resolution unit parses control information, and the corresponding descending transmission buffer descriptor BD of construction is stored in slow
Second buffer zone of memory cell；When first buffer zone is filled with, the data message in the first buffer zone is sent to into second
The buffer unit of logical device, and the corresponding descending transmission BD of data message is sent to into the second logical device by BD messages
Buffer unit, wherein, the BD messages include more than one BD；
The buffer unit of the second logical device is received after data message, is believed data according to the BD information of descending transmission BD messages
Breath is reduced to one or more data messages, is sent by Service Interface Card；After being sent completely, reply one and confirm BD messages to the
One logical device, wherein, the confirmation BD messages include the confirmation BD for one above BD.
2. communicator as claimed in claim 1, it is characterised in that when the first buffer zone is filled with, by the first buffer zone
In the data message and corresponding descending transmission BD messages buffer unit that is sent to the second logical device specifically include, it is described
First logical device write the buffer unit of the second logical device by the data message of the first buffer zone, and by data message pair
The descending transmission BD for answering is sent to the buffer unit of the second logical device by BD messages.
3. communicator as claimed in claim 1, it is characterised in that when the first buffer zone is filled with, by the first buffer zone
In the data message and corresponding descending transmission BD messages buffer unit that is sent to the second logical device specifically include, it is described
Descending transmission BD corresponding with the first buffer zone data message is issued the second logic device by the first logical device by BD messages
The buffer unit of part, the second logical device sends out read request, the first logical device response read request according to BD to the first logical device
The corresponding data information of the first buffer zone is sent to into the buffer unit of the second logical device.
4. communicator as claimed in claim 1, it is characterised in that the control information of the data message is included in header
During SOP/ telegram ends EOP is indicated.
5. communicator as claimed in claim 1, it is characterised in that the buffer unit of second logical device includes the 4th
Buffer zone and the 5th buffer zone, when second logical device receives the uplink data messages of Service Interface Card transmission
Afterwards, control information is peeled off, data message is put into into the 4th buffer zone, resolution unit parsing control information constructs up transmission
BD is stored in the 5th buffer zone, when the 4th buffer zone is filled with, by the data message in the 4th buffer zone and corresponding up
The buffer unit that BD is sent to the first logical device by BD messages is sent, wherein, the BD messages include more than one BD；
The buffer unit of the first logical device is received after data message, is reduced into data message according to descending transmission BD information
One or more data messages, are sent to CPU.
6. communicator as claimed in claim 1, it is characterised in that first logical device further comprises the 3rd and delays
Region is deposited, and it is standby each other with the first buffer zone, and the data message for receiving is stored in the first caching by first logical device
Region, when the first buffer zone has been filled with, by follow-up data information Store in the 3rd buffer zone, when the first buffer zone
In data message send after as the 3rd buffer zone standby buffer zone.
7. communicator as claimed in claim 5, it is characterised in that second logical device further comprises the 6th and delays
Region is deposited, and it is standby each other with the 4th buffer zone, and the data message for receiving is stored in the 4th caching by second logical device
Region, when the 4th buffer zone has been filled with, by follow-up data information Store in the 6th buffer zone, when the 4th buffer zone
In data message send after as the 6th buffer zone standby buffer zone.
8. the communicator as described in claim 1 to 7 is arbitrary, it is characterised in that when starting to be stored in number in data cache region
It is believed that during breath, starting intervalometer, when the buffer zone is filled with or timer expiry, by the data message and data of the buffer zone
The corresponding descending transmission BD of information sends and deletes intervalometer by BD messages.
9. communicator as claimed in claim 8, it is characterised in that the intervalometer when a length of data cache region it is big
The ratio of the little transmission rate with PCIE buses rounds up a clock cycle.
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Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104901904A (en) * | 2015-04-22 | 2015-09-09 | 上海昭赫信息技术有限公司 | Method and device for transmitting data from PCIE acceleration sub card to host |
| CN105022699B (en) * | 2015-07-14 | 2018-04-24 | 惠龙易通国际物流股份有限公司 | The preprocess method and system of buffer area data |
| CN106453018A (en) * | 2016-11-28 | 2017-02-22 | 天津光电通信技术有限公司 | Communication platform based on PCIe Switch and communication method |
| CN107525955A (en) * | 2017-07-07 | 2017-12-29 | 珠海格力电器股份有限公司 | A kind of ammeter data processing method and processing device |
| CN108170373B (en) * | 2017-12-19 | 2021-01-05 | 云知声智能科技股份有限公司 | Data caching method and device and data transmission system |
| CN109361607B (en) * | 2018-10-15 | 2021-09-17 | 迈普通信技术股份有限公司 | Method and device for acquiring table item data and communication equipment |
| CN113973039A (en) * | 2020-07-24 | 2022-01-25 | 深圳市中兴微电子技术有限公司 | Data processing method, device, equipment and storage medium |
| CN112887319B (en) * | 2021-02-01 | 2022-07-01 | 上海帆一尚行科技有限公司 | Network state monitoring method and device based on downlink traffic and electronic equipment |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6647443B1 (en) * | 2000-12-28 | 2003-11-11 | Intel Corporation | Multi-queue quality of service communication device |
| CN101202707A (en) * | 2007-12-03 | 2008-06-18 | 杭州华三通信技术有限公司 | Method for transmitting message of high speed single board, field programmable gate array and high speed single board |
| CN103064807A (en) * | 2012-12-17 | 2013-04-24 | 福建星网锐捷网络有限公司 | Multi-channel direct memory access controller |
| CN103218313A (en) * | 2013-04-02 | 2013-07-24 | 杭州华三通信技术有限公司 | Method and electric device for interacting cache descriptors |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030065735A1 (en) * | 2001-10-02 | 2003-04-03 | Connor Patrick L. | Method and apparatus for transferring packets via a network |
-
2013
- 2013-10-25 CN CN201310514176.4A patent/CN103546394B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6647443B1 (en) * | 2000-12-28 | 2003-11-11 | Intel Corporation | Multi-queue quality of service communication device |
| CN101202707A (en) * | 2007-12-03 | 2008-06-18 | 杭州华三通信技术有限公司 | Method for transmitting message of high speed single board, field programmable gate array and high speed single board |
| CN103064807A (en) * | 2012-12-17 | 2013-04-24 | 福建星网锐捷网络有限公司 | Multi-channel direct memory access controller |
| CN103218313A (en) * | 2013-04-02 | 2013-07-24 | 杭州华三通信技术有限公司 | Method and electric device for interacting cache descriptors |
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| CN103546394A (en) | 2014-01-29 |
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