CN103545589A - Positive and negative photoresist technology combined microstrip line manufacturing method - Google Patents

Positive and negative photoresist technology combined microstrip line manufacturing method Download PDF

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Publication number
CN103545589A
CN103545589A CN201310485962.6A CN201310485962A CN103545589A CN 103545589 A CN103545589 A CN 103545589A CN 201310485962 A CN201310485962 A CN 201310485962A CN 103545589 A CN103545589 A CN 103545589A
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microstrip line
positive
glue
photoresist
layer
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李建华
徐立新
陈和峰
卢冲赢
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Beijing Institute of Technology BIT
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Beijing Institute of Technology BIT
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Abstract

The invention discloses a positive and negative photoresist technology combined microstrip line manufacturing method. The positive and negative photoresist technology combined microstrip line manufacturing method includes: 1), spinning a layer of positive photoresist on glass sheets or silicon slices as a device releasing sacrificial layer; 2), deposing a layer of Cu metal on the positive photoresist via the magnetron sputtering technology as an electroplating seed layer; 3), coating the positive photoresist on the Cu seed layer and photoetching; 4), using electroplate Ni as a microstrip line ground layer; 5), sputtering the Cu metal layer; 6), coating SU-8 photoresist on the Cu layer and photoetching; 7), sputtering a Cr/Cu electroplating seed layer; 8), coating photoresist on the SU-8 dielectric layer, and photoetching; 9), electroplating microstrip line; 10), dissolving the positive photoresist with solvent, so that microstrip line devices with the SU-8 photoresist as the dielectric layer are released from glass or silicon slices.

Description

A kind of microstrip line manufacture method of positive and negative adhesive process combination
Technical field
The present invention relates to RF MEMS manufacturing technology, especially relate to a kind of manufacture method of microstrip line.
Background technology
Along with the development of technology, radiotechnics is towards shorter and shorter millimeter wave, submillimeter wave future development.Millimeter wave between microwave and light, have bandwidth, resolution high, can all weather operations, the advantage such as easy of integrationization, therefore in the fields such as military, communication, safety, have a wide range of applications.But in millimere-wave band, along with the raising of frequency, more and more higher to the requirement of machining accuracy, traditional machining can not meet the demands, must be by means of new process technology, and MEMS Micrometer-Nanometer Processing Technology just can meet the requirement of machining accuracy.It has that precision is high, controllability good, can manufacture in batches, with the IC technique advantage such as compatible mutually.
Summary of the invention
In order to overcome above-mentioned the deficiencies in the prior art, the present invention proposes a kind of microstrip line manufacture method of positive and negative adhesive process combination.
The present invention adopts following technical scheme:
A microstrip line manufacture method for adhesive process combination, comprises the following steps:
The first step applies positive photoresist on glass or silicon substrate, the sacrifice layer discharging as device;
Second step, magnetron sputtering C r/Cu Seed Layer on above-mentioned positive photoresist;
The 3rd step, positive glue photoetching, plating microstrip line metal ground plane;
The 4th step, sputter Cu metal level;
The 5th step, applies the negative glue of SU-8, and makes figure by lithography;
The 6th step, finally photoetching on SU-8 dielectric layer, plating microstrip line.
The 7th step, successively removes positive photoresist and plating seed layer with weakly alkaline solution and corrosion of metals solution, thereby microstrip line device is released from substrate.
In the technical program, the sacrifice layer that first positive glue discharges as device is used, and this is because positive adhesive process compatibility is good, is easy to be dissolved in organic solvent and alkaline solution, is therefore a kind of good sacrificial layer material.Secondly; the developer solution of SU-8 negative photoresist is alkaline solution; and positive photoresist can be dissolved in alkaline solution; therefore for to avoid SU-8 in the dissolving of the positive glue of developing process Zhong Dui lower floor; need to be before SU-8 gluing sputter one deck Cu metal level, thereby protect positive glue not dissolved in SU-8 developing process.
In the process discharging at device, because positive glue can dissolve fast in acetone, directly substrate is put into when acetone can cause positive peptization solution metal seed layer is torn, thereby stick in the problem on device, therefore at dispose procedure, will successively remove positive glue with weakly alkaline solution exposes metal seed layer, then with specific corrosive liquid, remove metal seed layer, repeat this process until by undermost positive peptization solution, thereby device is released.
The present invention obtains following effect:
1. utilize SU-8 negative photoresist dielectric constant high, the feature of stable mechanical performance, the dielectric layer using SU-8 negative photoresist glue as microstrip line is used.
2. positive photoresist and SU-8 negative photoresist are used in technique simultaneously, have solved the problem of two kinds of incompatible uses of photoresist.
3. for to prevent that SU-8 glue developing solution from aligning the dissolving of glue, sputter layer of metal layer on positive glue, Cu for example, thus solved the dissolution problems that SU-8 glue developing solution aligns glue.
4. utilize positive glue can be dissolved in the feature of weakly alkaline solution, with weakly alkaline solution, first remove the positive glue of the superiors, then by particular solution, remove metal level, repeat this process until device finally releases.
Accompanying drawing explanation
Figure be take the microstrip line manufacturing process flow diagram that SU-8 glue is dielectric layer.
Embodiment:
Embodiment 1
A microstrip line manufacture method for adhesive process combination, comprises the following steps:
(1) glass of certain size or silicon chip (such as 4 cun) are used to H 2sO 4+ H 2o 2, deionized water cleans successively, dries, and then on substrate, evaporates HMDS(coupling agent).
(2) by the way of spin coating, AZ4620 positive photoresist is coated on the substrate of handling well to thickness 5 μ m.
(3) on hot plate, photoresist is carried out to front baking, condition is 65 ℃/30min, 95 ℃/60min, 120 ℃/60min, cooling with stove.
(4) by many targets of magnetic control sputter deposition Cr/Cu Seed Layer,
Figure DEST_PATH_GDA0000413234480000021
(5) in Cr/Cu Seed Layer, apply the positive glue of AZ4620,10 μ m.
(6) on hot plate, photoresist is carried out to front baking, condition is 65 ℃/30min, 95 ℃/60min, cooling with stove.
(7) SUSS MA6 ultraviolet photolithographic machine exposure, develops.
(8) electroplated Ni metal.
(9) electroplated after on hot plate post bake, condition is 120 ℃/60min, cooling with stove.
(10) with many targets of magnetic control sputter deposition Cu metal level,
Figure DEST_PATH_GDA0000413234480000022
(11) apply SU-82010 photoresist 30um.
(12) front baking, 65 ℃/3min, 95 ℃/5min.
(13) SUSS MA6 ultraviolet photolithographic machine exposure, develops.
(14) after, dry, 65 ℃/3min, 95 ℃/5min.
(15) by many targets of magnetic control sputter deposition Cr/Cu Seed Layer,
Figure DEST_PATH_GDA0000413234480000023
(16) apply the positive glue 10 μ m of ARP.
(17) 65 ℃/30min of front baking, 95 ℃/30min.
(18) SUSS MA6 ultraviolet photolithographic machine exposure, develops.
(19) electroplated Ni/Au microstrip line layer.
(20) use 1%(Wt under room temperature) the positive glue of the NaOH solution removal the superiors, until expose Seed Layer.
(21) with ammoniacal liquor and ammonium ceric nitrate, remove respectively Cu and Cr.
(22) repeat the said process of (20) (21) until undermost positive glue is removed, device releases from substrate.
Embodiment 2
(1) glass of certain size or silicon chip (such as 4 cun) are cleaned successively with H2SO4+H2O2, deionized water, dry, then on substrate, evaporate HMDS(coupling agent).
(2) by the way of spin coating, ARP positive photoresist is coated on the substrate of handling well to thickness 10 μ m.
(3) with program-control baking oven, photoresist is carried out to front baking, condition is 65 ℃/40min, 95 ℃/90min, 120 ℃/90min, cooling with stove.
(4) with many targets of magnetic control sputter deposition Cu Seed Layer, thickness
Figure DEST_PATH_GDA0000413234480000031
(5) in Cu Seed Layer, apply the positive glue of AZ4620,10 μ m.
(6) with program-control baking oven, photoresist is carried out to front baking, condition is 65 ℃/400min, 95 ℃/90min, cooling with stove.
(7) SUSS MA6 ultraviolet photolithographic machine exposure, develops.
(8) electroplated Ni metal.
(9) electroplated rear post bake, condition is 120 ℃/60min, cooling with stove.
(10) with many targets of magnetic control sputter deposition Cu metal level, thickness
Figure DEST_PATH_GDA0000413234480000032
(11) apply SU-82010 photoresist 30um.
(12) front baking, 65 ℃/3min, 95 ℃/5min.
(13) SUSS MA6 ultraviolet photolithographic machine exposure, develops.
(14) after, dry, 65 ℃/3min, 95 ℃/5min.
(15) by many targets of magnetic control sputter deposition Cr/Cu Seed Layer,
(16) apply the positive glue 10 μ m of ARP.
(17) 65 ℃/30min of front baking, 95 ℃/30min.
(18) SUSS MA6 ultraviolet photolithographic machine exposure, develops.
(19) electroplated Ni/Au microstrip line layer.
(20) use 1%(Wt under room temperature) the positive glue of the NaOH solution removal the superiors, until expose Seed Layer.
(21) with ammoniacal liquor and ammonium ceric nitrate, remove respectively Cu and Cr.
(22) repeat the said process of (20) (21) until undermost positive glue is removed, device releases from substrate.

Claims (5)

1. a microstrip line manufacture method for positive and negative adhesive process combination, is characterized in that comprising the following steps:
The first step applies the sacrifice layer that positive glue discharges as device on glass or silicon chip;
Second step, sputter plating seed layer gluing, photoetching on positive glue, electroplated Ni is as ground plane;
The 3rd step, sputter one deck Cu metal level on substrate obtained above;
The 4th step, applies SU-8 photoresist and makes figure by lithography;
The 5th step, sputter Cr/Cu Seed Layer on figure obtained above;
The 6th step, gluing, makes microstrip line figure by lithography;
The 7th step, electroplated Ni/Au microstrip line;
The 8th step, dissolves positive glue, the microstrip line that to obtain take SU-8 photoresist be dielectric layer.
2. the microstrip line manufacture method that a kind of SU-8 glue according to claim 1 is dielectric layer, it is characterized in that with high-k, and the SU-8 negative photoresist of mechanical performance excellence is as the dielectric layer of microstrip line.
3. the microstrip line manufacture method that a kind of SU-8 glue according to claim 1 is dielectric layer, is characterized in that the sacrifice layer discharging as microstrip line device with positive photoresist.
4. the microstrip line manufacture method that a kind of SU-8 glue according to claim 1 is dielectric layer; it is characterized in that before applying SU-8 glue; first want sputter one deck Cu metal level; this is alkaline because of SU-8 glue developing solution; for avoiding can dissolving the positive glue of lower floor in SU-8 glue developing process, therefore not dissolved with one deck Cu metal level protection positive glue below.
5. the microstrip line manufacture method that a kind of SU-8 glue according to claim 1 is dielectric layer, its feature will successively be dissolved at the dispose procedure of device.
CN201310485962.6A 2013-10-16 2013-10-16 Positive and negative photoresist technology combined microstrip line manufacturing method Pending CN103545589A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104953218A (en) * 2015-05-11 2015-09-30 中国科学院半导体研究所 Lateral-metallized coplanar waveguide transmission line
CN109879241A (en) * 2019-02-25 2019-06-14 湖南大学 A method of preparing the releasable micro-nano structure of large area
CN111106215A (en) * 2018-10-29 2020-05-05 山东浪潮华光光电子股份有限公司 Preparation method of LED chip electrode
CN112062085A (en) * 2020-09-10 2020-12-11 浙江集迈科微电子有限公司 Manufacturing process of silicon-based photoresist medium transverse transmission line structure

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102621804A (en) * 2009-08-21 2012-08-01 技鼎股份有限公司 Method for forming metal microstructure

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102621804A (en) * 2009-08-21 2012-08-01 技鼎股份有限公司 Method for forming metal microstructure

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
钱嵩松等: "基于MEMS 加工工艺的亚毫米波肖特基单端混频器", 《制导与引信》, vol. 32, no. 3, 30 September 2011 (2011-09-30) *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104953218A (en) * 2015-05-11 2015-09-30 中国科学院半导体研究所 Lateral-metallized coplanar waveguide transmission line
CN111106215A (en) * 2018-10-29 2020-05-05 山东浪潮华光光电子股份有限公司 Preparation method of LED chip electrode
CN111106215B (en) * 2018-10-29 2021-02-05 山东浪潮华光光电子股份有限公司 Preparation method of LED chip electrode
CN109879241A (en) * 2019-02-25 2019-06-14 湖南大学 A method of preparing the releasable micro-nano structure of large area
CN112062085A (en) * 2020-09-10 2020-12-11 浙江集迈科微电子有限公司 Manufacturing process of silicon-based photoresist medium transverse transmission line structure
CN112062085B (en) * 2020-09-10 2024-02-23 浙江集迈科微电子有限公司 Manufacturing process of silicon-based photoresist medium transverse transmission line structure

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Application publication date: 20140129