CN103545336B - Semiconductor device and its manufacture method - Google Patents
Semiconductor device and its manufacture method Download PDFInfo
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- CN103545336B CN103545336B CN201210238572.4A CN201210238572A CN103545336B CN 103545336 B CN103545336 B CN 103545336B CN 201210238572 A CN201210238572 A CN 201210238572A CN 103545336 B CN103545336 B CN 103545336B
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Abstract
Provide a kind of semiconductor device and its manufacture method.A kind of semiconductor device, including: one first doped layer；One second doped layer, it is the most identical with described first doped layer；One transparent insulating layer, this transparent insulating layer is between described first doped layer and described second doped layer；One the 3rd doped layer, the 3rd doped layer is positioned at the opposite side of described second doped layer of this transparent insulating layer relatively, and it is the most contrary with described second doped layer；And a conducting structure, this conducting structure runs through described second doped layer, described 3rd doped layer and described transparent insulating layer, with the first doped layer described in electrical couplings and described 3rd doped layer.
Description
Technical field
The present invention relates to a kind of semiconductor device, particularly to a kind of semiconductor device with stack architecture and its manufacture method.
Background technology
In this area, in order to change component characteristic, the semiconductor device with stack architecture sometimes can be formed.
Such as, two light emitting diodes sending different colours light respectively of storehouse, available a kind of colour mixture is luminous.U.S. Patent Bulletin number 7064354 discloses a kind of color mixture LED, utilizes transparent adhesion layer to engage two light-emitting diode chip for backlight unit, and one of them light-emitting diode chip for backlight unit sends sodium yellow, and another light-emitting diode chip for backlight unit sends blue light.
Other known technology also discloses that correlation technique.Such as, U.S. Patent Bulletin number 7732803 discloses multiple light emitting diodes of storehouse, the most each light emitting diode has p type semiconductor layer, n type semiconductor layer and active layer, and each light emitting diode can independently control, and has ohmic contact layer between light emitting diode.
Summary of the invention
The present invention relates to a kind of semiconductor device with stack architecture and its manufacture method.
One embodiment of the invention provides a kind of semiconductor device, includes the first doped layer, transparent insulating layer, the second doped layer, the 3rd doped layer the most successively.Second doped layer and the first doped layer have identical electrically, the second doped layer and the 3rd doped layer have opposite-sign.Conducting structure runs through the second doped layer, the 3rd doped layer, and transparent insulating layer, with electrical couplings the first doped layer and the 3rd doped layer.
Another embodiment of the present invention provides the manufacture method of a kind of semiconductor device, including: a first substrate is provided, forming one first semiconductor unit on it, wherein the first semiconductor unit is sequentially formed one the 4th doped layer, one first active layer and one first doped layer by first substrate；First doped layer is formed one first transparent insulating layer；Thering is provided a second substrate, form one second semiconductor unit on this second substrate, wherein the second semiconductor unit is sequentially formed one the 3rd doped layer, one second active layer and one second doped layer by second substrate；Second doped layer is formed one second transparent insulating layer；Couple the first transparent insulating layer and the second transparent insulating layer；Remove second substrate, to expose the 3rd doped layer；Forming a conducting structure, it runs through the second semiconductor unit, the first transparent insulating layer and the second transparent insulating layer, with electrical couplings the first semiconductor unit and the second semiconductor unit.
Accompanying drawing explanation
Figure 1A to 1B is to illustrate the schematic perspective view of semiconductor device according to a first embodiment of the present invention and it is along the generalized section of A-A ' dotted line respectively.
Fig. 1 C is the generalized section illustrating semiconductor device according to a second embodiment of the present invention.
Fig. 2 A to Fig. 2 I illustrates a kind of manufacture method according to another embodiment of the present invention semiconductor device.
Fig. 3 illustrates semiconductor device array according to a third embodiment of the present invention.
Fig. 4 illustrates semiconductor device array according to a fourth embodiment of the present invention.
Fig. 5 illustrates semiconductor device array according to a fifth embodiment of the present invention.
Fig. 6 illustrates semiconductor device array according to a sixth embodiment of the present invention.
Drawing reference numeral explanation
1/1A/1B: semiconductor device
2: semiconductor device
10: substrate
12: the first semiconductor units
12a: the four doped layer
12b: the first active layer
12c: the first doped layer
12d: the first transparency conducting layer
14: the second semiconductor units
14a: the three doped layer
14b: the second active layer
14c: the second doped layer
14d: the second transparency conducting layer
16: transparent insulating layer
16a: the first transparent insulating layer
16b: the second transparent insulating layer
18: conducting structure
18a: hole
18b: insulating barrier
18c: conductive layer
22: the first electrodes
24: the second electrodes
26: interior online/attachment structure
30: substrate
142: exposed surface
144: exposed surface
146: exposed surface
Detailed description of the invention
Figure 1A Yu Figure 1B illustrates semiconductor device according to an embodiment of the invention, and wherein Figure 1A is schematic perspective view, and Figure 1B is the generalized section in Figure 1A along A-A ' dotted line.
Seeing Figure 1A and Figure 1B, semiconductor device 1 includes the first semiconductor unit 12 and the second semiconductor unit 14, and each semiconductor unit 12/14 respectively includes at least one doped layer.First semiconductor unit 12 can be located at below the second semiconductor unit 14, and arranges on the substrate 10.Additionally, transparent insulating layer 16 is between the first semiconductor unit 12 and the second semiconductor unit 14, in order to engage two semiconductor units 12/14；Conducting structure 18 runs through the second semiconductor unit 14 and transparent insulating layer 16, in order to electrical couplings the first semiconductor unit 12 and the second semiconductor unit 14.Preferably, one doped layer of conducting structure 18 electrical couplings the first semiconductor unit 12 and a doped layer of the second semiconductor unit 14, the doped layer of above-mentioned first semiconductor unit 12 and the doping series of strata of the second semiconductor unit 14 are electrically contrary, and its details is described more fully below.
Semiconductor device the 1, first semiconductor unit 12 and/or the second semiconductor unit 14 can be photovoltaic cell, light emitting diode, transistor, optical sensor, or diode etc..
In the present embodiment, it is preferred that the first semiconductor unit 12 from bottom to top can include the 4th doped layer 12a, the first active layer 12b, the first doped layer 12c and the first transparency conducting layer 12d.Second semiconductor unit 14 can include the 3rd doped layer 14a, the second active layer 14b, the second doped layer 14c and the second transparency conducting layer 14d.Wherein, the first doped layer 12c's and the second doped layer 14c is the most identical, and the second doped layer 14c's and the 3rd doped layer 14a is the most contrary, and the first doped layer 12c's and the 4th doped layer 12a is the most contrary." electrically " refer to the kenel of doping herein, that is, p-type or N-type.
In one embodiment, semiconductor device 1 is a photovoltaic cell, and the energy gap (energygap) that the energy gap of the first active layer 12b is less than the second active layer 14b.
In the present embodiment, the first semiconductor unit 12 and second semiconductor unit 14 of semiconductor device 1 is light emitting diode.
In the present embodiment, the first doped layer 12c and the second doped layer 14c is p-type doped layer, and the 3rd doped layer 14a and the 4th doped layer 12a is n-type doping layer.
In the present embodiment, substrate 10 includes (polar) substrate that polarizes, semipolar (semi-polar) substrate or non-polarized (non-polar) substrate, and its material can be GaAs (GaAs), the SiGe (SiGe) that germanium (Ge) surface is formed, the carborundum (SiC) that silicon (Si) surface is formed, the aluminium oxide (Al2O3) that aluminum (Al) surface is formed, gallium nitride (GaN), indium nitride (InN), zinc oxide (ZnO), aluminium nitride (AlN), sapphire (sapphire), glass, quartz or a combination thereof, but it is not limited to this.4th doped layer 12a, the first active layer 12b, the first doped layer 12c, the 3rd doped layer 14a, the second active layer 14b, and second the material of doped layer 14c comprise III-nitride, such as indium nitride (InN), gallium nitride (GaN), aluminium nitride (AlN), InGaN (InGaN), indium nitride gallium aluminium (InAlGaN) etc., but it is not limited to above-mentioned material.
In the present embodiment, conducting structure 18 at least includes hole 18a, insulating barrier 18b, conductive layer 18c.Hole 18a runs through the second doped layer 14c, the 3rd doped layer 14a, and transparent insulating layer 16.Insulating barrier 18b is formed at the side-walls of hole 18a.Conductive layer 18c fills up hole 18a, and electrical couplings the first doped layer 12c and the 3rd doped layer 14a.It is distributed in the quantity of semiconductor device 1 by increasing conducting structure 18, the carrier transportation distribution of the first semiconductor unit 12 and the second semiconductor unit 14 can be improved, to strengthen the efficiency of semiconductor device 1.
In the present embodiment, the 3rd doped layer 14a, at the exposed surface 142 relative to the second doped layer 14c, can have coarse structure.If semiconductor device 1 is photovoltaic cell, then coarse structure can be effectively improved absorbing amount, to strengthen the photoelectric transformation efficiency of semiconductor device 1；If semiconductor device 1 is light emitting diode, then coarse structure can be effectively improved the amount of light of semiconductor device 1.
In the present embodiment, for convenience with other semiconductor device or external terminal electrical couplings, at the exposed surface 144 of the 4th doped layer 12a, can have the first electrode 22；At the exposed surface 146 of transparency conducting layer 14d, can have the second electrode 24.When providing voltage at the second electrode 24, electric current is by the second doped layer 14c and the 3rd doped layer 14a, then via conducting structure 18, flows to the first doped layer 12c.Wherein, first electrode 22 or the second electrode 24 are N-type electrode, then its material can be made up of titanium, aluminum, chromium, platinum, golden one of them or a combination thereof, such as chromium/platinum/gold (Cr/Pt/Au), titanium/aluminum/platinum/gold (Ti/Al/Pt/Au) or titanium/platinum/gold (Ti/Pt/Au)；First electrode 22 or the second electrode 24 are P-type electrode, then its material can be made up of nickel, platinum, silver, one of them or a combination thereof of tin indium oxide, such as nickel silver (Ni/Ag), nickel/platinum/silver (Ni/Pt/Ag) or Indium sesquioxide. tin silver (ITO/Ag).
The material of above-mentioned transparent insulating layer 16 can include transparent oxide, such as silicon dioxide (SiO2), silicon nitride (Si3N4), titanium dioxide (TiO2) or tantalum oxide (Tantalumpentoxide, Ta2O5).The material of above-mentioned first transparency conducting layer 12d and the second transparency conducting layer 14d can include one of them or a combination thereof of llowing group of materials: antimony tin oxide (AntimonyTinOxide, ATO), indium tin oxide (IndiumTinOxide, ITO), stannum oxide (TinOxide, SnO2), Zinc oxide doped aluminum (aluminumdopedzincoxide, AZO), Zinc oxide doped gallium (Galliumdopedzincoxide, and Zinc oxide doped indium (Indiumdopedzincoxide, IZO) GZO).
Fig. 1 C illustrates semiconductor device 2 according to a second embodiment of the present invention.The present embodiment is from the different places of Figure 1A embodiment, eliminates the first transparency conducting layer 12d and the second transparency conducting layer 14d, and the second electrode 24 is positioned at the exposed surface 146 of the second doped layer 14c.
Fig. 2 A to Fig. 2 I illustrates the manufacture method according to one embodiment of the invention semiconductor device.
As shown in Figure 2 A, forming the first semiconductor unit 12 on the substrate 10, it can include the 4th doped layer 12a, the first active layer 12b, the first doped layer 12c and the first transparency conducting layer 12d.The material of the first semiconductor unit 12 can comprise III-nitride.In the present embodiment, the 4th doped layer 12a is n-type doping layer, such as n type gallium nitride layer；First active layer 12b can be single or multiple quantum trap layer；First doped layer 12c is p-type doped layer, such as p-type gallium nitride layer.In another embodiment, the first transparency conducting layer 12d can be omitted.
Additionally, between substrate 10 and the 4th doped layer 12a, can have a cushion (not shown).In one embodiment, cushion can comprise one of them or its combination in any of llowing group of materials: undoped gallium nitride (GaN), N-shaped gallium nitride, aluminium nitride, aluminium gallium nitride alloy, magnesium nitride or silicon nitride.
The method forming the first transparency conducting layer 12d comprises the steps that dip coated (dipcoating), rotary coating (spincoating), spraying coating (spraycoating), chemical gaseous phase deposition (ChemicalVaporDeposition, CVD), evaporation (Evaporation) or sputter (Sputtering).
As shown in Figure 2 B, in the top of the first transparency conducting layer 12d (or first doped layer 12c), forming the first transparent insulating layer 16a, forming method can be identical with the method forming the first transparency conducting layer 12d.Additionally, an available Technology, such as, polish (polish), to polish the first transparent insulating layer 16a.
As shown in Figure 2 C, forming the second semiconductor unit 14 on substrate 30, it can include the 3rd doped layer 14a, the second active layer 14b, the second doped layer 14c and the second transparency conducting layer 14d.The material of the second semiconductor unit 14 can comprise III-nitride.In the present embodiment, the 3rd doped layer 14a is n-type doping layer, such as n type gallium nitride layer；Second active layer 14b can be single or multiple quantum trap layer；Second doped layer 14c is p-type doped layer, such as p-type gallium nitride layer.In another embodiment, the second transparency conducting layer 14d can be omitted.
Additionally, between substrate 30 and the 3rd doped layer 14a, can have a cushion (not shown).In one embodiment, cushion can comprise one of them or its combination in any of llowing group of materials: undoped gallium nitride (GaN), N-shaped gallium nitride, aluminium nitride, aluminium gallium nitride alloy, magnesium nitride or silicon nitride.The method forming the second transparency conducting layer 14d can be identical with the method forming the first transparency conducting layer 12d.
As shown in Figure 2 D, in the top of the second transparency conducting layer 14d (or second doped layer 14c), forming the second transparent insulating layer 16b, forming method can be identical with the method forming the second transparency conducting layer 14d.Additionally, an available Technology, such as, polish (polish), to polish the second transparent insulating layer 16b.
As shown in Figure 2 E, it is inverted the second semiconductor unit 14 and substrate 30, makes the second transparent insulating layer 16b be directed at the first transparent insulating layer 16a.Then, under a coupling condition, the second transparent insulating layer 16b and the first transparent insulating layer 16a is coupled into a transparent insulating layer 16.Above-mentioned coupling condition includes heating and/or pressurization.Such as, not destroy the temperature of first, second semiconductor unit 12/14, such as 700-800 DEG C heating, merged into each other through pressurized, heated by identical interface material, and make the second transparent insulating layer 16b and the first transparent insulating layer 16a coupling.Above-mentioned transparent first insulating barrier 16a and the material of the second transparent insulating layer 16b, the material merged into each other being included under coupling condition, such as silicon dioxide (SiO2).
Then, as shown in Figure 2 F, removable substrate 30, and optionally, the exposed surface 142 of the 3rd doped layer 14a can be roughened, form coarse structure on surface 142.Such as, available wet etching forms coarse structure.The method removing substrate 30, can be laser lift-off technology (laserlift-off) or wet etching, but be not limited to this.
Then, as shown in Figure 2 G, at least one hole 18a is etched by the 3rd doped layer 14a, hole 18a runs through the 3rd doped layer 14a, the second active layer 14b, the second doped layer 14c, the second transparency conducting layer 14d and transparent insulating layer 16, to expose the first transparency conducting layer 12d (without the first transparency conducting layer 12d, then expose the first doped layer 12c).Meanwhile, etch a part for the second semiconductor unit 14 and a part for the first semiconductor unit 12, to expose an exposed surface 144 of the 4th doped layer 12a, and an exposed surface 146 of the second transparency conducting layer 14d (or second doped layer 14c).The method of etching, can comprise, but is not limited to inductively coupled plasma reactive ion etching (InductivelyCoupledPlasmaReactiveIonEtching, ICP-RIE) or laser etching.
Then, as illustrated in figure 2h, the sidewall at hole 18a forms insulating barrier 18b, and formation conductive layer 18c is to fill up hole 18a, and contacts the 3rd doped layer 14a.By conductive layer 18c, the first doped layer 12c (through the first transparency conducting layer 12d) and the 3rd doped layer 14a electrical couplings.
Then, as shown in figure 2i, form the first electrode 22 at exposed surface 144, form the second electrode 24 at exposed surface 146.
Fig. 3 illustrates semiconductor device array according to a third embodiment of the present invention.Form multiple aforesaid semiconductor device on the substrate 10, such as, semiconductor device 1A and semiconductor device 1B, wherein, second electrode 24 of semiconductor device 1A, interconnection structure 26 (interconnect) or other attachment structure 26, first electrode 22 of electrical couplings semiconductor device 1B can be passed through, thus form a series connection array.
Fig. 4 illustrates semiconductor device array according to the fourth embodiment of the invention.On the substrate 10, forming multiple aforesaid semiconductor device, such as, semiconductor device 1A and semiconductor device 1B, wherein, two adjacent semiconductor devices (such as 1A/1B) share second electrode 24, form an array in parallel.
Fig. 5 illustrates semiconductor device array according to a fifth embodiment of the present invention.On the substrate 10, forming multiple aforesaid semiconductor device, such as, semiconductor device 1A and semiconductor device 1B, wherein, two adjacent semiconductor devices (such as 1A/1B) share first electrode 22, form an array in parallel.
Fig. 6 illustrates a kind of semiconductor device array according to a sixth embodiment of the present invention.This quasiconductor array is a series connection array, the first electrode 22 of semiconductor device 1, connects the second electrode 24 of adjacent semiconductor devices 1.Series connection array can be odd number array, that is, one of them of line number or columns is odd number.The area of interconnection structure 26 it is effectively reduced by the arrangement mode of above-mentioned quasiconductor array.
In the various embodiments described above, the p-type doped layer of semiconductor unit 12/14, active layer and n-type doping layer can be considered an epitaxial structure, its available tunnel junctions (tunneljunction) or other knot layer, connect or the more epitaxial structure of storehouse.That is, each semiconductor unit 12/14 can have multiple epitaxial structure.
According to the description of the present invention, those skilled in the art can do various modification, change or replace.Therefore, the description of the present invention is only for those skilled in the art, it is shown that how to realize the present invention, and described embodiment is only preferred embodiment.After those skilled in the art read the description of the present invention, it is to be understood which assembly in the embodiment of the present invention can be replaced with material, which assembly or sequence of process steps change, and which feature can be alone applied.All other changes without departing from the equivalence completed under the spirit disclosed in invention or modifies, and all should be included in scope of the presently claimed invention.
Claims (17)
1. a semiconductor device, including:
One first doped layer；
One second doped layer, it is the most identical with described first doped layer；
One transparent insulating layer, described transparent insulating layer is between described first doped layer and described second doped layer；
One the 3rd doped layer, described 3rd doped layer is positioned at the opposite side of described second doped layer of the most described transparent insulating layer, and it is the most contrary with described second doped layer；And
A plurality of conducting structures, described a plurality of conducting structures run through described second doped layer, described 3rd doped layer and described transparent insulating layer, with the first doped layer described in electrical couplings and described 3rd doped layer,
The most each conducting structure includes:
One hole, described hole runs through described second doped layer, described 3rd doped layer and described transparent insulating layer；
One insulating barrier, described insulating barrier is formed at the sidewall of described hole；
One conductive layer, described conductive layer fills up described hole, and the first doped layer described in electrical couplings and described 3rd doped layer.
2. semiconductor device as claimed in claim 1, also includes two transparency conducting layers, lays respectively between described transparent insulating layer and described first doped layer, and between described transparent insulating layer and described second doped layer.
3. semiconductor device as claimed in claim 1, also include a substrate, one the 4th doped layer, one first active layer and one second active layer, described 4th doped layer is between described substrate and described first doped layer, and it is the most contrary with described first doped layer；Described first active layer is between described first doped layer and described 4th doped layer thus forms one first semiconductor unit；Described second active layer is between described second doped layer and described 3rd doped layer thus forms one second semiconductor unit.
4. semiconductor device as claimed in claim 1, wherein said 3rd doped layer has a coarse structure relative to an exposed surface of described second doped layer.
5. semiconductor device as claimed in claim 3, also includes two electrodes, lays respectively at an exposed surface of described 4th doped layer, and be positioned at an exposed surface of described second doped layer.
6. semiconductor device as claimed in claim 1, the material of wherein said transparent insulating layer comprises one of them or a combination thereof of llowing group of materials: silicon dioxide, silicon nitride, titanium dioxide and tantalum oxide.
7. semiconductor device as claimed in claim 2, the material of wherein said two transparency conducting layers includes one of them or a combination thereof of llowing group of materials: antimony tin oxide, indium tin oxide, stannum oxide, Zinc oxide doped aluminum, Zinc oxide doped gallium and Zinc oxide doped indium.
8. a manufacture method for semiconductor device, including:
Thering is provided a first substrate, form one first semiconductor unit on described first substrate, wherein said first semiconductor unit is sequentially formed one the 4th doped layer, one first active layer and one first doped layer by described first substrate；
Described first doped layer is formed one first transparent insulating layer；
Thering is provided a second substrate, form one second semiconductor unit on described second substrate, wherein said second semiconductor unit is sequentially formed one the 3rd doped layer, one second active layer and one second doped layer by described second substrate；
Described second doped layer is formed one second transparent insulating layer；
Couple described first transparent insulating layer and described second transparent insulating layer；
Remove described second substrate, to expose described 3rd doped layer；
Forming a plurality of conducting structure, described a plurality of conducting structures run through described second semiconductor unit, described first transparent insulating layer and described second transparent insulating layer, with the first semiconductor unit described in electrical couplings and described second semiconductor unit,
The step wherein forming each conducting structure includes:
Being etched a hole by described 3rd doped layer, described hole runs through described second semiconductor unit, described first transparent insulating layer and described second transparent insulating layer, to expose a part for described first doped layer；
Sidewall at described hole forms an insulating barrier；And
Form a conductive layer to fill up described hole, and with described first doped layer and described 3rd doped layer electrical couplings.
9. manufacture method as claimed in claim 8, also include being formed between described second doped layer and described first transparent insulating layer respectively one first transparency conducting layer, and between described first doped layer and described second transparent insulating layer, form one second transparency conducting layer.
10. manufacture method as claimed in claim 9, the forming method of wherein said first transparency conducting layer, described second transparency conducting layer, described first transparent insulating layer and described second transparent insulating layer includes Dipcoat method, method of spin coating, spraying rubbing method, chemical vapour deposition technique, evaporation or sputtering method.
11. manufacture methods as claimed in claim 8, wherein forming described first transparent insulating layer or/and after described second transparent insulating layer, also include polishing described first transparent insulating layer or/and described second transparent insulating layer.
12. manufacture methods as claimed in claim 8, wherein said semiconductor device includes a photovoltaic cell, and the energy gap of described first active layer is less than the energy gap of described second active layer.
13. manufacture methods as claimed in claim 8, also include the exposed surface being roughened described 3rd doped layer of the most described second doped layer.
14. manufacture methods as claimed in claim 8, also include:
Etch a part for described second semiconductor unit, a part for described first transparent insulating layer, a part for described second transparent insulating layer, a part for described first doped layer and a part for described first active layer, to expose described 4th doped layer；
An exposed surface at described 4th doped layer forms one first electrode.
15. manufacture methods as claimed in claim 8, also include；
Etch a part and the part for described second active layer of described 3rd doped layer, to expose described second doped layer；
Exposed surface at described second doped layer forms one second electrode.
16. manufacture methods as claimed in claim 8, the method for wherein said coupling includes heating or pressurization.
17. 1 kinds of semiconductor devices, including:
One first semiconductor unit；
One second semiconductor unit；
One transparent insulating layer, described transparent insulating layer is between described first semiconductor unit and described second semiconductor unit；And
A plurality of conducting structures, described a plurality of conducting structures run through one of them and described transparent insulating layer of described first semiconductor unit and described second semiconductor unit, and the first semiconductor unit described in electrical couplings and described second semiconductor unit,
The most each conducting structure includes:
One hole, described hole runs through one of them and described transparent insulating layer of described first semiconductor unit and described second semiconductor unit；
One insulating barrier, described insulating barrier is formed at the sidewall of described hole；
One conductive layer, described conductive layer fills up described hole, and the first semiconductor unit described in electrical couplings and described second semiconductor unit.
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