CN103545182B - A kind of low work function metal gate forming method - Google Patents
A kind of low work function metal gate forming method Download PDFInfo
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- CN103545182B CN103545182B CN201210241699.1A CN201210241699A CN103545182B CN 103545182 B CN103545182 B CN 103545182B CN 201210241699 A CN201210241699 A CN 201210241699A CN 103545182 B CN103545182 B CN 103545182B
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- work function
- thermal anneal
- anneal process
- metal gate
- layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
Abstract
The embodiment of the invention discloses a kind of low work function metal gate forming method, the method includes：Substrate is provided；In Grown interface layer film；High-K gate dielectric layer is grown on the layer film of interface；The deposited metal gate work function layer on high-K gate dielectric layer；Work function regulating course is deposited in metal gate work-function layer；The deposition filling metal on work function regulating course, and be heat-treated；A thermal anneal process and/or secondary thermal anneal process are carried out, wherein, a thermal anneal process is carried out after the completion of growth high-K gate dielectric layer, and the secondary thermal anneal process is carried out after the completion of deposited metal gate work function layer.The technical scheme provided by the embodiment of the present invention, can effectively strengthen regulating course low workfunction metal for the regulating power of work function, so as to realize low threshold voltage of the cmos device in the case of low-leakage current.
Description
Technical field
The present invention relates to semiconductor applications, more particularly, it relates to a kind of low work function metal gate forming method.
Background technology
With the continuous development of semiconductor technology, integrated circuit integration degree more and more higher, the size of device are also continuous
Reduce.But the continuous reduction of device size causes the performance of device also to receive very big impact.
For example, as cmos device characteristic size is less and less, in order to realize big saturation current, it is necessary to drop low-threshold power
Pressure.At present, a method for lowering threshold voltage is reducing threshold voltage using band edge function metal grid.For cmos circuit
In NMOS tube, need the metal gate of low work function to reduce threshold voltage, be to realize the purpose, it is general using in band or high
Mix low workfunction metal to realize in the metal gate of work function, for example, can mix the metals such as TiAl or Al, but this kind of regulation
There is the upper limit, because if low workfunction metal is mixed too much, leakage current can be caused to be increased dramatically.And leak electricity and flow through
Greatly, easily increase the power consumption of electronic device, cause electronic device temperature to raise, so as to affect the life-span of electronic device.
Therefore, to solve the above problems, need a kind of new low work function metal gate forming method.
The content of the invention
What the embodiment of the present invention was realized in：
A kind of low work function metal gate forming method is embodiments provided, including：
Substrate is provided；
In Grown interface layer film；
High-K gate dielectric layer is grown on boundary layer；
Thermal anneal process；
The deposited metal gate work function layer on high-K gate dielectric layer；
Work function regulating course is deposited in metal gate work-function layer；
The deposition filling metal on work function regulating course, and be heat-treated；
A thermal anneal process and/or secondary thermal anneal process are carried out, wherein, a thermal anneal process is high in growth
Carry out after the completion of K gate dielectric layers, the secondary thermal anneal process is carried out after the completion of deposited metal gate work function layer.
Compared with prior art, technical scheme provided in an embodiment of the present invention has advantages below：By in metal gate
Thermal anneal process is suitably introduced in forming process, effectively strengthens low workfunction metal for the regulating power of work function, so as to reality
Existing low threshold voltage of the cmos device in the case of low-leakage current.
Description of the drawings
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
Accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, without having to pay creative labor, may be used also
To obtain other accompanying drawings according to these accompanying drawings.
Fig. 1 is a kind of low work function metal gate structural representation involved by the embodiment of the present invention；
A kind of low work function metal gate forming method flow chart that Fig. 2 is provided by the embodiment of the present invention；
Another kind of low work function metal gate forming method flow chart that Fig. 3 is provided by the embodiment of the present invention；
The third low work function metal gate forming method flow chart that Fig. 4 is provided by the embodiment of the present invention.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than the embodiment of whole.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
The disclosure by being suitably introduced into annealing process in metal gate forming process, so as to effectively improve low workfunction metal
Regulating power in band or in the metal gate of high work function, so, without the need for mixing too in band or in high-work-function metal grid
Many low work(metals, so that it may realize the reduction of cmos device threshold voltage, and be not result in that leakage current is excessive.
As shown in figure 1, the low work(metal-gate structures schematic diagram involved by the disclosure.The structure is wrapped from bottom to up successively
Include：Semiconductor substrate 101；Interface layer film 102；High-K gate dielectric layer 103；Metal gate work-function layer 104；Work function regulating course
105 and filling metal level 106.
Embodiment one
For this purpose, present embodiments providing a kind of forming method of low work function metal gate, concrete steps refer to Fig. 2 institutes
Show, including：
Step S201：Semiconductor substrate 101 is provided；
In this step, substrate 101 is by taking Si as an example, but in actual applications, and substrate can include any suitable partly leading
Body substrate, can specifically be but not limited to Si, Ge, GeSi, GaAs, InP, GaInAs, SiC, SOI（Silicon-on-insulator）Or
Any III/V compound semiconductors of person etc..According to design requirement known in the art（Such as p-substrate or N-shaped lining
Bottom）, substrate 101 can be including various doping configurations.Additionally, substrate 101 can alternatively include epitaxial layer, can be changed by stress
Become to strengthen performance.
Step S202：Growth interface layer film 102 on the substrate 101；
In the present embodiment, interface layer film 102 can be SiO2Film.
Step S203：High-K gate dielectric layer 103 is grown on interface layer film 102；
In the present embodiment, high-K gate dielectric layer 103 can include HfO2、HfSiO、HfSiON、HfTaO、HfTiO、
HfZrO and combinations thereof, and/or other suitable materials.High-K gate dielectric layer 103 can be for example, by chemical vapor deposition
（CVD）Or ald（ALD）Technique being formed.In embodiments of the present invention, the high-K dielectric layer 103 is HfO2It is thin
Film, and generated using ALD technique, its thickness can be between 2-4nm.
Step S204：Thermal anneal process is carried out to the structure；
In the present embodiment, heat-treatment temperature range can between 300-600 °C, the time can be controlled in 5s to 2min it
Between.Wherein, when thermal anneal process is carried out, can select to carry out in nitrogen or have in the atmosphere of a small amount of oxygen.
Step S205：The deposited metal gate work function layer 104 on high-K gate dielectric layer 103；
In actual applications, the material of metal gate work-function layer can including TaC, HfC, TiC, TiN, TiSiN, TaTbN,
TaErN、TaYbN、TaSiN、HfSiN、RuTax、NiTax、TaN、MoSiN、MoNx、TiCN、TaAlC、TiAlN、PtSix、
NiSix、Pt、Ru、Ir、Mo、HfRux、RuOxOr its combination etc., in the present embodiment, metal gate work-function layer adopts TiN, TaN
Deng its thickness range is may be selected between 1-5nm.
Step S206：Work function regulating course 105 is deposited in metal gate work-function layer 104；
To reduce the threshold voltage of cmos device, can be using one layer of low workfunction metal of deposition in metal gate work-function layer
Mode realizing.Under normal circumstances, work function can be served as using metals such as TiAl, Al or Ti and adjusts layer material, its thickness
Scope is may be selected between 0.2-7nm.
Step S207：The deposition filling metal level 106 on work function regulating course 105, and the structure is heat-treated.
In this step, the metal of W, TiAl, TiN can be deposited on work function regulating course 105 to form filling metal level,
Interconnection and stress are provided for the metal gate.
After completing the procedure, need to carry out quick thermal annealing process to total, in making work function regulating course
Low workfunction metal fully can spread.
In the present embodiment, after the deposition for completing high-K gate dielectric layer, thermal anneal process is introduced, effectively can be strengthened
Low workfunction metal for the regulating power of work function, so as to realize low-threshold power of the cmos device in the case of low-leakage current
Pressure.
Embodiment two
The embodiment of the present disclosure provides the forming method of another kind of low work function metal gate, and concrete steps refer to Fig. 3 institutes
Show, including：
Step S301：Semiconductor substrate 101 is provided；
In the present embodiment, substrate specifically refers to embodiment one using which kind of material, will not be described here, and is below related to
To the step of do same treatment.
Step S302：Growth interface layer film 102 on the substrate 101；
Step S303：High-K gate dielectric layer 103 is grown on interface layer film 103；
Step S304：The deposited metal gate work function layer 104 on high-K gate dielectric layer 103；
Step S305：Thermal anneal process is carried out to the structure；
In the present embodiment, thermal anneal process temperature range is can be controlled between 300-600 °C, and the time can be controlled in 5s and arrives
Between 5min.Wherein, when thermal anneal process is carried out, can select to carry out in nitrogen or have in the atmosphere of a small amount of oxygen.
Step S306：Work function regulating course 105 is deposited in metal gate work-function layer 104；
Step S307：The deposition filling metal level 106 on work function regulating course 105, and the structure is heat-treated.
As can be seen that the present embodiment is compared with embodiment one, after deposited metal gate work function step is completed, then enter
Row thermal anneal process.By the method, can effectively strengthen low workfunction metal for the regulating power of work function, so as to realize
Low threshold voltage of the cmos device in the case of low-leakage current.
Embodiment three
The embodiment of the present disclosure provides the forming method of the third low work function metal gate, and concrete steps refer to Fig. 4 institutes
Show, including：
Step S401：Semiconductor substrate 101 is provided；
In the present embodiment, substrate specifically refers to embodiment one using which kind of material, will not be described here, and is below related to
To the step of do same treatment.
Step S402：Growth interface layer film 102 on the substrate 101；
Step S403:High-K gate dielectric layer 103 is grown on interface layer film 102；
Step S404：Thermal anneal process is carried out to the structure；
In the present embodiment, heat-treatment temperature range can between 300-600 °C, the time can be controlled in 5s to 2min it
Between.Wherein, when thermal anneal process is carried out, can select to carry out in nitrogen or have in the atmosphere of a small amount of oxygen.
Step S405：The deposited metal gate work function layer 104 on high-K gate dielectric layer 103；
Step S406：Thermal anneal process is carried out to the structure again；
In the thermal anneal process of this step, thermal anneal process temperature range is can be controlled between 300-600 °C, and the time can
Control is between 5s to 5min.Wherein, when thermal anneal process is carried out, can select in nitrogen or have the atmosphere of a small amount of oxygen
Inside carry out.
Step S407：Work function regulating course 105 is deposited in metal gate work-function layer 104；
Step S408：The deposition filling metal level 106 on work function regulating course 105, and the structure is heat-treated.
Compared with the first two embodiment, the present embodiment is to improve low workfunction metal for the regulating power of work function,
Thermal anneal process is carried out in the growth for completing high-K dielectric layer 102 and after completing deposited metal gate work function layer respectively, so as to realize
Low threshold voltage of the cmos device in the case of low-leakage current.
The foregoing description of the disclosed embodiments, enables professional and technical personnel in the field to realize or using the present invention.
Various modifications to these embodiments will be apparent for those skilled in the art, as defined herein
General Principle can be realized without departing from the spirit or scope of the present invention in other embodiments.Therefore, the present invention
The embodiments shown herein is not intended to be limited to, and is to fit to and principles disclosed herein and features of novelty phase one
The most wide scope for causing.
Claims (10)
1. a kind of low work function metal gate forming method, it is characterised in that include：
Substrate is provided；
In Grown interface layer film；
High-K gate dielectric layer is grown on the layer film of interface；
The deposited metal gate work function layer on high-K gate dielectric layer；
Work function regulating course is deposited in metal gate work-function layer；
The deposition filling metal on work function regulating course, and be heat-treated；
A thermal anneal process and/or secondary thermal anneal process are carried out, wherein, a thermal anneal process is growing high K grid
Carry out after the completion of dielectric layer, the secondary thermal anneal process is carried out after the completion of deposited metal gate work function layer；
The secondary thermal anneal process temperature is 300-600 DEG C；
The secondary thermal anneal process time is 5s-5min.
2. method according to claim 1, it is characterised in that include：Thermal anneal process temperature is 300-600
℃。
3. method according to claim 1, it is characterised in that include：The thermal anneal process time is 5s-
2min。
4. method according to claim 1, it is characterised in that include：Thermal anneal process is in nitrogen or a small amount of
Carry out in the environment of oxygen.
5. method according to claim 2, it is characterised in that include：The secondary thermal anneal process is in nitrogen or a small amount of
Carry out in the environment of oxygen.
6. method according to any one of claim 1 to 5, it is characterised in that：The metal gate work-function layer material is
TiN or TaN.
7. method according to any one of claim 1 to 5, it is characterised in that it is Al that the work function adjusts layer material
Or TiAl or Ti.
8. method according to any one of claim 1 to 5, it is characterised in that the high-K gate dielectric layer thickness is 2-
4nm。
9. method according to any one of claim 1 to 5, it is characterised in that the metal gate work-function layer thickness is
1-5nm。
10. method according to any one of claim 1 to 5, it is characterised in that the work function regulating course thickness is
0.2-7nm。
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Citations (3)
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|---|---|---|---|---|
| CN101361173A (en) * | 2006-01-20 | 2009-02-04 | 国际商业机器公司 | Introduction of metal impurity to change workfunction of conductive electrodes |
| CN101800178A (en) * | 2009-02-09 | 2010-08-11 | 中国科学院微电子研究所 | Preparation method of hafnium silicon aluminum oxygen nitrogen high-dielectric constant gate dielectric |
| CN102087967A (en) * | 2009-12-04 | 2011-06-08 | 复旦大学 | Method for effectively modulating TiNx metal gate work function |
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| JP4358252B2 (en) * | 2007-03-27 | 2009-11-04 | 株式会社東芝 | Memory cell of nonvolatile semiconductor memory |
| US8298927B2 (en) * | 2010-05-19 | 2012-10-30 | Institute of Microelectronics, Chinese Academy of Sciences | Method of adjusting metal gate work function of NMOS device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101361173A (en) * | 2006-01-20 | 2009-02-04 | 国际商业机器公司 | Introduction of metal impurity to change workfunction of conductive electrodes |
| CN101800178A (en) * | 2009-02-09 | 2010-08-11 | 中国科学院微电子研究所 | Preparation method of hafnium silicon aluminum oxygen nitrogen high-dielectric constant gate dielectric |
| CN102087967A (en) * | 2009-12-04 | 2011-06-08 | 复旦大学 | Method for effectively modulating TiNx metal gate work function |
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