CN103544678A - Video image processing device and video image processing method - Google Patents
Video image processing device and video image processing method Download PDFInfo
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- CN103544678A CN103544678A CN201210243026.XA CN201210243026A CN103544678A CN 103544678 A CN103544678 A CN 103544678A CN 201210243026 A CN201210243026 A CN 201210243026A CN 103544678 A CN103544678 A CN 103544678A
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Abstract
An embodiment of the invention provides a video image processing device and a video image processing method. The video image processing method includes that a first processor is utilized to realize horizontal zoom of original image data, and during the horizontal zoom is performed by the first processor, a second processor is utilized to perform vertical zoom on first image data subjected to the horizontal zoom, so that parallel processing of the horizontal zoom by the first processor and the vertical zoom by the second processor is realized, and image processing is quickened even by utilizing a complicated three-convolution algorithm for image zoom processing since a parallel processing mode by the dual processors is adopted.
Description
Technical field
The present invention relates to the communications field, relate in particular to a kind of video image processing device and method.
Background technology
Video image amplifies and to be widely used with dwindling in a lot of fields.Existing digital video convergent-divergent algorithm mainly contains neighbor algorithm, secondary linear interpolation algorithm and cubic convolution algorithm.Neighbor algorithm is only used the gray-scale value as this sampled point from the gray-scale value of the nearest pixel of sampled point to be measured, do not consider the impact of other neighbor pixels, thereby after resampling, gray-scale value has obvious uncontinuity, image quality loss is larger, can produce obvious mosaic and crenellated phenomena.Bilinear interpolation algorithm is considered the sampled point to be measured impact of four direct neighbor pixel gray-scale values around, do not consider the impact of gray-value variation rate between each adjoint point, therefore there is the character of low-pass filter, cause the high fdrequency component of image after convergent-divergent to incur loss, it is comparatively fuzzy that image border becomes to a certain extent.Cubic convolution algorithm is not only considered the impact of four direct neighbor pixel gray-scale values around, also considers the impact of their gray-value variation rates.Therefore overcome the weak point of first two method, can produce the edge more more level and smooth than bilinear interpolation, reached better image effect, but because algorithm is complicated, calculated amount causes greatly execution efficiency not high.
Also do not have at present scheme when utilizing cubic convolution algorithm to carry out video image zooming, effectively to improve the efficiency that image is processed.
Summary of the invention
The embodiment of the present invention provides a kind of video image processing device and method, for improving image scaling processing speed, even if make to utilize complicated cubic convolution algorithm to carry out image scaling processing, also can guarantee higher treatment effeciency.
, described device comprises first processor and the second processor, described first processor and described the second processor concurrent working, wherein:
Described first processor, for raw image data is carried out to horizontal scaling, when the horizontal scaling of every row raw image data is completed, the first view data after this row horizontal scaling is completed is deposited to specified memory space;
Described the second processor, carries out vertically scale for the first view data that described specified memory space is stored.
The utilization method that video image processing device carries out video image processing as mentioned above, described method comprises:
Utilize first processor to carry out horizontal scaling to raw image data;
When first processor completes the horizontal scaling of every row raw image data, the first view data after this row horizontal scaling is completed is deposited to specified memory space;
Utilize the second processor to carry out vertically scale to first view data of storing in described specified memory space.
The scheme providing according to the embodiment of the present invention, can utilize first processor to realize the horizontal scaling of raw image data, and can be when first processor carries out horizontal scaling, utilize the first view data that the second processor completes for horizontal scaling to carry out vertically scale, thereby realize, first processor carries out horizontal scaling, the second processor carries out the parallel processing of vertically scale, even if make to utilize complicated cubic convolution algorithm to carry out image scaling processing, owing to adopting the mode of dual processor parallel processing, also can effectively improve the speed that image is processed.
Accompanying drawing explanation
The structural representation of the video image processing device that Fig. 1 provides for the embodiment of the present invention one;
The structural representation of the video image processing device that Fig. 2 provides for the embodiment of the present invention one;
The flow chart of steps of the method for video image processing that Fig. 3 provides for the embodiment of the present invention two;
The flow chart of steps of the method for video image processing that Fig. 4 provides for the embodiment of the present invention three;
The first specified memory unit that Fig. 5 provides for the embodiment of the present invention three realize schematic diagram;
The data flowchart that Fig. 6 provides for the embodiment of the present invention four;
The processing time contrast schematic diagram that Fig. 7 provides for the embodiment of the present invention five.
Embodiment
In order to solve in video image zooming is processed, because cubic convolution algorithm exists, algorithm is complicated, calculated amount is large, cause utilizing cubic convolution algorithm to carry out video image zooming and can cause the slower problem of processing speed, the embodiment of the present invention proposes to utilize respectively processor to realize the parallel processing of horizontal scaling and the vertically scale of video image, thereby effectively improves image processing speed.Certainly, the scheme that the embodiment of the present invention provides is not only applicable to utilize cubic convolution algorithm to realize image scaling, is applicable to utilize other Image Zooming Algorithms to realize image scaling yet, and all can improve the speed that image is processed.
Below in conjunction with Figure of description and each embodiment, describe.
Embodiment mono-,
The embodiment of the present invention one provides a kind of video image processing device, and the structure of this device can comprise first processor 11 and the second processor 12 as shown in Figure 1, described first processor and described the second processor concurrent working, wherein:
Described first processor 11 is for raw image data is carried out to horizontal scaling, and when the horizontal scaling of every row raw image data is completed, the first view data after this row horizontal scaling is completed is deposited to specified memory space; Described the second processor 12 carries out vertically scale for the first view data that described specified memory space is stored.
Concrete, described the second processor 12 can be regularly or for reading in real time described specified memory space, when the first view data of determining after described specified memory space stores horizontal scaling and completes, first view data of storing in described specified memory space is carried out to vertically scale.Or described the second processor 12 also can, according to the notice of described first processor, carry out vertically scale to first view data of storing in described specified memory space.
By dual processor, realize the horizontal scaling of image and the mode of vertically scale parallel processing, can effectively improve the speed that image is processed, even if make to utilize complicated algorithm to carry out image scaling, also can guarantee the speed that image scaling is processed.
Concrete, because DM648 is Leonardo da Vinci (DaVinci) the technology digital signal processor (DSPs) of processing for image specially, engine video image coprocessor (VICP) based on instruction is supported the video processing functions such as color space conversion, scaled, solution alternate-line scanning, therefore, in the present embodiment, can consider using DM648 primary processor as first processor, realize the horizontal scaling of view data, using video image coprocessor VICP as the second processor, realize the vertically scale of view data.
Described first processor is DM648 primary processor, described the second processor is that the structure of the video image processing device of video image coprocessor VICP can be as shown in Figure 2, this device is except comprising DM648 primary processor and VICP, can further include Double Data Rate synchronous DRAM (DDR, Double Date Rate) 13:
Described Double Data Rate synchronous DRAM 13 is for storing raw image data;
Described DM648 primary processor 11 carries out horizontal scaling for the raw image data that described DDR is stored, when the horizontal scaling of every row raw image data is completed, the first view data after this row horizontal scaling is completed is deposited the first specified memory unit to VICP, and at VICP described in setting time trigger.For example, described DM648 primary processor 11 can be according to Image Zooming Algorithm requirement, and the first view data of depositing in determining the first specified memory unit enough described video image coprocessor 12 is carried out moment of vertically scale, triggers described VICP.
Described video image coprocessor 12, for according to the triggering of described DM648 primary processor, carries out vertically scale to first view data of storing in described the first specified memory unit.
In the present embodiment, with DM648 primary processor, partial original image data are carried out after horizontal scaling, and other raw image datas are being carried out in the process of horizontal scaling, the first view data that VICP carries out after horizontal scaling this part is carried out the parallel processing that vertically scale is realized horizontal scaling and vertically scale, if horizontal scaling execution speed is very fast, can start as early as possible the vertically scale of view data.And, when utilizing some algorithm to carry out image scaling, need the data after multirow horizontal scaling can carry out vertically scale, for example, if utilize cubic convolution algorithm to carry out image scaling, need the first view data after 4 row horizontal scalings can carry out vertically scale processing.Therefore, to a certain extent, can think that the quickening of horizontal scaling speed can be accelerated the speed that image is processed.
When DM648 primary processor carries out horizontal scaling to the raw image data of storing in described DDR, raw image data can be moved to the memory headroom to self.In order further to improve the speed that image is processed, preferably, can in DM648 primary processor, take the ping-pong-buffer internal storage structure of two buffer memorys, in DM648 primary processor, configuration comprises the secondary internal memory 111 of the first buffer memory (can represent with Buffer A) and the second buffer memory (can represent with Buffer B):
When DM648 processing unit carries out horizontal scaling to move a line raw image data the first buffer memory from DDR, the second buffer memory is moved a line raw image data to self for receiving from DDR, when DM648 processing unit carries out horizontal scaling to move a line raw image data the second buffer memory from DDR, the first buffer memory is moved a line raw image data to self for receiving from DDR, thereby utilize the first buffer memory and the second buffer memory to realize the parallel of data-moving and data processing, further improve the speed of data processing.
It is that the DM648 processing unit 112 that DM648 primary processor comprises is realized that DM648 primary processor carries out to the raw image data of storing in described DDR that horizontal scaling can be understood as.Can be understood as DM648 processing unit, for carrying out horizontal scaling to move the raw image data of secondary internal memory from DDR.
Concrete, except the first specified memory unit 121(can represent with Coefficient Memory, for the first view data after storing horizontal scaling and completing) outside, described VICP can also comprise that VICP processing unit 122, the second specified memory unit 123(can represent with Command Memory) and the 3rd specified memory unit 124(can represent with Image Memory):
The second specified memory unit 123 is for storing vertically scale order;
The vertically scale order of VICP processing unit 122 for storing according to the second specified memory unit, the first view data after the horizontal scaling in described the first specified memory unit is completed is carried out vertically scale;
The 3rd specified memory unit 124 is for the second view data after storing vertically scale and completing.
Further, described device can further include enhancement mode direct memory access EDMA controller 14:
Described EDMA controller 14 is for raw image data is moved to described secondary internal memory from described DDR, and the second view data after vertically scale is completed is moved described DDR from described the 3rd specified memory unit.Thereby can utilize the EDMA technology that can realize high speed data transfer, realize moving fast of data, further improve image processing speed.And preferably, EDMA controller is moved described secondary internal memory by raw image data from described DDR, and the operation of moving described DDR from described the 3rd specified memory unit of the second view data after vertically scale is completed also can be understood as parallel carrying out, make can to obtain as early as possible in DDR the view data after horizontal scaling and vertically scale are processed.
Based on same inventive concept, provide following method with the embodiment of the present invention one.
Embodiment bis-,
The embodiment of the present invention two provides a kind of method of video image processing, and the device that the method utilizes the embodiment of the present invention one to provide is realized video image and processed, and the step of the method as shown in Figure 3, comprising:
Step 101, utilize first processor to carry out horizontal scaling to raw image data.
Step 102, deposit the first view data after horizontal scaling.
This step comprises, when first processor completes the horizontal scaling of every row raw image data, the first view data after this row horizontal scaling is completed is deposited to specified memory space.
Step 103, carry out vertically scale.
This step can be understood as, and during the first view data after described specified memory space stores horizontal scaling and completes, utilizes the second processor to carry out vertically scale to first view data of storing in described specified memory space.
In the present embodiment, can be understood as, the first view data after horizontal scaling is carried out to vertically scale, thereby obtain the second view data after horizontal scaling and vertically scale, therefore, can be understood as step 101 ~ step 103 order carries out, and due in step 103, parts of images data are being carried out after horizontal scaling, can carry out the vertically scale of view data is processed, therefore, in fact, horizontal scaling operation and vertically scale operation can be understood as by first processor and the second processor executed in parallel, thereby can improve the speed that image scaling is processed.
First processor take below as DM648 primary processor, and the second processor is VICP, and utilizes cubic convolution algorithm that a two field picture of 720*576 is amplified to 1280*720 for example, and the scheme of the embodiment of the present invention two is elaborated.
Embodiment tri-,
The embodiment of the present invention three provides a kind of method of video image processing, and the step of the method can as shown in Figure 4, comprise:
In this step, according to image scaling size, can set up vertically scale order in the order space of VICP, and be positioned in the second specified memory unit of VICP.
In the vertically scale order of setting up, can comprise following parameter: the deposit position of order (can be understood as reference position and the size of the second specified memory unit), the start address of pending view data (can be understood as the reference position of the first specified memory unit), the start address (can be understood as the reference position of the 3rd specified memory unit) that after processing, view data is deposited, the width of pending view data (can be understood as the width of pending view data horizontal direction, as in the present embodiment, after level is amplified, the width of pending view data is 1280 pixels), the line number of pending view data is (owing to adopting cubic convolution algorithm, each vertically scale action need carries out for the pending view data of 4 row, therefore in the first specified memory unit, can select the pending view data of 4 row to process.This parameter can be characterized in the first specified memory unit the order of selecting which pending view data of 4 row and selecting) and the filter factor (this parameter, for the pending view data of 4 row of selecting, is set according to cubic convolution algorithm) of corresponding row data.
Concrete, DM648 primary processor can call ixmenc_set_saturation () interface successively, and imxenc_filter () interface and imxenc_sleep () interface are set up the order of vertically scale in the order space of VICP.
In the order of initialization vertically scale, can be configured EDMA controller, and start EDMA controller a line raw image data is moved to the secondary internal memory of DM648 primary processor from DDR, as, start EDMA controller a line raw image data is moved to the first buffer memory (Buffer A) secondary internal memory from DDR.
In this step, can judge whether the every a line in raw image data all have been carried out to convergent-divergent processing (comprising horizontal scaling and vertically scale).Concrete, in the present embodiment, can judge whether the convergent-divergent processing of 720 row raw image datas all completes.
The executive agent of this step can be DM648 primary processor, and DM648 primary processor can directly determine whether the horizontal scaling processing of self completes.And can pass through IMX-wait () interface, and to VICP, send inquiry request receiving feedback information, judge in VICP, whether vertically scale processing finishes.
If judge image data scaling processing, not yet complete, can continue to perform step 203, otherwise, can process ends.
Whether step 203, determined level convergent-divergent are processed and are completed.
In this step, can judge whether the every a line in raw image data all have been carried out to horizontal scaling processing, concrete, in the present embodiment, can judge whether the horizontal scaling processing of 720 row raw image datas all completes.If judge horizontal scaling processing, not yet complete, can continue to perform step 204, otherwise, can redirect execution step 205.
In this step, can utilize secondary internal memory to realize the parallel work-flow of data-moving and data processing, as, suppose that EDMA controller moves a line raw image data to the first buffer memory (Buffer A) secondary internal memory from DDR, DM648 processing unit carries out horizontal scaling to a line raw image data of moving from DDR the first buffer memory (Buffer A), and simultaneously, if raw image data is not yet all moved to secondary internal memory, can start EDMA controller next line raw image data is moved in the second buffer memory (Buffer B).
Owing to utilizing cubic convolution algorithm to carry out image scaling, need 4 row view data can realize vertically scale, therefore, in this step, can judge whether that enough view data carry out vertically scale.If define enough view data, carry out vertically scale, can continue to perform step 206, otherwise, can jump to step 202.
In the present embodiment, defining enough view data carries out vertically scale and can be understood as and in the first specified memory unit, at least store 4 row the first view data.
Can be for carrying out vertically scale if determine enough view data, each, start before VICP does vertically scale, can be according to the filter factor in the sequential update vertically scale order of image data lines in VICP the first specified memory unit.
Therefore, in this step, when defining enough view data and carry out vertically scale, can upgrade the correlation parameter in vertically scale order.As, determine the nominated bank in the first specified memory unit that this vertically scale is corresponding, upgrade the filter factor of line number and the corresponding row data of the pending view data in vertically scale order.
It should be noted that, in the present embodiment, can be by the first specified memory cell location for storing the circulation buffer of 5 row view data, DM648 primary processor is placed directly into the view data after horizontal scaling is processed in the first specified memory unit, can, with behavior unit, deposit continuously.For example, as shown in Figure 5, the pending data of 5 row (the first view data) can be deposited altogether in the first specified memory unit, and while making wherein 4 row read to do vertically scale and process for VICP, DM648 primary processor can write the pending data of new a line.1,2,3,4,5 represent respectively the pending data of a line, and corresponding memory headroom is used respectively buffer1, buffer2, and buffer3, buffer4, buffer5 represents.Write from buffer1, buffer2 then, buffer3, buffer4 is until buffer5, then buffer1, buffer2 ..., so continuous circulation is deposited.When writing buffer3, VICP can read buffer4, buffer5, and buffer1, the data of buffer2 are done vertically scale.Now, the line number that can upgrade pending view data is 4,5,1,2(utilizes buffer4 in the first specified memory unit, buffer5, buffer1, the first view data that buffer2 preserves is respectively carried out vertically scale), and the filter factor that upgrades corresponding row data is buffer4, buffer5, buffer1, filter factor corresponding to every row the first view data of preserving in buffer2.
In the present embodiment, 5 first view data of passing through after horizontal scaling can be stored in the first specified memory unit, while making 4 row first view data of VICP in utilizing the first specified memory unit carry out vertically scale, can also utilize the first specified memory unit to continue to receive the first view data after horizontal scaling, make in vertically scale process, the view data of pending vertically scale operation such as still can receive, after a vertically scale has been operated, can carry out in time vertically scale operation next time, further improve the speed that image is processed.
In this step, concrete, DM648 can pass through IMX start() interface, notice VICP carries out vertically scale processing.VICP is after receiving notice, can be according to the vertically scale order after upgrading, the first view data in the first specified memory unit is carried out to vertically scale processing, and the second view data obtaining after vertically scale can being processed is deposited to the 3rd specified memory unit.Now, DM648 primary processor can configure EDMA controller, and the second view data obtaining after vertically scale is processed is moved to DDR.Certainly, at configuration EDMA controller, the second view data obtaining after vertically scale is processed is moved to before DDR, DM648 primary processor can configure the 3rd specified memory unit to DSP(DM648) available, concrete, DM648 primary processor can be by IMGBUF switch() interface configuration the 3rd specified memory unit can use DSP.
At VICP, the first view data in the first specified memory unit is completed after vertically scale processing, can jump to step 202.
In the present embodiment, the executive agent of each step can be understood as DM648 primary processor, concrete, can be understood as the DM648 processing unit in DM648 primary processor.
Below by the data flow in tetra-pairs of embodiment of the present invention three of embodiment, describe.
Embodiment tetra-,
In the embodiment of the present invention three, data flow can be as shown in Figure 6, and wherein, raw image data is moved to the secondary internal memory DM648 primary processor from DDR by EDMA.A line raw image data carries out after the convergent-divergent computing of horizontal direction, is stored the first specified memory unit to VICP.View data in the first specified memory unit is carried out after the convergent-divergent computing of vertical direction, is stored the 3rd specified memory unit to VICP.View data in the 3rd specified memory unit is moved to DDR by EDMA, makes can obtain the view data through horizontal scaling and vertically scale in DDR.
Below by when adopting cubic convolution algorithm to carry out image scaling, the scheme of utilizing prior art to provide, the contrast of spent data processing time, describes the lifting of the present invention program's data-handling efficiency with utilizing the present invention program.
Embodiment five,
As shown in Figure 7, in compiling condition, it is non-debugging mode, open 3 grades and optimize option, in the situation of the cubic convolution convergent-divergent api interface that use ti provides, the convergent-divergent time of realizing of utilizing the present invention program to be amplified to HD form (1280*720) two field picture to SD form (702*576) is 6.27ms.
Under equal conditions, (compiling condition is non-debugging mode, open 3 grades and optimize option, the cubic convolution convergent-divergent api interface that uses ti to provide), DM648 is used original c code, and the convergent-divergent time of realizing that SD form (702*576) is amplified to HD form (1280*720) two field picture needs 638ms.If the linear assembly code that uses ti to provide replaces original c code, required time reduces to 31.76ms.Even and further configured EDMA controller, optimized internal memory use, required time is also wanted 10.32ms.This means, use the scheme providing of the present invention to realize zooming digital video image, can obtain significant speed and promote, reach good image scaling treatment effeciency.
Those skilled in the art should understand, the application's embodiment can be provided as method, system or computer program.Therefore, the application can adopt complete hardware implementation example, implement software example or in conjunction with the form of the embodiment of software and hardware aspect completely.And the application can adopt the form that wherein includes the upper computer program of implementing of computer-usable storage medium (including but not limited to magnetic disk memory, CD-ROM, optical memory etc.) of computer usable program code one or more.
The application is with reference to describing according to process flow diagram and/or the block scheme of the method for the embodiment of the present application, equipment (system) and computer program.Should understand can be in computer program instructions realization flow figure and/or block scheme each flow process and/or the flow process in square frame and process flow diagram and/or block scheme and/or the combination of square frame.Can provide these computer program instructions to the processor of multi-purpose computer, special purpose computer, Embedded Processor or other programmable data processing device to produce a machine, the instruction of carrying out by the processor of computing machine or other programmable data processing device is produced for realizing the device in the function of flow process of process flow diagram or a plurality of flow process and/or square frame of block scheme or a plurality of square frame appointments.
These computer program instructions also can be stored in energy vectoring computer or the computer-readable memory of other programmable data processing device with ad hoc fashion work, the instruction that makes to be stored in this computer-readable memory produces the manufacture that comprises command device, and this command device is realized the function of appointment in flow process of process flow diagram or a plurality of flow process and/or square frame of block scheme or a plurality of square frame.
These computer program instructions also can be loaded in computing machine or other programmable data processing device, make to carry out sequence of operations step to produce computer implemented processing on computing machine or other programmable devices, thereby the instruction of carrying out is provided for realizing the step of the function of appointment in flow process of process flow diagram or a plurality of flow process and/or square frame of block scheme or a plurality of square frame on computing machine or other programmable devices.
Although described the application's preferred embodiment, once those skilled in the art obtain the basic creative concept of cicada, can make other change and modification to these embodiment.So claims are intended to all changes and the modification that are interpreted as comprising preferred embodiment and fall into the application's scope.
Obviously, those skilled in the art can carry out various changes and modification and the spirit and scope that do not depart from the application to the application.Like this, if within these of the application are revised and modification belongs to the scope of the application's claim and equivalent technologies thereof, the application is also intended to comprise these changes and modification interior.
Claims (7)
1. a video image processing device, is characterized in that, described device comprises first processor and the second processor, described first processor and described the second processor concurrent working, wherein:
Described first processor, for raw image data is carried out to horizontal scaling, when the horizontal scaling of every row raw image data is completed, the first view data after this row horizontal scaling is completed is deposited to specified memory space;
Described the second processor, carries out vertically scale for the first view data that described specified memory space is stored.
2. device as claimed in claim 1, is characterized in that, described first processor is DM648 primary processor, and described the second processor is video image coprocessor VICP, and described device also comprises Double Data Rate synchronous DRAM DDR:
Described DDR, for storing raw image data;
Described DM648 primary processor, for the raw image data that described DDR is stored, carry out horizontal scaling, when the horizontal scaling of every row raw image data is completed, the first view data after this row horizontal scaling is completed is deposited the first specified memory unit to VICP, and at VICP described in setting time trigger;
Described VICP, for according to the triggering of described DM648 primary processor, carries out vertically scale to first view data of storing in described the first specified memory unit.
3. device as claimed in claim 2, is characterized in that, described DM648 primary processor comprises DM648 processing unit and a secondary internal memory:
Described DM648 processing unit, for carrying out horizontal scaling to move the raw image data of secondary internal memory from DDR;
Described secondary internal memory comprises the first buffer memory and the second buffer memory, when DM648 processing unit carries out horizontal scaling to move a line raw image data the first buffer memory from DDR, the second buffer memory is moved a line raw image data to self for receiving from DDR, when DM648 processing unit carries out horizontal scaling to move a line raw image data the second buffer memory from DDR, the first buffer memory is moved a line raw image data to self for receiving from DDR.
4. device as claimed in claim 3, is characterized in that, except the first specified memory unit, described VICP also comprises VICP processing unit, the second specified memory unit and the 3rd specified memory unit:
The second specified memory unit, for storing vertically scale order;
VICP processing unit, for the vertically scale order of storing according to the second specified memory unit, the first view data after the horizontal scaling in described the first specified memory unit is completed is carried out vertically scale;
The 3rd specified memory unit, for the second view data after storing vertically scale and completing.
5. device as claimed in claim 4, is characterized in that, described device also comprises enhancement mode direct memory access EDMA controller:
Described EDMA controller, for raw image data is moved to described secondary internal memory from described DDR, and the second view data after vertically scale is completed is moved described DDR from described the 3rd specified memory unit.
6. device as claimed in claim 2, it is characterized in that, when described device is used for utilizing cubic convolution algorithm to carry out video image processing, described the first specified memory cell location is the space size of storage 5 row the first view data, when VICP reads the first view data that wherein 4 row have write and does vertically scale and process, DM648 primary processor writes the first view data to remaining a line.
Utilization as arbitrary in claim 1 ~ 6 as described in a video image processing device method of carrying out video image processing, it is characterized in that, described method comprises:
Utilize first processor to carry out horizontal scaling to raw image data;
When first processor completes the horizontal scaling of every row raw image data, the first view data after this row horizontal scaling is completed is deposited to specified memory space;
Utilize the second processor to carry out vertically scale to first view data of storing in described specified memory space.
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