CN103531554B - Semiconductor subassembly and manufacture method thereof - Google Patents
Semiconductor subassembly and manufacture method thereof Download PDFInfo
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- CN103531554B CN103531554B CN201310336911.7A CN201310336911A CN103531554B CN 103531554 B CN103531554 B CN 103531554B CN 201310336911 A CN201310336911 A CN 201310336911A CN 103531554 B CN103531554 B CN 103531554B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- Microelectronics & Electronic Packaging (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract
The open a kind of semiconductor subassembly of the present invention and manufacture method thereof, described semiconductor subassembly comprises semiconductor substrate and at least one passivation layer, described passivation layer comprises several rectangular element, several Cutting Road and several bridge part, described rectangular element spaced-apart relation, each Cutting Road lays respectively between two adjacent rectangular elements, and described bridge part is spaced across described Cutting Road and connects two adjacent rectangular elements.By being horizontally set with bridge part at described Cutting Road, make the surface of two adjacent rectangular elements can utilize the joint of bridge part, reach surface continuous print effect, make follow-up plating bath can connect all rectangular elements of described passivation layer, to improve the yield of plating.
Description
Technical field
The invention relates to a kind of semiconductor subassembly and manufacture method thereof, cut in particular to one
Road is crossed with semiconductor subassembly and the manufacture method thereof of bridge part.
Background technology
The technology of existing straight-through silicon perforation (Through Silicon via, TSV), is to be arranged by vertical circuit
In silicon substrate, it is provided that there is upper zone density and the 3D circuit structure without side joint circuit, straight-through
In the manufacture process of silicon perforation, silicon substrate elder generation etching and punching, then insert such as copper (Cu), silver (Ag), gold
(Au) metallic conductor such as, after the perforation of straight-through silicon is formed, then blanketing passivation layer, using as silicon substrate
And the insulant between conductor.
Along with the miniaturization of manufacture of semiconductor, the opening made by straight-through silicon perforation is more and more less, covers
Passivation layer on described silicon substrate also needs to revise accordingly, and then uses the passivating material (High of high-res
Resolution Passivation Material), with blanketing in described silicon substrate or the stacking of several layers.Institute
After stating passivation layer shaping, the lateral margin of the passivation layer of Cutting Road both sides is relatively easy to form abrupt slope, and then produces
The wall vertical with passivation layer end face, owing to the surface of described passivation layer is interrupted because of Cutting Road, and logical
When crossing physical deposition mode formation Seed Layer (the seed layer) such as sputtering (sputtering), Seed Layer cannot be adhered to
On described vertical wall, the surface of described passivation layer is caused to carry out plating system in later use Seed Layer
Make to have when bump bottom metal layer (UBM) or redistribution (RDL) circuit discontinuous situation, i.e. one wafer
On partial chip district cannot be successfully formed Seed Layer, thus impact powers in described passivation layer surface and is coated with
Make bump bottom metal layer or the yield of redistribution circuit.
Therefore, it is necessary to a kind of wafer and the semiconductor subassembly made thereof and manufacture method are provided, existing to solve
There is the problem existing for technology.
Summary of the invention
In view of this, the present invention provides a kind of wafer and the semiconductor subassembly made thereof and manufacture method, with
Solve existing to carry out plating in passivation layer surface and have discontinuous problem.
Present invention is primarily targeted at a kind of semiconductor subassembly of offer, it can be by described Cutting Road
It is horizontally set with bridge part, improves the plating yield of all chip region on same wafer.
The secondary objective of the present invention is to provide another kind of semiconductor subassembly, and it can avoid plating to be attached to passivation layer
The Seed Layer on surface has discontinuous situation in Cutting Road position.
The secondary objective of the present invention is to provide the manufacture method of another kind of semiconductor subassembly, and it can pass through
It is horizontally set with bridge part at described Cutting Road, has made the passivation layer surface of each chip region produce continuous print effect.
For reaching the object defined above of the present invention, one embodiment of the invention provides a kind of semiconductor subassembly, wherein
Described semiconductor subassembly comprises semiconductor substrate and at least one passivation layer, and described semiconductor substrate comprises one
Active surface, a back side and several perforating holes, the described back side in contrast to described active surface, described in rethread
Hole is through to the described back side from described active surface, and described passivation layer covers on the described back side, described blunt
Changing layer and comprise several rectangular element, several Cutting Road and several bridge part, described rectangular element is spaced
Arrangement, each Cutting Road lays respectively between two adjacent rectangular elements, described bridge part be spaced across
Described Cutting Road and connection two adjacent rectangular elements.
It addition, another embodiment of the present invention provides a kind of semiconductor subassembly, wherein said semiconductor subassembly bag
Containing semiconductor substrate and at least one passivation layer, described semiconductor substrate comprise an active surface, a back side,
Several perforating holes and four cutting edges, the described back side is in contrast to described active surface, and described perforating holes is from institute
Stating active surface and be through to the described back side, described passivation layer covers on the described back side, described passivation layer bag
Containing a rectangular element, a ring-type Cutting Road and several bridge part stub, described rectangular element has four
Individual side, described Cutting Road be positioned at the side of described rectangular element and described semiconductor substrate cutting edge it
Between, described bridge part stub is spaced across being positioned at described Cutting Road.
Furthermore, further embodiment of this invention provides the manufacture method of a kind of semiconductor subassembly, wherein said system
The method of making comprises step: purchase semiconductor wafer, comprise semiconductor substrate, an active surface, one
The back side and several perforating holes, the described back side is in contrast to described active surface, and described perforating holes is from described active
Surface is through to the described back side；And covering at least one passivation layer is on the described back side, and described passivation layer
Form several rectangular element, several Cutting Road and several bridge part, described rectangular element spaced-apart relation,
Each Cutting Road lays respectively between two adjacent rectangular elements, and described bridge part is spaced to be cut across described
Cut and connect two adjacent rectangular elements.
As it has been described above, by being horizontally set with bridge part at described Cutting Road, make the table of two adjacent rectangular elements
Face can utilize the joint of bridge part, reaches surface continuous print effect, makes follow-up plating bath to connect described
All rectangular elements of passivation layer, to improve the plating yield of all chip region on same wafer.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of one embodiment of the invention semiconductor subassembly (semiconductor crystal wafer).
Fig. 2 is the partial enlarged drawing of Fig. 1 semiconductor subassembly.
Fig. 3 is the line A-A sectional view of Fig. 2 semiconductor subassembly.
Fig. 4 is the line B-B sectional view of Fig. 2 semiconductor subassembly.
Fig. 5 to 6 is the sectional view of another embodiment of the present invention semiconductor subassembly (semiconductor crystal wafer).
Fig. 7 to 8 is the sectional view of yet another embodiment of the invention semiconductor subassembly (semiconductor crystal wafer).
Fig. 9 is the top view of further embodiment of this invention semiconductor subassembly (semiconductor chip).
Figure 10 is the line C-C sectional view of Fig. 9 semiconductor subassembly.
Detailed description of the invention
The explanation of following embodiment is graphic with reference to add, may be used to enforcement in order to illustrate the present invention
Specific embodiment.Furthermore, the direction term that the present invention is previously mentioned, the most upper and lower, top, the end, front,
Afterwards, left and right, inside and outside, side, surrounding, central authorities, level, laterally, vertically, longitudinally, axially,
Radially, the superiors or orlop etc., be only the direction with reference to annexed drawings.Therefore, the direction of use is used
Language is to illustrate and understand the present invention, and is not used to limit the present invention.
Refer to Fig. 1, shown in 2, the semiconductor subassembly 100 of one embodiment of the invention, it mainly comprises one
Semiconductor substrate 2 and at least one passivation layer 3 (Passivation), such as epoxy resin (epoxy), benzocyclobutene
(BCB, benzocyclobutene) or pi (PI, polyimide), described semiconductor subassembly 100
For semiconductor crystal wafer (Wafer), it is to make to have having of a tool integrated circuit on described semiconductor substrate 2
Surface, source, the present invention by describe in detail the most one by one the detail structure of above-mentioned each element, assembled relation and
Its operation principles.
Refer to Fig. 2, shown in 3, described semiconductor substrate 2 for example, silicon substrate, it comprises an active table
The back side 22, face 21, one and several perforating holes 23, the described back side 22 in contrast to described active surface 21,
Described perforating holes 23 is through to the described back side 22 from described active surface 21.
Described passivation layer 3 is simple layer in the present embodiment, its cover on the described back side 22, with as
The insulation part of one redistribution layer (redistribution layer).Described passivation layer 3 comprises several rectangular element
31, several Cutting Roads 32 (see Fig. 3) and several bridge part 33 (see Fig. 4), described rectangular element 31 is each other
Being spaced, each Cutting Road 32 lays respectively between two adjacent rectangular elements 31, described bridge part 33
It is spaced across described Cutting Road 32, and connects two adjacent rectangular elements 31, wherein said Cutting Road
The width (distances between two adjacent rectangular elements 31) of 32 is 80 microns to 120 microns, such as 90,
100 or 110 microns；The width of described bridge part 33 (both side edges of described bridge part 33 bearing of trend it
Between distance) be 10 microns to 200 microns, such as 20,30,50,75,100,120,150 or
180 microns.The design of described bridge part 33 width is not only available for electric current and passes through, when subsequent wafer is cut,
Also can avoid causing the peeling of described passivation layer 3.
It addition, described semiconductor subassembly 100 also comprises several conductive projection 4 (such as copper pillar bumps (Copper
Pillar), tin projection or gold projection), lay respectively at the bump bottom metal layer 24 (UBM) of described active surface 21
On, described conductive projection 4 and bump bottom metal layer 24 are pointed to the bottom surface of described perforating holes 23；And
Described semiconductor subassembly 100 can be more separately in end face plating another bump bottom metal of formation of described perforating holes 23
Layer, to combine another dimpling block 5 (micro-bump), in order to the described follow-up combination of semiconductor subassembly 100 one
Upper chip or the metal ball of upper packaging body or connection pad (not illustrating).
According to above-mentioned structure, described passivation layer 3 passes through to be horizontally set with bridge part 33 at described Cutting Road 32,
The surface making two adjacent rectangular elements 31 can utilize the joint of bridge part 33, makes described passivation layer 3
Surface produces continuous print effect, and the path of follow-up plating can connect described passivation by described bridge part 33
All rectangular elements 31 of layer 3, and then avoid by physical deposition mode shapes such as sputterings (sputtering)
Discontinuous situation is had, to improve when becoming Seed Layer (seed layer) on described rectangular element 31 surface
On same wafer, the follow-up plating in all chip region makes bump bottom metal layer (UBM) or redistribution (RDL) electricity
The yield on road.
Refer to Fig. 5, shown in 6, the semiconductor subassembly 100 of another embodiment of the present invention is similar in appearance to the present invention
One embodiment, and approximately along by similar elements title and figure number, but the difference characteristic of the present embodiment is:
Described semiconductor subassembly 100 comprises three layers of described passivation layer sequentially stacked 3,3 ', 3 ", described sequentially
The passivation layer 3,3 ', 3 of stacking " formed stepped (see Fig. 5) at described Cutting Road 32.It is,
The length of the bridge part 33 of the passivation layer 3 at the closer described back side 22 is less than further away from the described back side 22
The length of bridge part 33 ' of passivation layer 3 ', same, the length of the bridge part 33 ' of described passivation layer 3 '
Less than described passivation layer 3 " bridge part 33 " length.
According to above-mentioned structure, by being horizontally set with bridge part 33,33 ', 33 at described Cutting Road 32 ",
Described passivation layer 3,3 ', 3 can be made respectively " surface produce continuous print effect, i.e. in each step be intended to
At described passivation layer 3,3 ' or 3 " surface is initially formed Seed Layer re-plating and makes bump bottom metal layer or heavily divide
During cloth circuit, the path of plating can pass through described bridge part 33,33 ' or 33 respectively " surface connection described blunt
Change layer 3,3 ' or 3 " all rectangular elements, therefore can be respectively increased at described passivation layer 3,3 ', 3 "
Surface carries out the yield electroplated.Additionally, described semiconductor subassembly 100 can also sequentially stack two layers, four
Layer or above passivation layer.
Refer to Fig. 7, shown in 8, the semiconductor subassembly 100 of yet another embodiment of the invention is similar in appearance to the present invention
Another embodiment, and approximately along by similar elements title and figure number, described semiconductor subassembly 100 wraps equally
Containing three layers of described passivation layer sequentially stacked 3,3 ', 3 ", the described passivation layer 3,3 ', 3 sequentially stacked "
Formed stepped at described Cutting Road 32, but the difference characteristic of the present embodiment is: described perforating holes
23 stretch in described passivation layer 3 ', and the plating of described perforating holes 23 end face forms another concave downward
Metal level (does not indicates).
As it has been described above, the present embodiment can provide another kind of implements structure, again by described passivation layer 3,3 '
Or 3 " surface is initially formed Seed Layer re-plating and makes bump bottom metal layer or during redistribution circuit, the road of plating
Footpath can pass through described bridge part 33,33 ' or 33 respectively " surface connect described passivation layer 3,3 ' or 3 " institute
Having rectangular element, to improve at described passivation layer 3,3 ', 3 " surface carries out the yield electroplated.
Refer to Fig. 9, shown in 10, the semiconductor subassembly 100 ' of further embodiment of this invention is similar in appearance to this
A bright embodiment, and approximately along by similar elements title and figure number, but the difference characteristic of the present embodiment is:
Described semiconductor subassembly 100 ' is the semiconductor chip (Chip) separated by semiconductor crystal wafer cutting, its
Comprising semiconductor substrate 2 and at least one passivation layer 3, described semiconductor substrate 2 comprises an active surface
21, a back side 22, several perforating holes 23 and four cutting edges 25, the described back side 22 has in contrast to described
Surface, source 21, described perforating holes 23 is through to the described back side 22, described passivation from described active surface 21
Layer 3 covers on the described back side 22, and described passivation layer 3 comprises ring-type the cutting of rectangular element 31,
Cutting 320 and several bridge part stub 330, described rectangular element 31 has four sides 311, institute
State Cutting Road 320 and be positioned at the side 311 of described rectangular element 31 and the cutting edge of described semiconductor substrate 2
Between 25, described bridge part stub 330 is spaced and across being positioned at described Cutting Road 320.In this reality
Executing in example, described passivation layer 3 is one layer but it also may as it is shown in figure 5, be provided with two layers, three layers or with
On the described passivation layer 3 that sequentially stacks, be not limited thereto, the width of wherein said Cutting Road 320 is
40 microns to 60 microns (distance between side 311 and cutting edge 25), such as 45,50 or 55 are micro-
Rice；The width of described bridge part 330 is 10 microns to 200 microns.
Coordinating with reference to Fig. 1, shown in 3, further embodiment of this invention provides the manufacturer of a kind of semiconductor subassembly
Method, the manufacture method of wherein said semiconductor subassembly can comprise the steps of:
Purchase semiconductor wafer (sign), comprise semiconductor substrate 2, active surface 21,
The back side 22 and several perforating holes 23, the described back side 22 is in contrast to described active surface 21, described perforating holes
23 are through to the described back side 22 from described active surface 21.
Coordinate with reference to Fig. 2, shown in 3, cover at least one passivation layer 3 on the described back side 22, and institute
State passivation layer 3 and form several rectangular element 31, several Cutting Road 32 and several bridge part 33, described square
Shape unit 31 spaced-apart relation, each Cutting Road 32 lays respectively between two adjacent rectangular elements 31,
Described bridge part 33 is spaced across described Cutting Road 32 and connects two adjacent rectangular elements 31, with shape
The Cutting Road 32 becoming passivation layer 3 is crossed with the semiconductor crystal wafer of bridge part 33.
Coordinating with reference to Fig. 9, shown in 10, then cutting described semiconductor crystal wafer becomes several semiconductor subassembly
(semiconductor chip), each described semiconductor subassembly (semiconductor chip) has four cutting edges 25,
Cutting Road 320 that the rectangular element 31, one of described passivation layer 3 is ring-type and several bridge part stub 330,
Described rectangular element has four sides, and described Cutting Road 320 is positioned at the side of described rectangular element 31
Between 311 and described cutting edge 25, described bridge part stub 330 is spaced across being positioned at described cutting
Road 320.
The present invention is been described by by above-mentioned related embodiment, but above-described embodiment only implements the present invention
Example.It must be noted that, it has been disclosed that embodiment be not limiting as the scope of the present invention.On the contrary,
The amendment and the equalization that are contained in the spirit and scope of claims arrange and are all included in the scope of the present invention
In.
Claims (10)
1. a semiconductor subassembly, it is characterised in that: described semiconductor subassembly comprises:
Semiconductor substrate, comprises: an active surface；One back side, in contrast to described active surface；And number
Individual perforating holes, is through to the described back side from described active surface, and wherein a bump bottom metal layer is positioned at institute
State the bottom surface of perforating holes；And
At least one passivation layer, covers on the described back side, and described passivation layer comprises: several rectangular elements, that
This is spaced；Several Cutting Roads, each Cutting Road lays respectively between two adjacent rectangular elements；And
Several bridge parts, are spaced across described Cutting Road and connect two adjacent rectangular elements.
2. semiconductor subassembly as claimed in claim 1, it is characterised in that: described semiconductor subassembly comprises two layers
Below the described passivation layer sequentially stacked, the described passivation layer sequentially stacked is formed at described Cutting Road
Stepped.
3. semiconductor subassembly as claimed in claim 1, it is characterised in that: the passivation layer at the closer described back side
The length of bridge part less than the length of bridge part of the passivation layer further away from the described back side.
4. semiconductor subassembly as claimed in claim 1, it is characterised in that: the width of described Cutting Road is 80
Micron is to 120 microns.
5. semiconductor subassembly as claimed in claim 1, it is characterised in that: the width of described bridge part is 10
Micron is to 200 microns.
6. a semiconductor subassembly, it is characterised in that: described semiconductor subassembly comprises:
Semiconductor substrate, comprises: an active surface；One back side, in contrast to described active surface；Several
Perforating holes, is through to the described back side from described active surface, and wherein a bump bottom metal layer is positioned at described
The bottom surface of perforating holes；And four cutting edges；And
At least one passivation layer, covers on the described back side, and described passivation layer comprises: a rectangular element, has
Four sides；One ring-type Cutting Road, is positioned at the side of described rectangular element and described semiconductor substrate
Cutting edge between；And several bridge part stub, it is spaced across being positioned at described Cutting Road.
7. semiconductor subassembly as claimed in claim 6, it is characterised in that: described semiconductor subassembly comprises two layers
Below the described passivation layer sequentially stacked, the described passivation layer sequentially stacked is formed at described Cutting Road
Stepped.
8. semiconductor subassembly as claimed in claim 6, it is characterised in that: the width of described Cutting Road is 40
Micron is to 60 microns.
9. semiconductor subassembly as claimed in claim 6, it is characterised in that: the width of described bridge part is 10
Micron is to 200 microns.
10. the manufacture method of a semiconductor subassembly, it is characterised in that: described manufacture method comprises step:
Purchasing semiconductor wafer, it comprises: semiconductor substrate；One active surface；One back side, on the contrary
In described active surface；And several perforating holes, it is through to the described back side from described active surface, wherein
One bump bottom metal layer is positioned at the bottom surface of described perforating holes；And
Covering at least one passivation layer is on the described back side, and described passivation layer is formed: several rectangular elements,
Spaced-apart relation；Several Cutting Roads, each Cutting Road lays respectively between two adjacent rectangular elements；
And several bridge part, it is spaced across described Cutting Road and connects two adjacent rectangular elements.
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| CN201610412701.5A CN106098661B (en) | 2013-08-05 | 2013-08-05 | Semiconductor subassembly and its manufacturing method |
| CN201310336911.7A CN103531554B (en) | 2013-08-05 | 2013-08-05 | Semiconductor subassembly and manufacture method thereof |
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| CN103824831B (en) * | 2014-02-20 | 2016-08-17 | 清华大学 | A kind of base plate for packaging and preparation method thereof |
| CN108601241B (en) * | 2018-06-14 | 2021-12-24 | 环旭电子股份有限公司 | SiP module and manufacturing method thereof |
| CN110702753B (en) * | 2019-10-29 | 2020-09-08 | 华中科技大学 | Preparation method and product of array sensor of bridge-type micro-nano structure sensing unit |
| TWI766271B (en) * | 2020-04-30 | 2022-06-01 | 矽品精密工業股份有限公司 | Electronic package and method for fabricating the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101593733A (en) * | 2009-06-29 | 2009-12-02 | 晶方半导体科技（苏州）有限公司 | Encapsulating structure |
| CN102931156A (en) * | 2012-10-08 | 2013-02-13 | 日月光半导体制造股份有限公司 | Structure and manufacturing method of semiconductor chip |
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| JPS61222151A (en) * | 1985-03-27 | 1986-10-02 | Ibiden Co Ltd | Manufacture of printed wiring substrate for mounting semiconductor |
| JPH0864875A (en) * | 1994-08-25 | 1996-03-08 | Sharp Corp | Manufacture of thermoelectric converter |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101593733A (en) * | 2009-06-29 | 2009-12-02 | 晶方半导体科技（苏州）有限公司 | Encapsulating structure |
| CN102931156A (en) * | 2012-10-08 | 2013-02-13 | 日月光半导体制造股份有限公司 | Structure and manufacturing method of semiconductor chip |
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| CN103531554A (en) | 2014-01-22 |
| CN106098661B (en) | 2019-01-22 |
| CN106098661A (en) | 2016-11-09 |
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