CN103531491B - Semiconductor technology, semiconductor structure and package structure thereof - Google Patents
Semiconductor technology, semiconductor structure and package structure thereof Download PDFInfo
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- CN103531491B CN103531491B CN201210231782.0A CN201210231782A CN103531491B CN 103531491 B CN103531491 B CN 103531491B CN 201210231782 A CN201210231782 A CN 201210231782A CN 103531491 B CN103531491 B CN 103531491B
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- supporting part
- photoresist layer
- semiconductor technology
- metal level
- loading end
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1405—Shape
- H01L2224/14051—Bump connectors having different shapes
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
The invention relates to a semiconductor technology, a semiconductor structure and a package structure thereof. The semiconductor technology comprises the following steps: providing a carrier, wherein the carrier has a metal layer, and the metal layer has a plurality of substrate areas and a plurality of lateral areas; forming a first photoresist layer; forming a plurality of bearing parts; removing the first photoresist layer to expose the bearing parts, wherein each bearing part has a bearing surface, and each bearing surface has a first area and a second area; forming a second photoresist layer which exposes the first areas of the bearing surfaces; forming a plurality of joint parts, wherein the joint parts cover the first areas of the bearing surfaces so that the joint parts are enabled to be connected with the bearing parts to form snap bumps; removing the second photoresist layer to expose the snap bumps; and removing the lateral areas of the metal layer to enable a plurality of under-bump metal layers to be formed on the substrate areas.
Description
Technical field
The invention relates to a kind of semiconductor technology, in particular to a kind of quasiconductor work with button-type projection
Skill.
Background technology
Existing known semiconductor package has substrate, chip and solder, wherein existing known semiconductor packages
Structure makes the projection of chip electrically engage with the connection gasket of substrate by solder, more next yet with current electronic product volume
It is less, therefore the bump pitch on chip is also less and less, in this case, solder in reflow easy overflow to neighbouring projection
And short-circuit situation is produced, affect the percentage of A-class goods of product.
As can be seen here, above-mentioned existing semiconductor technology is in structure with use, it is clear that still suffered from inconvenience and defect, and
Urgently it is further improved.In order to solve above-mentioned problem, relevant manufactures there's no one who doesn't or isn't painstakingly seeking solution,
But have no that applicable design is developed completing for a long time always, and common product not have appropriate structure can solve the problem that above-mentioned
Problem, this is clearly the problem suddenly solved by related dealer.Therefore how to found a kind of semiconductor technology of new structure, half
Conductor structure and its packaging structure, real category is currently important to research and develop one of problem, and also becoming current industry pole needs improved target.
The content of the invention
It is an object of the present invention to overcome the defect that existing semiconductor technology is present, and provide a kind of new structure
Semiconductor technology, semiconductor structure and its packaging structure, technical problem to be solved are to provide a kind of semiconductor technology, non-
It is adapted to practicality.
The object of the invention to solve the technical problems employs the following technical solutions to realize.According to present invention proposition
Its include at least the following steps：A carrier is provided, the carrier has surface and is formed at the metal level on the surface, the metal
Layer has multiple substrate zones and multiple LHAs on the outside of substrate zone；The first photoresist layer is formed in the metal level, this
One photoresist layer has multiple first openings；Multiple supporting parts are formed in the described first opening；Remove first photoresist layer with
The supporting part is manifested, respectively the supporting part has loading end, respectively the loading end has the firstth area and the secondth area；Form the second light
Photoresist layer is in the metal level, and second photoresist layer covers the supporting part, and second photoresist layer has multiple second to open
Mouthful and second opening appears firstth area of the loading end；Form multiple junction surfaces to be open described second, and institute
Firstth area that junction surface covers the loading end is stated, so that respectively the junction surface connects the respectively supporting part and formation button-type is convex
Block (snap bump)；Remove second photoresist layer to manifest the button-type projection；And remove the described of the metal level
LHA, so that the substrate zone of the metal level forms multiple Underbump metallization layers.
The object of the invention to solve the technical problems can also be applied to the following technical measures to achieve further.
Aforesaid semiconductor technology, wherein described respectively supporting part has first thickness, respectively the junction surface has second
Thickness, the second thickness are more than the first thickness.
Aforesaid semiconductor technology, wherein described respectively supporting part includes the first bearing bed and the second bearing bed.
Aforesaid semiconductor technology, wherein the material of the described supporting part can be selected from gold, nickel or copper etc..
Aforesaid semiconductor technology, wherein the material at the described junction surface can be selected from gold, nickel or copper etc..
Aforesaid semiconductor technology, wherein the material of the described Underbump metallization layer can be selected from titanium/copper, titanium
Tungsten/copper or titanium tungsten/gold etc..
The object of the invention to solve the technical problems also employs the following technical solutions to realize.According to proposed by the present invention
Which includes at least：One carrier, which has surface and multiple Underbump metallization layers for being formed at the surface；And multiple button-types
Projection (snap bump), which is formed on the Underbump metallization layer, and respectively the button-type projection has supporting part and connects this and holds
The junction surface in load portion, respectively the supporting part there is loading end, respectively the loading end has the firstth area and the secondth area, and respectively the junction surface covers
Each firstth area of the loading end.
The object of the invention to solve the technical problems can also be applied to the following technical measures to achieve further.
Aforesaid semiconductor structure, wherein its described has additionally comprised Gold plated Layer, respectively the button-type is convex for the Gold plated Layer cladding
Block.
Aforesaid semiconductor structure, wherein described respectively Underbump metallization layer has ring wall, the Gold plated Layer cladding is described
Ring wall.
Aforesaid semiconductor structure, wherein described respectively supporting part has first thickness, respectively the junction surface has second
Thickness, the second thickness are more than the first thickness.
Aforesaid semiconductor structure, wherein described respectively supporting part includes the first bearing bed and the second bearing bed.
Aforesaid semiconductor structure, wherein the material of the described supporting part can be selected from gold, nickel or copper etc..
Aforesaid semiconductor structure, wherein the material at the described junction surface can be selected from gold, nickel or copper etc..
Aforesaid semiconductor structure, wherein the material of the described Underbump metallization layer can be selected from titanium/copper, titanium
Tungsten/copper or titanium tungsten/gold etc..
The object of the invention to solve the technical problems also employs the following technical solutions to realize in addition.Carry according to the present invention
Go out
The object of the invention to solve the technical problems can also be applied to the following technical measures to achieve further.
Aforesaid semiconductor packaging structure, wherein its described is included at least：One semiconductor structure, which includes：One
Carrier, which has surface and multiple Underbump metallization layers for being formed at the surface；And multiple button-type projections (snap bump),
Which is formed on the Underbump metallization layer, and respectively the button-type projection has supporting part and connects the junction surface of the supporting part, respectively
The supporting part has loading end, and respectively the loading end has the firstth area and the secondth area, and what respectively the junction surface covered each loading end should
Firstth area；And a substrate, which has multiple connecting elements and multiple solders, and respectively the solder is formed at the respectively connecting element
On, the connecting element is incorporated into the junction surface of the button-type projection, and the solder coats the junction surface and described
Supporting part described in solder connection and the connecting element.
Aforesaid semiconductor packaging structure, wherein the described solder is limited in secondth area of the loading end.
Aforesaid semiconductor packaging structure, wherein the material of the described becket is gold.
Aforesaid semiconductor packaging structure, wherein described respectively supporting part has first thickness, respectively the junction surface has
Second thickness, the second thickness are more than the first thickness.
Aforesaid semiconductor packaging structure, wherein the material of the described supporting part can be selected from gold, nickel or copper etc..
Aforesaid semiconductor packaging structure, wherein the material at the described junction surface can be selected from gold, nickel or copper etc..
Aforesaid semiconductor packaging structure, wherein the material of the described Underbump metallization layer can selected from titanium/copper,
Titanium tungsten/copper or titanium tungsten/gold etc..
The present invention has clear advantage and beneficial effect compared with prior art.From above technical scheme, be up to
To above-mentioned purpose, the invention provides a kind of semiconductor technology, which comprises the steps of：A carrier is provided, the carrier has
Surface and the metal level on the surface is formed at, the metal level has multiple substrate zones and multiple outsides on the outside of substrate zone
Area；The first photoresist layer is formed in the metal level, first photoresist layer has multiple first openings；Form multiple supporting parts to exist
First opening；First photoresist layer is removed to manifest the supporting part, respectively the supporting part has loading end, and respectively this holds
Section has the firstth area and the secondth area；The second photoresist layer is formed in the metal level, and is held described in second photoresist layer covering
Load portion, second photoresist layer has multiple second openings and second opening appears firstth area of the loading end；
Multiple junction surfaces are formed in the described second opening, and the junction surface covers firstth area of the loading end, so as to respectively should
The junction surface connection respectively supporting part and formation button-type projection (snap bump)；Second photoresist layer is removed to manifest
State button-type projection；The LHA of the metal level is removed, so that the substrate zone of the metal level is formed under multiple projections
Metal level.
By above-mentioned technical proposal, semiconductor technology of the present invention, semiconductor structure and its packaging structure at least have following
Advantage and beneficial effect：As the button-type projection has the supporting part and a little junction surfaces, therefore when being combined with substrate, base
Solder on plate can be carried and is limited on the supporting part, prevent solder overflow from causing electrically to neighbouring button-type projection
The situation of failure.
In sum, semiconductor technology of the present invention, which includes one carrier of offer, and the carrier has metal level, the metal
Layer has multiple substrate zones and multiple LHAs；Form the first photoresist layer；Form multiple supporting parts；Remove first photoresist
To manifest the supporting part, respectively the supporting part has loading end to layer, and respectively the loading end has the firstth area and the secondth area；Form the
Two photoresist layers, second photoresist layer appear firstth area of the loading end；Form multiple junction surfaces, and the engagement
Portion covers firstth area of the loading end, so that respectively the junction surface connects the respectively supporting part and forms button-type projection
(snap bump)；Remove second photoresist layer to manifest the button-type projection；Remove the outside of the metal level
Area, so that the substrate zone forms multiple Underbump metallization layers.The present invention is a significant progress in technology, and has obvious
Good effect, is really new and innovative, progressive, practical new design.
Described above is only the general introduction of technical solution of the present invention, in order to better understand the technological means of the present invention,
And can be practiced according to the content of description, and in order to allow the above and other objects of the present invention, feature and advantage can
Become apparent, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, describe in detail as follows.
Description of the drawings
Fig. 1：According to first preferred embodiment of the present invention, a kind of flow chart of semiconductor technology.
Fig. 2A to Fig. 2 H：According to first preferred embodiment of the present invention, the schematic cross-section of the semiconductor technology.
Fig. 3：According to second preferred embodiment of the present invention, the schematic cross-section of another kind of semiconductor structure.
Fig. 4：According to the 3rd preferred embodiment of the present invention, the schematic cross-section of another kind of semiconductor structure.
Fig. 5：According to first preferred embodiment of the present invention, a kind of schematic cross-section of semiconductor package.
10:A carrier is provided, the carrier has surface and is formed at the metal level on the surface
11:The first photoresist layer is formed in the metal level
12:Form multiple supporting parts
13:Remove first photoresist layer to manifest the supporting part
14:The second photoresist layer is formed in the metal level
15:Form multiple junction surfaces
16:Remove second photoresist layer
17:Remove the metal level
100:Semiconductor structure
110:Carrier 111:Surface
112:1 12a of Underbump metallization layer:Ring wall
120:Button-type projection 121:Supporting part
121’:First bearing bed 121 "：Second bearing bed
121a：Loading end 121b：Firstth area
121c：Second area 122：Junction surface
130：Gold plated Layer 200：Semiconductor package
210：Substrate 211：Connecting element
211a：Lateral wall 212：Solder
213：Becket A：Metal level
A1：Substrate zone A2：LHA
H1：First thickness H2：Second thickness
O1：First opens O2：Second opening
P1：First photoresist layer P2：Second photoresist layer
Specific embodiment
Further to illustrate the present invention to reach technological means and effect that predetermined goal of the invention is taken, below in conjunction with
Accompanying drawing and preferred embodiment, to according to its concrete reality of semiconductor technology proposed by the present invention, semiconductor structure and its packaging structure
Mode, structure, feature and its effect are applied, is described in detail as after.
Fig. 1 and Fig. 2A to Fig. 2 H is referred to, its presently preferred embodiments of the present invention, a kind of semiconductor technology include following step
Suddenly：First, refer to Fig. 1 and Fig. 2A, there is provided a carrier 110, the carrier 110 has surface 111 and is formed at the surface 111
Metal layer A, the metal layer A has multiple substrate zone A1 and multiple LHA A2 on the outside of substrate zone A1；Then, please join
Fig. 1 and Fig. 2 B being read, the first photoresist layer P1 being formed in the metal layer A, first photoresist layer P1 has multiple first opening O1；
Afterwards, Fig. 1 and Fig. 2 C are referred to, and multiple supporting parts 121 are formed in the described first opening O1, the material energy of the supporting part 121
It is enough to be selected from gold, nickel or copper etc.；Then, Fig. 1 and Fig. 2 D are referred to, removes the first photoresist layer P1 to manifest the carrying
Portion 121, respectively, with loading end 121a, respectively loading end 121a is with the first area 121b and the second area 121c for the supporting part 121；It
Afterwards, Fig. 1 and Fig. 2 E are referred to, the second photoresist layer P2 is formed in the metal layer A, and hold described in second photoresist layer P2 coverings
Load portion 121, second photoresist layer P2 have multiple second to open O2 and described second open the institute that O2 appears the loading end 121a
State the first area 121b；Then, Fig. 1 and Fig. 2 F are referred to, and are formed multiple junction surfaces 122 and O2, and the engagement are opened described second
Portion 122 covers the firstth area 121b of the loading end 121a so that respectively the junction surface 122 connect the respectively supporting part 121 and
Button-type projection (snap bump) 120 is formed, the material at the junction surface 122 can be selected from gold, nickel or copper etc., wherein institute
The material for stating supporting part 121 and the junction surface 122 can be identical or be differed；Afterwards, Fig. 1 and Fig. 2 G are referred to, remove this
To manifest the button-type projection 120, in the present embodiment, respectively the supporting part 121 has first thickness to two photoresist layer P2
H1, respectively the junction surface 122 have second thickness H2, second thickness H2 be more than first thickness H1；Finally, refer to Fig. 1 and
Fig. 2 H, remove the LHA A2 of the metal layer A, so that the substrate zone A1 of the metal layer A forms gold under multiple projections
Category layer 112 to form semiconductor structure 100, the material of the Underbump metallization layer 112 can selected from titanium/copper, titanium tungsten/copper or
Titanium tungsten/gold etc..
Referring again to Fig. 2 H, which is a kind of semiconductor structure 100 of first embodiment of the invention, the semiconductor structure 100
Including at least having a carrier 110 and a multiple button-type projections (snap bump) 120, the carrier 110 have surface 111 and
Multiple Underbump metallization layers 112 for being formed at the surface 111, the button-type projection 120 are formed at the Underbump metallization layer
On 112, respectively the button-type projection 120 has supporting part 121 and connects the junction surface 122 of the supporting part 121, respectively the supporting part
121 have loading end 121a, and respectively loading end 121a has the first area 121b and the second area 121c, and respectively the junction surface 122 covers
Each firstth area 121b of loading end 121a.As the button-type projection 120 has the supporting part 121 and a little junction surfaces
122, therefore when being combined with substrate, the solder on substrate can be carried and is limited on the supporting part 121, prevent solder overflow
Cause the situation of electrical property failure to neighbouring button-type projection 120.
Separately, Fig. 3 is referred to, which is a kind of semiconductor structure 100 of second embodiment of the invention, the semiconductor structure 100
Including at least having a carrier 110 and multiple button-type projections (snap bump) 120, second embodiment and first embodiment
Different places are that respectively the supporting part 121 includes the first bearing bed 121 ' and the second bearing bed 121 ", which is forming multiple carryings
Portion 121 is initially formed respectively first bearing bed 121 ' in the step of described first opens O1, afterwards in respectively first bearing bed 121 '
Upper each second bearing bed 121 of formation ", in the present embodiment, each second bearing bed 121 " with respectively loading end 121a.
Then, Fig. 4 is referred to, which is a kind of semiconductor structure 100 of third embodiment of the invention, the semiconductor structure
100 including at least having a carrier 110, multiple button-type projections 120 and Gold plated Layer 130, wherein 3rd embodiment and first
It is that the semiconductor structure 100 includes the Gold plated Layer 130 at embodiment difference, it is convex that the Gold plated Layer 130 coats the respectively button-type
Block 120, and in the present embodiment, respectively the Underbump metallization layer 112 has ring wall 112a, the Gold plated Layer 130 also coats the ring
Wall 112a is preventing the button-type projection 120 and the Underbump metallization layer 112 from aoxidizing or making moist.
Additionally, referring to Fig. 5, which applies a kind of semiconductor package 200 that first embodiment of the invention is formed, its
Include a semiconductor structure 100 and a substrate 210, the semiconductor structure 100 includes a carrier 110 and multiple
Button-type projection 120, the carrier 110 have surface 111 and multiple Underbump metallization layers 112 for being formed at the surface 111, described
Button-type projection 120 is formed on the Underbump metallization layer 112, and respectively the button-type projection 120 has supporting part 121 and connection
The junction surface 122 of the supporting part 121, respectively, with loading end 121a, respectively loading end 121a is with the firstth area for the supporting part 121
121b and the second area 121c, respectively the junction surface 122 cover firstth area 121b of respectively loading end 121a, the substrate 210 has
Multiple connecting elements 211, multiple solders 212 and multiple beckets 213, respectively the connecting element 211 have lateral wall 211a, respectively should
Solder 212 is formed in the respectively connecting element 211, and respectively the becket 213 coats respectively lateral wall 211a, the becket 213
Material be gold, the connecting element 211 is incorporated into the junction surface 122 of the button-type projection 120, the solder 212
Coat the junction surface 122 and the solder 212 connects the supporting part 121 and the connecting element 211, in the present embodiment
In, the solder 212 is carried and is limited in the secondth area 121c of the loading end 121a.
The above, is only presently preferred embodiments of the present invention, not makees any pro forma restriction to the present invention, though
So the present invention is disclosed above with preferred embodiment, but is not limited to the present invention, any to be familiar with this professional technology people
Member, in the range of without departing from technical solution of the present invention, when making a little change or modification using the technology contents of the disclosure above
For the Equivalent embodiments of equivalent variations, as long as being without departing from technical solution of the present invention content, according to the technical spirit pair of the present invention
Any simple modification, equivalent variations and modification that above example is made, still fall within the range of technical solution of the present invention.
Claims (6)
1. a kind of semiconductor technology, it is characterised in which includes at least the following steps：
A carrier is provided, the carrier has surface and is formed at the metal level on the surface, and the metal level has multiple substrate zones
And multiple LHAs on the outside of substrate zone；
The first photoresist layer is formed in the metal level, first photoresist layer has multiple first openings；
Multiple supporting parts are formed in the described first opening；
First photoresist layer is removed to manifest the supporting part, respectively the supporting part has loading end, and respectively the loading end has
Firstth area and the secondth area；
The second photoresist layer is formed in the metal level, and second photoresist layer covers the supporting part, second photoresist layer
With the multiple second openings and second opening appears firstth area of the loading end；
Multiple junction surfaces are formed in the described second opening, and the junction surface covers firstth area of the loading end, so that
Respectively the junction surface connects the respectively supporting part and forms button-type projection；
Remove second photoresist layer to manifest the button-type projection；And
The LHA of the metal level is removed, so that the substrate zone of the metal level forms multiple Underbump metallization layers.
2. semiconductor technology as claimed in claim 1, it is characterised in that respectively the supporting part has first thickness, respectively the junction surface
With second thickness, the second thickness is more than the first thickness.
3. semiconductor technology as claimed in claim 1, it is characterised in that respectively the supporting part includes the first bearing bed and second
Bearing bed.
4. semiconductor technology as claimed in claim 1, it is characterised in that the material of the supporting part is selected from gold, nickel or copper.
5. semiconductor technology as claimed in claim 1, it is characterised in that the material at the junction surface is selected from gold, nickel or copper.
6. semiconductor technology as claimed in claim 1, it is characterised in that the material of the Underbump metallization layer selected from titanium/
Copper, titanium tungsten/copper or titanium tungsten/gold.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210231782.0A CN103531491B (en) | 2012-07-05 | 2012-07-05 | Semiconductor technology, semiconductor structure and package structure thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210231782.0A CN103531491B (en) | 2012-07-05 | 2012-07-05 | Semiconductor technology, semiconductor structure and package structure thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103531491A CN103531491A (en) | 2014-01-22 |
| CN103531491B true CN103531491B (en) | 2017-04-12 |
Family
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| Application Number | Title | Priority Date | Filing Date |
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| CN201210231782.0A Active CN103531491B (en) | 2012-07-05 | 2012-07-05 | Semiconductor technology, semiconductor structure and package structure thereof |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5937320A (en) * | 1998-04-08 | 1999-08-10 | International Business Machines Corporation | Barrier layers for electroplated SnPb eutectic solder joints |
| CN1689150A (en) * | 2002-10-09 | 2005-10-26 | 飞思卡尔半导体公司 | Method for eliminating voiding in plated solder |
| CN202758871U (en) * | 2012-07-05 | 2013-02-27 | 颀邦科技股份有限公司 | Semiconductor structure and packaging construction |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050285116A1 (en) * | 2004-06-29 | 2005-12-29 | Yongqian Wang | Electronic assembly with carbon nanotube contact formations or interconnections |
| KR20110083969A (en) * | 2010-01-15 | 2011-07-21 | 삼성전자주식회사 | Semiconductor package and method of forming the same |
-
2012
- 2012-07-05 CN CN201210231782.0A patent/CN103531491B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5937320A (en) * | 1998-04-08 | 1999-08-10 | International Business Machines Corporation | Barrier layers for electroplated SnPb eutectic solder joints |
| CN1689150A (en) * | 2002-10-09 | 2005-10-26 | 飞思卡尔半导体公司 | Method for eliminating voiding in plated solder |
| CN202758871U (en) * | 2012-07-05 | 2013-02-27 | 颀邦科技股份有限公司 | Semiconductor structure and packaging construction |
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| CN103531491A (en) | 2014-01-22 |
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