CN103530484A - Device parameter optimization method of integrated circuit - Google Patents

Abstract

The invention provides a device parameter optimization method of an integrated circuit, which comprises the following steps of A, extracting a parasitic parameter initial value of the integrated circuit; B. constructing a first function according to the initial value of the device parameter and the initial value of the parasitic parameter, wherein the first function represents the relationship between the value of the parasitic parameter and the value of the device parameter; C. determining a circuit parameter of the integrated circuit according to the parasitic parameter value and the device parameter value, judging whether the circuit parameter meets a preset requirement, and if not, adjusting the device parameter value; D. and C, obtaining a parasitic parameter calculation value according to the adjusted device parameter value and the first function, and returning to the step C. The method for optimizing the device parameters of the integrated circuit provided by the invention avoids the defects that a software tool needs to be repeatedly called for extracting parasitic parameters and the physical layout needs to be adjusted for multiple times in the prior art, improves the optimization efficiency of the device parameters of the integrated circuit, and ensures that the optimization automation of the device parameters of the integrated circuit is easy to realize.

Description

A kind of device parameters optimization method of integrated circuit

Technical field

The present invention relates to integrated circuit (IC) design technical field, relate in particular to a kind of device parameters optimization method of integrated circuit.

Background technology

The device parameters optimization of integrated circuit is an important and time-consuming stage in design flow of integrated circuit, the final actual electric property of integrated circuit not only depends on the device parameters value of integrated circuit, also depends on ghost effect, the ghost effect between device of device itself, the ghost effect between ghost effect, the ghost effect between line and line and the device of line itself.

At present, the device parameters optimization method flow process of integrated circuit as shown in Figure 1.Wherein, the action need of the parasitic parameter of step S11 extraction integrated circuit is in current physical layout, adopt existing Software tool, call complicated Finite Element Method, Element BEM or the calculating of multipole point methods and obtain parasitic parameter, this step is because computing method complexity can take the longer time.And in the device parameters optimizing process of integrated circuit, the fine setting number of times of device parameters is thousands of, even hundreds thousand of more than.In so many number of times, call existing Software tool and extract parasitic parameter and can expend for a long time, cause the device parameters of integrated circuit to optimize robotization and be difficult to realize.

In addition, in the device parameters optimization method of existing integrated circuit, in order to obtain device parameters optimum results accurately, need to be when evaluating the quantitative result of device parameters fine setting each time, accurately consider to adjust circuit design after device parameter value physical layout on ghost effect, so device parameters value of every adjustment, need to be adjusted accordingly to physical layout (step S14 as shown in Figure 1).Repeated multiple times like this adjustment physical layout also can expend long-time, causes the device parameters optimization robotization of integrated circuit to be difficult to realize.

Summary of the invention

In view of this, the invention provides a kind of device parameters optimization method of integrated circuit, be intended to solve obtaining because depending on physical layout and the parasitic parameter extracting tool long device parameters that causes integrated circuit consuming time of parasitic parameter in the device parameters optimizing process of integrated circuit and optimize robotization and be difficult to the problem realizing.

In order to address the above problem, the present invention adopts following technical scheme:

A device parameters optimization method, comprise,

The parasitic parameter initial value of A, extraction integrated circuit;

B, according to device parameters initial value and described parasitic parameter initial value, build the first function, the relation between described the first function representation parasitic parameter value and device parameters value;

C, according to parasitic parameter value and device parameters value, determine the circuit parameter of described integrated circuit, and judge whether described circuit parameter meets pre-provisioning request, if not, adjust described device parameters value;

Device parameters value and described the first function after D, foundation are adjusted obtain parasitic parameter calculated value, return to step C;

Wherein, described parasitic parameter value is described parasitic parameter initial value or described parasitic parameter calculated value; Described device parameters value is the device parameters value after described device parameters initial value or described adjustment.

Further, described step B specifically comprises:

Acquisition device housing size initial value, described device housing is the external figure frame of each device of comprising of integrated circuit;

According to described device housing size initial value and described device parameters initial value, build the second function, the relation between described the second function representation device housing size value and described device parameters value; Wherein, described device housing size value comprises device housing size initial value;

According to described the second function and described device parameters value, obtain described device housing size value;

According to described device housing size value and described parasitic parameter initial value, build described the first function.

Further, described parasitic parameter comprises dead resistance, and described foundation described device housing size value and described parasitic parameter initial value, build described the first function, specifically comprise,

Any interconnection line in selected integrated circuit, described interconnection line comprises the straight-line segment of some sections of first directions and the straight-line segment of some sections of second directions, wherein, first direction and second direction are orthogonal;

Determine and each section of all devices that described straight-line segment is relevant;

Determine the length contribution initial value of each device relevant to described each section of described straight-line segment to straight-line segment corresponding thereto;

According to described each device relevant to described each section of described straight-line segment to the length contribution initial value of straight-line segment corresponding thereto and the housing size initial value of this related device, build the 3rd function, each device relevant to described each section of described straight-line segment of described the 3rd function representation is to the relation between the length contribution of straight-line segment corresponding thereto and this device housing size value; Wherein, described length contribution comprises length contribution initial value;

According to described the 3rd function and all devices relevant to described straight-line segment, determine the length contribution summation of all devices relevant to this straight-line segment to this straight-line segment;

The all straight-line segments that length contribution summation and the described interconnection line of this straight-line segment comprised according to all devices relevant to every section of straight-line segment, build the 4th function, the relation between the housing size of all related devices that all straight-line segments that described the 4th function representation interconnect length comprises with it are corresponding;

According to described the 4th function and all skip floor via holes, to the contribution of the dead resistance of described interconnection line and described parasitic parameter initial value, build the first function that is of a size of parameter with described device housing.

Further, the minimum boundary rectangle that the external figure of described device is described device.

Further, described device housing size value comprises the housing size value XL of first direction and the housing size value YL of second direction, and described the second function is:

$\mathrm{XL}=\underset{i=1}{\overset{n-1}{\mathrm{\Σ}}}{c}_{i,i+1}\×p_i\×p_{i+1}+\underset{i=1}{\overset{n}{\mathrm{\Σ}}}{c}_i\×p_i+c_0;$

$\mathrm{YL}=\underset{i=1}{\overset{n-1}{\mathrm{\Σ}}}{k}_{i,i+1}\×p_i\×p_{i+1}+\underset{i=1}{\overset{n}{\mathrm{\Σ}}}{k}_i\×p_i+k_0;$

Wherein, p _ii device parameters, the number that n is device parameters, c _{i, i+1}, c _i, c ₀housing size value XL and device parameters p for described device first direction _ibetween the coefficient of the second function, k _i, k _{i, i+1}, k ₀housing size value YL and device parameters p for described device second direction _ibetween the coefficient of the second function.

Further, described definite and each section of all devices that described straight-line segment is relevant, comprise,

According to all endpoint locations of described interconnection line, determine the external figure of described interconnection line;

Judge whether intersecting of the first device housing in the external graphics field of described straight-line segment and described interconnection line at least on one side, if so, determine that described the first device is the device relevant to described straight-line segment, judge whether described straight-line segment comprises at least one section of sub-line segment being positioned at outside device housing, and the length of described sub-line segment is not less than device in the external graphics field of the described interconnection line minimum housing size value in the direction of described straight-line segment place, if, by the both sides translation to sub-line segment on perpendicular to described sub-line segment length direction of described sub-line segment, then judge whether intersecting of the second device housing in the external graphics field of described sub-line segment and described interconnection line at least on one side, and whether judge between described the second device and described sub-line segment without other devices, if, determine that described the second device is related device.

Further, describedly determine that each device relevant to described each section of described straight-line segment contributes initial value to the length of straight-line segment corresponding thereto, comprise,

When straight-line segment that described straight-line segment is first direction, judge the intersecting or whether intersect with the extended line at least on one side of housing in the second direction of related device of housing of the straight-line segment of described first direction and the second direction of related device at least on one side whether, if so, determine the housing size value XL that described related device is its first direction to the length contribution initial value of straight-line segment;

When straight-line segment that described straight-line segment is second direction, judge the intersecting or whether intersect with the extended line at least on one side of housing on the first direction of related device of housing of the straight-line segment of described second direction and the first direction of related device at least on one side whether, if so, described related device is the housing size value YL of its second direction to the length contribution of straight-line segment.

Further, when straight-line segment that straight-line segment is first direction, described the 3rd function is:

L _x,i,j＝k _x,j,1×XL _j+k _x,j,0；

Wherein, L _{x, i, j}represent the length contribution of related device j to the straight-line segment i of first direction, XL _jrepresent related device j housing size value in a first direction, k _{x, j, 1}represent the length contribution L of related device j to the straight-line segment i on first direction _{x, i, j}housing size value XL with the first direction of device j _jthe Monomial coefficient of funtcional relationship, k _{x, j, 0}represent the length contribution L of related device j to the straight-line segment i on first direction _{x, i, j}with the housing size value XL on the first direction of device j _jthe zero degree item coefficient of funtcional relationship;

When straight-line segment that straight-line segment is second direction, described the 3rd function is:

L _y,i,j＝k _y,j,1×YL _j+k _y,j,0；

Wherein, L _{y, i, j}represent the length contribution of related device j to the straight-line segment i of second direction, YL _jrepresent the housing size value of related device j in second direction, k _{y, j, 1}represent the length contribution L of related device j to the straight-line segment i in second direction _{y, i, j}housing size value YL with the second direction of device j _jthe Monomial coefficient of funtcional relationship, k _{y, j, 0}represent the length contribution L of related device j to the straight-line segment i in second direction _{y, i, j}with the housing size value YL in the second direction of device j _jthe zero degree item coefficient of funtcional relationship.

Further, set described interconnection line and comprise the straight-line segment of n section first direction and the straight-line segment of l section second direction, h device is relevant to one section of straight-line segment of first direction, and m device is relevant to one section of straight-line segment of second direction, and described the 4th function, is specially:

$L_{\mathrm{xy}}=\underset{i=1}{\overset{n}{\mathrm{\Σ}}}\left(\underset{j=1}{\overset{h}{\mathrm{\Σ}}}(k_{x,j,1}\×{\mathrm{XL}}_j+k_{x,j,0})\right)+\underset{i=1}{\overset{l}{\mathrm{\Σ}}}\left(\underset{j=1}{\overset{m}{\mathrm{\Σ}}}(k_{y,j,1}\×{\mathrm{YL}}_j+k_{y,j,o})\right).$

Further, described the first function, is specially:

$R_{\mathrm{wires}}=k\×[\underset{i=1}{\overset{n}{\mathrm{\Σ}}}\left(\underset{j=1}{\overset{h}{\mathrm{\Σ}}}(k_{x,j,1}\×{\mathrm{XL}}_j+k_{x,j,0})\right)+\underset{i=1}{\overset{l}{\mathrm{\Σ}}}\left(\underset{j=1}{\overset{m}{\mathrm{\Σ}}}(k_{y,j,1}\×{\mathrm{YL}}_j+k_{y,j,o})\right)]+\underset{i=1}{\overset{n}{\mathrm{\Σ}}}(R_{\mathrm{via},i,i+1}/N_{\mathrm{vias},i})$

；

Wherein, k is the coefficient of the first function, R _{via, i, i+1}for skip floor i, the resistance of a via hole of i+1 layer, N _{vias, i}for skip floor i, the mistake hole count on i+1 layer, n is total n skip floor on described interconnection line.

Further, the acquisition methods of described all skip floor via holes to the contribution of the dead resistance of described interconnection line, comprises,

Select any skip floor, obtain the number of via hole and the resistance of a via hole between described skip floor of described skip floor;

According to the resistance of the number of the via hole of described skip floor and via hole, obtain the contribution of all via holes of all described skip floors to the dead resistance of described interconnection line;

Contribution according to skip floor described in each to the dead resistance of interconnection line, obtains the contribution to the dead resistance of described interconnection line of all skip floors on described interconnection line.

Further, described step C, also comprises, if so, finishes the device parameters optimization of integrated circuit.

The first function that the present invention has built relation between device parameters value and parasitic parameter value according to device parameters initial value and the parasitic parameter initial value of integrated circuit.After device parameters in integrated circuit is adjusted, according to the first function building, can directly estimate the parasitic parameter calculated value in the integrated circuit after being adjusted.The device parameters optimization method of this integrated circuit only needs to call the Software tool that once extracts parasitic parameter and extracts parasitic parameter initial value, the parasitic parameter value of adjusting the integrated circuit after device parameter value can obtain by the first function estimation building, and the obtaining of parasitic parameter value of the integrated circuit after adjustment device parameters do not rely on physical layout.So, the device parameters optimization method of integrated circuit provided by the invention has avoided in prior art, needing repeatedly repeatedly to call the defect that Software tool extracts parasitic parameter and repeatedly does the adjustment of physical layout, improved the optimization efficiency of the device parameters of integrated circuit, the optimization robotization of the device parameters of integrated circuit is easily realized.

Accompanying drawing explanation

In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.

Fig. 1 is the device parameters optimization method process flow diagram of integrated circuit of the prior art;

Fig. 2 is the device parameters optimization method process flow diagram of the integrated circuit of the embodiment of the present invention;

Fig. 3 is that the device parameters value of take of the embodiment of the present invention builds the method flow diagram of the first function as parameter;

Fig. 4 is that the device housing size value of take of the embodiment of the present invention builds the method flow diagram of the first function as parameter;

Fig. 5 is the structural representation of the integrated circuit of the embodiment of the present invention.

Embodiment

For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.

A lot of details have been set forth in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here and implement, those skilled in the art can do similar popularization without prejudice to intension of the present invention in the situation that, so the present invention is not subject to the restriction of following public specific embodiment.

Referring to Fig. 2.Fig. 2 is the device parameters optimization method process flow diagram of the integrated circuit of the embodiment of the present invention.The device parameters optimization method of this integrated circuit, comprises the following steps:

The parasitic parameter initial value of S21, extraction integrated circuit:

Integrated circuit comprises many devices, and each device all has corresponding device parameters.It should be noted that; device parameters described here mainly refers to the geometric parameter of each device and the parameter of other control device physical layouts composition of built-up circuit; for example can be long for grid width, the grid of MOSFET, can also control parameter or extraction location control parameter etc. for finger number, protection ring.Device parameters described above has determined the parasitic parameter of integrated circuit.The extraction of parasitic parameter can complete by parasitic parameter extraction Software tool well known in the art.

This step adopts the Software tool of extraction parasitic parameter well known in the art to extract the parasitic parameter initial value of current integrated circuit particularly.This step is the routine operation of this area, and those skilled in the art are known at an easy rate, for the sake of brevity, at this, are not describing in detail.

S22, according to device parameters initial value and parasitic parameter initial value, build the first function:

Each device in current integrated circuit has corresponding device parameters initial value, has been determined the parasitic parameter initial value of integrated circuit by these device parameters initial values.According to device parameters initial value and the parasitic parameter initial value in current integrated circuit, build the first funtcional relationship representing between parasitic parameter value and device parameters value.Particularly, the cloudy variable that the parasitic parameter value of take is the first function, device parameters value is the first argument of function, builds the first function.Device parameters value described here not only can comprise the device parameters initial value in current integrated circuit, can also comprise the device parameters initial value after adjustment.

More specifically, in conjunction with Fig. 3, according to device parameters initial value and parasitic parameter initial value, build the first function, comprise the following steps:

S2201, acquisition device housing size initial value:

First, it should be noted that, the device housing described in the present embodiment refers to the frame of external figure of each device of integrated circuit.For easy, this external figure is preferably the minimum boundary rectangle of device.

The present embodiment be take minimum boundary rectangle and is described as example.When the external figure of device is minimum boundary rectangle, the housing of device comprises the housing on mutually perpendicular both direction, is respectively the housing of first direction and the housing of second direction, that is to say, the device housing of rectangle comprises length sides and width edge.Correspondingly, device housing size comprises the device housing size XL of first direction and the device housing size YL of second direction.

When designing integrated circuit, in order to obtain the utilization factor of good circuit performance and raising chip area, device is generally designed to rectangle.So, when carrying out integrated circuit (IC) design, can learn the device housing size initial value of integrated circuit.The housing size initial value of each device is included in the device housing size initial value of first direction and the device housing size initial value of second direction.

S2202, according to device housing size initial value and device parameters initial value, build the second function:

Because device housing size initial value and device parameters initial value are known quantity, according to this initial value, build the second function that represents device housing size value and device parameters value relation.Device housing size value described here not only can comprise device housing initial value, can also comprise and adjust corresponding device housing size value after integrated circuit (IC)-components parameter.

One of them device of setting integrated circuit has n device parameters, is respectively p ₁, p ₂..., p _n, the second function of the housing size XL on the first direction of device is f _xL, the second function of the housing size YL in the second direction of device is f _yL,

$\mathrm{XL}=f_{\mathrm{XL}}(p_1,{\mathrm{<figure-callout\; id="2"\; label="p"\; filenames="HDA0000407736610000022.png"\; state="\{\{state\}\}">p</figure-callout>}}_2,...,p_n)$

$=\underset{i=1}{\overset{n-1}{\mathrm{\&Sigma;}}}{c}_{i,i+1}\&times;p_i\&times;p_{i+1}+\underset{i=1}{\overset{n}{\mathrm{\&Sigma;}}}{c}_i\&times;p_i+c_0;$

$={\mathrm{<figure-callout\; id="2"\; label="c"\; filenames="HDA0000407736610000022.png"\; state="\{\{state\}\}">c</figure-callout>}}_{\mathrm{1,2}}\&times;p_1\&times;{\mathrm{<figure-callout\; id="2"\; label="p"\; filenames="HDA0000407736610000022.png"\; state="\{\{state\}\}">p</figure-callout>}}_2+...+c_{n-1,n}\&times;p_{n-1}\&times;p_n+c_1\&times;p_1+{\mathrm{<figure-callout\; id="2"\; label="c"\; filenames="HDA0000407736610000022.png"\; state="\{\{state\}\}">c</figure-callout>}}_2\&times;{\mathrm{<figure-callout\; id="2"\; label="p"\; filenames="HDA0000407736610000022.png"\; state="\{\{state\}\}">p</figure-callout>}}_2+...+c_n\&times;p_n+c_0$

$\mathrm{YL}=f_{\mathrm{YL}}(p_1,{\mathrm{<figure-callout\; id="2"\; label="p"\; filenames="HDA0000407736610000022.png"\; state="\{\{state\}\}">p</figure-callout>}}_2,...,p_n)$

$=\underset{i=1}{\overset{n-1}{\mathrm{\&Sigma;}}}{k}_{i,i+1}\&times;p_i\&times;p_{i+1}+\underset{i=1}{\overset{n}{\mathrm{\&Sigma;}}}{k}_i\&times;p_i+k_0;$

$={\mathrm{<figure-callout\; id="2"\; label="k"\; filenames="HDA0000407736610000022.png"\; state="\{\{state\}\}">k</figure-callout>}}_{\mathrm{1,2}}\&times;p_1\&times;{\mathrm{<figure-callout\; id="2"\; label="p"\; filenames="HDA0000407736610000022.png"\; state="\{\{state\}\}">p</figure-callout>}}_2+...+k_{n-1,n}\&times;p_{n-1}\&times;p_n+k_1\&times;p_1+{\mathrm{<figure-callout\; id="2"\; label="k"\; filenames="HDA0000407736610000022.png"\; state="\{\{state\}\}">k</figure-callout>}}_2\&times;{\mathrm{<figure-callout\; id="2"\; label="p"\; filenames="HDA0000407736610000022.png"\; state="\{\{state\}\}">p</figure-callout>}}_2+...+k_n\&times;p_n+k_0$

Wherein, p _ii device parameters, the number that n is device parameters, c _{i, i+1}, c _i, c ₀for the housing size XL of described device first direction and the coefficient of the second function between device parameters, k _i, k _{i, i+1}, k ₀for the housing size YL of described device second direction and the coefficient of the second function between device parameters.

Above-mentioned function f _xLand f _yLbuilding process as follows:

First, the PCell of this device of take is template, in the element layout under producing different components parameter value, and the housing size value YL of the housing size value XL of a series of first direction of acquisition device and second direction;

Secondly, according to the housing size value XL in a first direction of the device under these different components parameter values, to f _xLcarry out curve fitting, obtain coefficient c _1,1, c _1,2..., c _{n-1, n}, c ₁, c ₂..., c _n, c ₀value, and then obtain function f _xL;

In like manner, the housing size value YL according to the device under these different components parameter values in second direction, to f _yLcarry out curve fitting, obtain coefficient k _1,1, k _1,2..., k _{n-1, n}, k ₁, k ₂..., k _n, k ₀value, obtain function f _yL.

S2203, foundation the second function and device parameters value, acquisition device housing size value:

Device parameters value is updated to the second function f _xLand f _yL, by calculating the second functional relation, can obtain first direction device housing size value XL that different components parameter value is corresponding and the device housing size value YL of second direction.

S2204, according to device housing size value and parasitic parameter initial value, build the first function:

The parasitic parameter initial value extracting according to step S21 and the device parameters value being calculated by the second function, build the first function with relation between device housing size value and parasitic parameter value.Due to, device housing size value calculates by the second function, and the second function is the relation between device parameters value and device housing size value, so basically, the first function is the relation between device parameters value and parasitic parameter value.

Parasitic parameter described in the present embodiment can comprise dead resistance, can also comprise stray capacitance or stray inductance.

When the parasitic parameter described in the present embodiment is dead resistance, step S2204, according to device housing size value and parasitic parameter initial value, builds the method for the first function, in conjunction with Fig. 4, specifically comprises the following steps:

Any interconnection line in S220401, selected integrated circuit:

Integrated circuit comprises some interconnection lines, and any interconnection line in selected this integrated circuit diagram is research object, and the dead resistance on this interconnection line is estimated.Obtaining of the dead resistance of other interconnection line is identical with the acquisition methods of the dead resistance of this interconnection line.

Generally, the interconnection line of integrated circuit is not a straight line, but comprises some sections of mutually perpendicular straight-line segments, and by skip floor via hole, is connected between each straight-line segment.That is to say, the straight-line segment described in the present embodiment does not comprise the skip floor via hole on interconnection line.

Set this interconnection line and comprise the straight-line segment of n section first direction and the straight-line segment of l section second direction.

S220402, definite and each section of all devices that described straight-line segment is relevant:

The method of determining all devices relevant to each section of described straight-line segment, specifically comprises the following steps:

I, according to all endpoint locations of described interconnection line, determine the minimum boundary rectangle of described interconnection line:

As mentioned above, interconnection line comprises some sections of mutually perpendicular straight-line segments.According to the end points of all mutually perpendicular straight-line segments, determine the minimum boundary rectangle of described interconnection line.

The minimum boundary rectangle of above-mentioned determined interconnection line is the preferred scheme of the present embodiment.In fact, the present embodiment can be determined a region that interconnection line can be included according to all endpoint locations of described interconnection line.This region can be the external figure of this interconnection line, as circumscribed circle, and boundary rectangle.But, if the area in this region is too large, in some and the incoherent device of interconnection line can being also contained in, so preferably make the minimum boundary rectangle of outer interconnection line, this minimum boundary rectangle can be included every part of interconnection line, can will get rid of beyond region with the incoherent device of this interconnection line again.

II, judge whether intersecting of the first device housing in the minimum circumscribed rectangular region of described straight-line segment and described interconnection line at least on one side, if so, determine that this first device is the device relevant to described straight-line segment, judge whether described straight-line segment comprises at least one section of sub-line segment being positioned at outside device housing, and the length of described sub-line segment is not less than minimum device in the minimum circumscribed rectangular region of the described interconnection line housing size in the direction of described straight-line segment place, if, by the both sides translation to sub-line segment on perpendicular to described sub-line segment length direction of described sub-line segment, then judge whether intersecting of the second device housing in the minimum circumscribed rectangular region of described sub-line segment and described interconnection line at least on one side, and between described the second device and described sub-line segment whether without other devices, if, determine that described the second device is the device relevant to described straight-line segment:

In order to be expressly understood how to confirm and each section of all devices that straight-line segment is relevant, refer to Fig. 5.Fig. 5 exemplifies the straight-line segment that straight-line segment is first direction, and has 16 devices (being respectively M1 to M16) in the minimum circumscribed rectangular region of the interconnection line under this straight-line segment.From this figure, find out, straight-line segment intersects with device M1, M2, M3 and M4 respectively, and definition device M1, M2, M3 and M4 are the first device, and device M1, M2, M3 and M4 are the device that this straight-line segment is relevant.

In addition, this straight-line segment comprises three sections of sub-line segments that are positioned at outside device housing, but the length of the first sub-line segment S1 and the second sub-line segment S2 is significantly less than the minimum housing size on the first direction of the device in this region, without this first sub-line segment S1 of translation and the second sub-line segment S2.Because the length of the 3rd sub-line segment S3 is greater than the minimum housing size on the first direction of the device in this region, so the 3rd sub-line segment S3 is being gone up to the both sides translation to sub-line segment perpendicular to described sub-line segment length direction (second direction), the 3rd sub-line segment S3 respectively with device M5, M6, M7 and M16's intersects at least on one side, then judge to the 3rd sub-line segment S3 respectively with device M5, M6, between M7 and M16, whether there is device, judgement draws the 3rd sub-line segment S3 and device M5, between M6 and M7, without device, exist, so, M5, M6 is the device relevant to this straight-line segment with M7, but there is device M5 between the 3rd sub-line segment S3 and device M16, so device M16 is not the device relevant to this straight-line segment, definition device M5, M6, M7 is the second device.

According to above-mentioned two steps, determine all devices relevant to this straight-line segment.The all devices relevant to this straight-line segment comprise the first device and the second device.In practical operation, determine that the execution sequence of the first device and the second device can exchange, the present embodiment is not construed as limiting its execution sequence.

According to said method, obtain all devices relevant to this straight-line segment, be respectively M1, M2, M3, M4, M5, M6 and M7.

When straight-line segment that straight-line segment is second direction, applicable equally said method, for for simplicity, does not repeat them here.

S220403, determine the length contribution initial value of each device relevant to every section of straight-line segment to straight-line segment corresponding thereto:

Particularly, when straight-line segment that straight-line segment is first direction, whether whether the housing that judges the second direction of the relative device of this straight-line segment intersect at least on one side or intersect with the extended line at least on one side of housing in the second direction of related device, if so, determine the housing size XL that this related device is its first direction to the length contribution initial value of straight-line segment.Visible in conjunction with Fig. 5, the frame of a second direction of this straight-line segment and device M1, M4 intersects, and the frame of two second directions of this straight-line segment and M2, M3 intersects, and the extended line in the second direction of this straight-line segment and its related device M5, M6, M7 intersects, so device M1, M2, M3, M4, M5, M6 and M7 are its housing size value XL of first direction separately to the length contribution initial value of this straight-line segment.

When straight-line segment that straight-line segment is second direction, judge the intersecting or whether intersect with the extended line at least on one side of housing in the second direction of its related device of housing of the first direction of this straight-line segment and its related device at least on one side whether, if so, determine the housing size value YL that length contribution initial value that this related device is this straight-line segment is its second direction.

S220404, build to represent that each device relevant with every section of straight-line segment is contributed the length of straight-line segment corresponding thereto and this device housing size value between the 3rd function:

Length contribution initial value and device housing size value according to each related device to straight-line segment corresponding thereto, build the 3rd function that represents relation between the length contribution of each related device straight-line segment corresponding thereto and the housing size value of this related device.

When straight-line segment that straight-line segment is first direction, between the contribution of the length of each related device straight-line segment corresponding thereto and the housing size value of its related device, the relational expression of the 3rd function of relation is:

L _x,i,j＝k _x,j,1×XL _j+k _x,j,0;

Wherein, L _{x, i, j}represent the length contribution of related device j to the straight-line segment i of first direction, XL _jrepresent related device j housing size in a first direction, k _{x, j, 1}represent the length contribution L of related device j to the straight-line segment i on first direction _{x, i, j}housing size XL with the first direction of device j _jthe Monomial coefficient of funtcional relationship, k _{x, j, 0}represent the length contribution L of related device j to the straight-line segment i on first direction _{x, i, j}with the housing size XL on the first direction of device j _jthe zero degree item coefficient of funtcional relationship.

When straight-line segment that straight-line segment is second direction, between the contribution of the length of each related device straight-line segment corresponding thereto and the housing size value of its related device, the relational expression of the 3rd function of relation is:

L _y,i,j＝k _y,j,1×YL _j+k _y,j,0;

Wherein, L _{y, i, j}represent the length contribution of related device j to the straight-line segment i of second direction, YL _jrepresent the housing size of related device j in second direction, k _{y, j, 1}represent the length contribution L of related device j to the straight-line segment i in second direction _{y, i, j}housing size YL with the second direction of device j _jthe Monomial coefficient of funtcional relationship, k _{y, j, 0}represent the length contribution L of related device j to the straight-line segment i in second direction _{y, i, j}with the housing size YL in the second direction of device j _jthe zero degree item coefficient of funtcional relationship.

S220405, the length contribution summation of definite all devices relevant to this straight-line segment to this straight-line segment:

According to representing the length contribution of each related device pair straight-line segment corresponding with it and the 3rd funtcional relationship between the housing size value of this device, when the housing size value of device is known, the length that can try to achieve this related device pair straight-line segment corresponding with it by this funtcional relationship is contributed, then all each device relevant to this straight-line segment summed up the length contribution of this straight-line segment, determine the length contribution summation of all devices relevant to this straight-line segment to this straight-line segment.

When straight-line segment i is the straight-line segment of first direction, suppose to have h related device relevant to this straight-line segment i, the length contribution summation L of all h the device relevant to this straight-line segment i to this straight-line segment i _x,iexpression formula as follows:

$L_{x,i}=\underset{j=1}{\overset{h}{\mathrm{\&Sigma;}}}(k_{x,j,1}\&times;{\mathrm{XL}}_j+k_{x,j,0});$

When straight-line segment i is the straight-line segment of second direction, suppose to have m related device relevant to this straight-line segment i, the length contribution summation L of all m the device relevant to this straight-line segment i to this straight-line segment i _y,iexpression formula as follows:

$L_{y,i}=\underset{j=1}{\overset{m}{\mathrm{\&Sigma;}}}(k_{y,j,1}\&times;{\mathrm{YL}}_j+k_{y,j,0}).$

It should be noted that, the number of the relative device of different straight-line segments is not necessarily identical.The related device number h of above-mentioned supposition or m are not fixing numerical value.For different straight-line segments, its h or m value may be different.Why doing above-mentioned supposition, is in order more clearly to write out function expression.

S220406, build to represent the 4th function of relation between the housing size value of all related devices that all straight-line segments that interconnect length comprises with it are corresponding:

Particularly, as mentioned above, this interconnection line comprises the straight-line segment of n section first direction and the straight-line segment of l section second direction, and the length of this interconnection line is the length contribution Ls of all related devices to the straight-line segment on all first directions _xwith the length contribution L of all related devices to the straight-line segment in all second directions _yadd and.According to described above, determine that the method for all devices relevant to every section of straight-line segment can learn, the device relevant to every section of straight-line segment may have a plurality of, and the number of the device relevant from different straight-line segments may be not identical yet.According to above-mentioned steps S220405, can learn that all devices relevant to every section of straight-line segment are to this length of straigh line contribution summation, then all related devices of all straight-line segments that comprise on this interconnection line are added the length contribution of its corresponding straight-line segment and, obtain the length of this interconnection line.So just built the 4th function of relation between the housing size value of all related devices that all straight-line segments that interconnect length comprises with it are corresponding.

Particularly, set described interconnection line and comprise the selected axial straight-line segment of coordinate system x of n section and the selected axial straight-line segment of coordinate system y of l section, h device is relevant to one section of straight-line segment of first direction, and m device is relevant to one section of straight-line segment of second direction, and the expression formula of the 4th function is as follows:

$L_{\mathrm{xy}}=L_x+L_y$

$=\underset{i=1}{\overset{n}{\mathrm{\&Sigma;}}}{L}_{x,i}+\underset{i=1}{\overset{l}{\mathrm{\&Sigma;}}}{L}_{y,i}.$

$=\underset{i=1}{\overset{n}{\mathrm{\&Sigma;}}}\left(\underset{j=1}{\overset{h}{\mathrm{\&Sigma;}}}(k_{x,j,1}\&times;{\mathrm{XL}}_j+k_{x,j,0})\right)+\underset{i=1}{\overset{l}{\mathrm{\&Sigma;}}}\left(\underset{j=1}{\overset{m}{\mathrm{\&Sigma;}}}(k_{y,j,1}\&times;{\mathrm{YL}}_j+k_{y,j,o})\right)$

S220407, structure are of a size of the first function of parameter with device housing:

Particularly, obtain in advance the contribution R of all skip floor via holes to the dead resistance of this interconnection line in integrated circuit _vias, the contribution R to the dead resistance of this interconnection line according to the 4th function and all skip floor via holes then _vias, and the dead resistance initial value of said extracted, build the first funtcional relationship between dead resistance and device housing size value.

$R_{\mathrm{wires}}=k\&times;[\underset{i=1}{\overset{n}{\mathrm{\&Sigma;}}}\left(\underset{j=1}{\overset{h}{\mathrm{\&Sigma;}}}(k_{x,j,1}\&times;{\mathrm{XL}}_j+k_{x,j,0})\right)+\underset{i=1}{\overset{l}{\mathrm{\&Sigma;}}}\left(\underset{j=1}{\overset{m}{\mathrm{\&Sigma;}}}(k_{y,j,1}\&times;{\mathrm{YL}}_j+k_{y,j,o})\right)]+\underset{i=1}{\overset{t}{\mathrm{\&Sigma;}}}(R_{\mathrm{via},i,i+1}/N_{\mathrm{vias},i})$

；

K is the coefficient of the first function, R _{via, i, i+1}for skip floor i, the resistance of a via hole of i+1 layer, N _{vias, i}for skip floor i, the mistake hole count on i+1 layer, t is total t skip floor on described interconnection line.

It should be noted that, obtain the contribution R of all skip floor via holes of any two terminal interconnection to the dead resistance of this interconnection line in integrated circuit _viasconcrete grammar as follows:

Select any skip floor, obtain the number of via hole and the resistance of a via hole on this skip floor of this skip floor:

Particularly, travel through interconnection line position between the via layer of this skip floor, determine the mistake hole count N of this skip floor _{vias, i}.The technological design packet providing according to integrated circuit manufacturer can obtain the resistance R of an interlevel via of each skip floor _{via, i, i+1}, as R _{via, 1,2}, R _{via, 2,3}deng.Wherein, R _{via, i, i+1}the resistance that represents the via hole between i layer and i+1 layer.

Due to the thickness of every one deck, to cross hole size etc. different, so the resistance of the single via hole between different skip floor is not identical yet.

According to the mistake number of perforations of this skip floor and the resistance of via hole, obtain the contribution to the dead resistance of this interconnection line of all via holes on all these skip floors:

It should be noted that, in integrated circuit diagram, between adjacent two layers, can realize and connecting by a via hole, in order to reduce resistance, increase reliability, conventionally adopt a plurality of via holes to realize and connect.Now, via hole between this skip floor is equivalent to the parallel connection of resistance, and now, the via hole of this skip floor is equivalent to the resistance after a plurality of via hole parallel connections the contribution of the dead resistance of interconnection line, so when realizing connection by a plurality of via holes between employing adjacent two layers, reduced the all-in resistance of via hole.

The resistance of a via hole on this skip floor obtaining according to above-mentioned steps is R _{via, i, i+1}, calculate the via hole obtain on this skip floor contribution R to the dead resistance of interconnection line _{vias, i},

R _vias,i＝R _via,i,i+1/N _vias,i。

According to each contribution of skip floor skip floor to the dead resistance of interconnection line, obtain the contribution to the dead resistance of this interconnection line of all skip floors on this interconnection line:

Contribution by cumulative single skip floor to interconnect resistance, obtains the resistance contribution R of all skip floors to it on this interconnection line _vias:

$R_{\mathrm{vias}}=\underset{i=1}{\overset{t}{\mathrm{\&Sigma;}}}{R}_{\mathrm{vias},i}.$

S23, according to described parasitic parameter value and described device parameters value, determine the circuit parameter of described integrated circuit:

Generally, under certain cloth graph topological structure, the device parameters value of integrated circuit has determined the parasitic parameter value of the device on integrated circuit, and device parameters value and parasitic parameter value determined the actual performance of circuit simultaneously, has determined circuit parameter.This circuit parameter can be for example the parameters such as enlargement factor, bandwidth.

The method the most accurately of determining circuit performance or circuit parameter is to carry out circuit simulation, but efficiency is lower.Another is exactly according to some circuit devcie parameters, parasitic parameter, and and circuit performance parameters between relation, set up macro model, according to macro model input circuit device parameters value and parasitic parameter value, directly calculate the performance parameter value of circuit.

S24, judge whether described circuit parameter meets pre-provisioning request, if not, execution step S25, if so, execution step S27:

Judge whether described circuit parameter meets pre-provisioning request, this pre-provisioning request is the design objective of setting before integrated circuit (IC) design, and as enlargement factor will reach 1000, bandwidth will reach 500MHz.If circuit parameter does not meet predetermined requirement, perform step S25; If circuit parameter meets pre-provisioning request, perform step S27.

S25, adjust described device parameters value:

Because circuit parameter does not meet pre-provisioning request, need to finely tune one or several device parameters values in circuit.

Described device parameters value after S26, foundation are adjusted and described the first function estimation obtain described parasitic parameter calculated value, return to step S23:

Device parameters value after adjusting is updated to the second function, can obtains corresponding device housing size value after the adjustment of device parameters value, the device housing size value then this being calculated is updated to the first function, calculates parasitic parameter calculated value.Then return to step S23, enter the optimization cyclic process of next device parameters.

The device parameters optimization of S27, end integrated circuit:

If circuit parameter meets pre-provisioning request, the device parameters Optimum Operation of integrated circuit finishes.

The first function that the present invention has built relation between device parameters value and parasitic parameter value according to device parameters initial value and the parasitic parameter initial value of integrated circuit.After device parameters in integrated circuit is adjusted, according to the first function building, can directly estimate the parasitic parameter calculated value in the integrated circuit after being adjusted.The device parameters optimization method of this integrated circuit only needs to call the Software tool that once extracts parasitic parameter and extracts parasitic parameter initial value, adjust after device parameter value the parasitic parameter value of integrated circuit can obtain by the first function estimation building, and the obtaining of parasitic parameter value of adjusting the integrated circuit after device parameters do not rely on physical layout.So, the device parameters optimization method of integrated circuit provided by the invention has avoided in prior art, needing repeatedly repeatedly to call the defect that Software tool extracts parasitic parameter and repeatedly does the adjustment of physical layout, improved the optimization efficiency of the device parameters of integrated circuit, the optimization robotization of the device parameters of integrated circuit is easily realized.

The above, be only preferred embodiment of the present invention, not the present invention done to any pro forma restriction.

Although the present invention discloses as above with preferred embodiment, yet not in order to limit the present invention.Any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.

Claims (12)

1. a device parameters optimization method for integrated circuit, is characterized in that, comprise,

The parasitic parameter initial value of A, extraction integrated circuit;

B, according to device parameters initial value and described parasitic parameter initial value, build the first function, the relation between described the first function representation parasitic parameter value and device parameters value;

C, according to parasitic parameter value and device parameters value, determine the circuit parameter of described integrated circuit, and judge whether described circuit parameter meets pre-provisioning request, if not, adjust described device parameters value;

Device parameters value and described the first function after D, foundation are adjusted obtain parasitic parameter calculated value, return to step C;

Wherein, described parasitic parameter value is described parasitic parameter initial value or described parasitic parameter calculated value; Described device parameters value is the device parameters value after described device parameters initial value or described adjustment.

2. device parameters optimization method according to claim 1, is characterized in that, described step B specifically comprises:

Acquisition device housing size initial value, described device housing is the external figure frame of each device of comprising of integrated circuit;

According to described device housing size initial value and described device parameters initial value, build the second function, the relation between described the second function representation device housing size value and described device parameters value; Wherein, described device housing size value comprises device housing size initial value;

According to described the second function and described device parameters value, obtain described device housing size value;

According to described device housing size value and described parasitic parameter initial value, build described the first function.

3. device parameters optimization method according to claim 2, is characterized in that, described parasitic parameter comprises dead resistance, and described foundation described device housing size value and described parasitic parameter initial value, build described the first function, specifically comprise,

Any interconnection line in selected integrated circuit, described interconnection line comprises the straight-line segment of some sections of first directions and the straight-line segment of some sections of second directions, wherein, first direction and second direction are orthogonal;

Determine and each section of all devices that described straight-line segment is relevant;

Determine the length contribution initial value of each device relevant to described each section of described straight-line segment to straight-line segment corresponding thereto;

According to described each device relevant to described each section of described straight-line segment to the length contribution initial value of straight-line segment corresponding thereto and the housing size initial value of this related device, build the 3rd function, each device relevant to described each section of described straight-line segment of described the 3rd function representation is to the relation between the length contribution of straight-line segment corresponding thereto and this device housing size value; Wherein, described length contribution comprises length contribution initial value;

According to described the 3rd function and all devices relevant to described straight-line segment, determine the length contribution summation of all devices relevant to this straight-line segment to this straight-line segment;

The all straight-line segments that length contribution summation and the described interconnection line of this straight-line segment comprised according to all devices relevant to every section of straight-line segment, build the 4th function, the relation between the housing size of all related devices that all straight-line segments that described the 4th function representation interconnect length comprises with it are corresponding;

According to described the 4th function and all skip floor via holes, to the contribution of the dead resistance of described interconnection line and described parasitic parameter initial value, build the first function that is of a size of parameter with described device housing.

4. device parameters optimization method according to claim 3, is characterized in that, the minimum boundary rectangle that the external figure of described device is described device.

5. device parameters optimization method according to claim 4, is characterized in that, described device housing size value comprises the housing size value XL of first direction and the housing size value YL of second direction, and described the second function is:

$\mathrm{XL}=\underset{i=1}{\overset{n-1}{\mathrm{\&Sigma;}}}{c}_{i,i+1}\&times;p_i\&times;p_{i+1}+\underset{i=1}{\overset{n}{\mathrm{\&Sigma;}}}{c}_i\&times;p_i+c_0;$

$\mathrm{YL}=\underset{i=1}{\overset{n-1}{\mathrm{\&Sigma;}}}{k}_{i,i+1}\&times;p_i\&times;p_{i+1}+\underset{i=1}{\overset{n}{\mathrm{\&Sigma;}}}{k}_i\&times;p_i+k_0;$

Wherein, p _ii device parameters, the number that n is device parameters, c _{i, i+1}, c _i, c ₀housing size value XL and device parameters p for described device first direction _ibetween the coefficient of the second function, k _i, k _{i, i+1}, k ₀housing size value YL and device parameters p for described device second direction _ibetween the coefficient of the second function.

6. device parameters optimization method according to claim 5, is characterized in that, described definite and each section of all devices that described straight-line segment is relevant, comprise,

According to all endpoint locations of described interconnection line, determine the external figure of described interconnection line;

Judge whether intersecting of the first device housing in the external graphics field of described straight-line segment and described interconnection line at least on one side, if so, determine that described the first device is the device relevant to described straight-line segment, judge whether described straight-line segment comprises at least one section of sub-line segment being positioned at outside device housing, and the length of described sub-line segment is not less than device in the external graphics field of the described interconnection line minimum housing size value in the direction of described straight-line segment place, if, by the both sides translation to sub-line segment on perpendicular to described sub-line segment length direction of described sub-line segment, then judge whether intersecting of the second device housing in the external graphics field of described sub-line segment and described interconnection line at least on one side, and whether judge between described the second device and described sub-line segment without other devices, if, determine that described the second device is related device.

7. device parameters optimization method according to claim 6, is characterized in that, describedly determines that each device relevant to described each section of described straight-line segment contributes initial value to the length of straight-line segment corresponding thereto, comprise,

When straight-line segment that described straight-line segment is first direction, judge the intersecting or whether intersect with the extended line at least on one side of housing in the second direction of related device of housing of the straight-line segment of described first direction and the second direction of related device at least on one side whether, if so, determine the housing size value XL that described related device is its first direction to the length contribution initial value of straight-line segment;

When straight-line segment that described straight-line segment is second direction, judge the intersecting or whether intersect with the extended line at least on one side of housing on the first direction of related device of housing of the straight-line segment of described second direction and the first direction of related device at least on one side whether, if so, described related device is the housing size value YL of its second direction to the length contribution of straight-line segment.

8. device parameters optimization method according to claim 6, is characterized in that,

When straight-line segment that straight-line segment is first direction, described the 3rd function is:

L _x,i,j＝k _x,j,1×XL _j+k _x,j,0；

Wherein, L _{x, i, j}represent the length contribution of related device j to the straight-line segment i of first direction, XL _jrepresent related device j housing size value in a first direction, k _{x, j, 1}represent the length contribution L of related device j to the straight-line segment i on first direction _{x, i, j}housing size value XL with the first direction of device j _jthe Monomial coefficient of funtcional relationship, k _{x, j, 0}represent the length contribution L of related device j to the straight-line segment i on first direction _{x, i, j}with the housing size value XL on the first direction of device j _jthe zero degree item coefficient of funtcional relationship;

When straight-line segment that straight-line segment is second direction, described the 3rd function is:

L _y,i,j＝k _y,j,1×YL _j+k _y,j,0；

Wherein, L _{y, i, j}represent the length contribution of related device j to the straight-line segment i of second direction, YL _jrepresent the housing size value of related device j in second direction, k _{y, j, 1}represent the length contribution L of related device j to the straight-line segment i in second direction _{y, i, j}housing size value YL with the second direction of device j _jthe Monomial coefficient of funtcional relationship, k _{y, j, 0}represent the length contribution L of related device j to the straight-line segment i in second direction _{y, i, j}with the housing size value YL in the second direction of device j _jthe zero degree item coefficient of funtcional relationship.

9. device parameters optimization method according to claim 8, it is characterized in that, set described interconnection line and comprise the straight-line segment of n section first direction and the straight-line segment of l section second direction, h device is relevant to one section of straight-line segment of first direction, m device is relevant to one section of straight-line segment of second direction, described the 4th function, is specially:

$L_{\mathrm{xy}}=\underset{i=1}{\overset{n}{\mathrm{\&Sigma;}}}\left(\underset{j=1}{\overset{h}{\mathrm{\&Sigma;}}}(k_{x,j,1}\&times;{\mathrm{XL}}_j+k_{x,j,0})\right)+\underset{i=1}{\overset{l}{\mathrm{\&Sigma;}}}\left(\underset{j=1}{\overset{m}{\mathrm{\&Sigma;}}}(k_{y,j,1}\&times;{\mathrm{YL}}_j+k_{y,j,o})\right).$

10. device parameters optimization method according to claim 9, is characterized in that, described the first function, is specially:

$R_{\mathrm{wires}}=k\&times;[\underset{i=1}{\overset{n}{\mathrm{\&Sigma;}}}\left(\underset{j=1}{\overset{h}{\mathrm{\&Sigma;}}}(k_{x,j,1}\&times;{\mathrm{XL}}_j+k_{x,j,0})\right)+\underset{i=1}{\overset{l}{\mathrm{\&Sigma;}}}\left(\underset{j=1}{\overset{m}{\mathrm{\&Sigma;}}}(k_{y,j,1}\&times;{\mathrm{YL}}_j+k_{y,j,0})\right)]+\underset{i=1}{\overset{n}{\mathrm{\&Sigma;}}}(R_{\mathrm{via},i,i+1}/N_{\mathrm{vias},i})$ ；

Wherein, k is the coefficient of the first function, R _{via, i, i+1}for skip floor i, the resistance of a via hole of i+1 layer, N _{vias, i}for skip floor i, the mistake hole count on i+1 layer, n is total n skip floor on described interconnection line.

11. device parameters optimization methods according to claim 3, is characterized in that, the acquisition methods of described all skip floor via holes to the contribution of the dead resistance of described interconnection line, comprises,

Select any skip floor, obtain the number of via hole and the resistance of a via hole between described skip floor of described skip floor;

According to the resistance of the number of the via hole of described skip floor and via hole, obtain the contribution of all via holes of all described skip floors to the dead resistance of described interconnection line;

Contribution according to skip floor described in each to the dead resistance of interconnection line, obtains the contribution to the dead resistance of described interconnection line of all skip floors on described interconnection line.

12. according to the optimization method described in claim 1-11 any one, it is characterized in that, described step C, also comprises, if so, finishes the device parameters optimization of integrated circuit.

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