CN103514944A

CN103514944A - Control circuit for generating pseudo-SRAM (Static Random Access Memory) refreshing clock by adopting display clock

Info

Publication number: CN103514944A
Application number: CN201210217456.4A
Authority: CN
Inventors: 李煜文
Original assignee: SHANGHAI MOJING ELECTRONIC TECHNOLOGY Co Ltd
Current assignee: SHANGHAI MOJING ELECTRONIC TECHNOLOGY Co Ltd
Priority date: 2012-06-28
Filing date: 2012-06-28
Publication date: 2014-01-15

Abstract

The invention aims at designing a display controller of an LCD (Liquid Crystal Display) and provides a design method of a control circuit for generating a pseudo-SRAM (Static Random Access Memory) refreshing clock by adopting a display clock. By adoption of the method, a circuit for clock generation can be omitted.

Description

Adopt read clock to produce the control circuit of pseudo SRAM refresh clock

Technical field

The present invention, for the design of LCD display controller, has proposed a kind of method for designing that adopts read clock to produce the control circuit of pseudo SRAM refresh clock, can save the circuit that clock occurs.

Background technology

In LCD display control chip, can use larger sram memory, using and store locally buffered as displaying contents.Because resolution and chromatic number are progressively soaring, SRAM capacity needs increasing.

In order to reduce cost, have and propose to replace SRAM by the technology of pseudo SRAM (similar DRAM).In this type of design, need for pseudo SRAM produces a refresh clock, for the refresh control of DRAM internal memory, also need to increase arbitration circuit, to prevent that the read-write cycle of refresh cycle and pseudo SRAM from bumping simultaneously.It designs complicated, has certain reliability hidden danger, has also increased cost.

Summary of the invention

The present invention's LCD controls display circuit, directly adopts LCD refresh clock (extracting) from the control signal receiving, after simple lifting/lowering is processed frequently, for controlling refreshing of pseudo SRAM.Like this, the refresh clock of pseudo SRAM and the refresh clock of LCD are homologies, have so greatly simplified arbitration design.

Accompanying drawing explanation

Fig. 1 is the LCD display control chip block diagram that adopts conventional design, directly adopts pseudo SRAM to replace SRAM, and has designed for it supporting refresh clock generation circuit and anticollision arbitration circuit.Wherein: A is interface circuit; B is control circuit; C is digital to analog converter; D drives and output circuit; E is pseudo SRAM; F is refresh clock generator; G is anticollision arbitration circuit.

Fig. 2 is the present invention's LCD display control chip block diagram, wherein: A is interface circuit; B is control circuit; C is digital to analog converter; D drives and output circuit; E is pseudo SRAM.

Embodiment

In the present invention's circuit, the control signal of sending here from system master chip, extract after LCD refresh clock, can, according to power consumption and pseudo SRAM rate request, carry out simple frequency division or process of frequency multiplication.Wherein process of frequency multiplication can complete with simple phaselocked loop.

In whole circuit design, can use the lowest common multiple frequency of LCD refreshing frequency and pseudo SRAM refreshing frequency as the reference clock of system only, and the former two is homology, therefore can verify by general synchronous logic checking flow process.

Claims

1. a design for LCD display controller, the employing read clock that can save the circuit of clock generation produces the method for designing that pseudo SRAM carrys out the control circuit of refresh clock.

2. a circuit design that meets claim 1, is characterized in that, extracts LCD show after refresh clock from system master chip the control signal of sending here, and desired signal, according to power consumption and pseudo SRAM rate request, is carried out to simple frequency division or process of frequency multiplication.

3. a circuit design that meets claim 1, is characterized in that, the refresh clock of pseudo SRAM and the refresh clock of LCD are homologies, has simplified arbitration design.

4. a circuit design that meets claim 1, it is characterized in that, in whole circuit design, can use the lowest common multiple frequency of LCD refreshing frequency and pseudo SRAM refreshing frequency as the reference clock of system only, and the former two is homology, therefore can verify by general synchronous logic checking flow process.