CN103514937A - Discharging circuit of memory - Google Patents
Discharging circuit of memory Download PDFInfo
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- CN103514937A CN103514937A CN201210207782.7A CN201210207782A CN103514937A CN 103514937 A CN103514937 A CN 103514937A CN 201210207782 A CN201210207782 A CN 201210207782A CN 103514937 A CN103514937 A CN 103514937A
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Abstract
The invention provides a discharging circuit of a memory to overcome the problem of uncontrollable discharging speeds of positive voltage and negative voltage in a traditional discharging circuit. The discharging circuit provided by the invention comprises a P-tube current mirror composed of PMOS tubes, an N-tube current mirror composed of NMOS tubes, a negative voltage discharging branch and a positive voltage discharging branch. Through controlling the number of the PMOS tubes in the circuit, the sizes of positive and negative voltage discharging currents are controlled, and the speeds of positive and negative voltage discharging currents are made to be identical in a same period of time. The speed of discharging current is controlled in the whole discharging process, so influence of an overfast discharging speed on the life of the memory is mitigated, and performance degradation of the memory is delayed; discharging in different periods of time is realized through adjusting the state of closing or opening of a switch, so discharging smoothness is improved.
Description
Technical field
The application relates to storer discharge technology field, particularly relates to a kind of storer discharge circuit.
Background technology
In existing storer, erase operation is the steps necessary of storage unit data writing, and it need to add negative voltage (VNEG) to the grid of storage unit (gate), and trap (well) is added to positive voltage (VPW).These two kinds of voltages are generally all produced by charge pump.Wipe after end, grid voltage and trap voltage all will discharge into GND (Ground represents ground or 0).The velocity of discharge can produce negative impact to the life-span of storer too soon.
Traditional discharge circuit as shown in Figure 1, negative voltage on storage unit grid and the positive voltage on trap, can be equivalent to a capacitor C 0, respectively there are a switching tube DISP and DISN in capacitor C 0 two ends, discharge circuit discharges to capacitor C 0 two ends respectively, as described in Figure 2, the velocity of discharge of generating positive and negative voltage is very fast for traditional discharge waveform, has reduced the serviceable life of storer.And the ducting capacity of switching tube DISP and DISN is affected by the factors such as sparking voltage, supply voltage, temperature, there will be the different situation of the capacitor C 0 both sides velocity of discharge, because velocity of discharge difference also can produce interference.
Summary of the invention
The application's technical matters to be solved is to provide a kind of storer discharge circuit, to solve the out of contior problem of the generating positive and negative voltage velocity of discharge in traditional discharge circuit.
In order to address the above problem, the application discloses a kind of storer discharge circuit, comprising:
The P tube current mirror that PMOS pipe forms;
The N tube current mirror that NMOS pipe forms;
Negative voltage discharge branch road and positive voltage discharge paths;
Wherein, the grid of the PMOS pipe in P tube current mirror meets internal current source Idisc, and source electrode meets builtin voltage VDD, and drain electrode connects negative voltage discharge branch road, for copying discharge current;
The grid of the 2nd PMOS pipe in P tube current mirror meets internal current source Idisc, and source electrode meets builtin voltage VDD, and drain electrode connects N tube current mirror, for copying discharge current;
Except a described PMOS pipe and described the 2nd PMOS pipe, described P tube current mirror also comprises n PMOS pipe, and the source electrode of described n PMOS pipe is connected with n switch respectively, grid and drain electrode meet internal current source Idisc, in parallel between n PMOS pipe, for the size of controlled discharge electric current, n >=1;
A described n switch is respectively used to control a described n PMOS and whether manages place in circuit;
The drain and gate of the NMOS pipe in N tube current mirror and the grid of the 2nd NMOS pipe connect the drain electrode of the 2nd PMOS pipe, the source ground of a NMOS pipe;
The drain electrode of the 2nd NMOS pipe in N tube current mirror connects positive voltage discharge paths, source ground;
When m switch is closed, m PMOS pipe place in circuit, the discharge current of negative voltage discharge branch road is Idisc/m, the discharge current of positive voltage discharge paths is Idisc/m, n >=1, n >=m >=1, n and m are positive integer;
By changing the state that switch is closed or disconnect, control the quantity of PMOS pipe place in circuit, adjust the time period of electric discharge.
Preferably, the time period of described adjustment electric discharge comprises:
When a described n switch is all closed, in circuit, access described n PMOS pipe in parallel, be now first discharge time section;
By reducing one by one the number of switches in closure state in a described n switch, reduce one by one the PMOS pipe quantity in parallel accessing in circuit, the quantity of a Closing Switch of every minimizing, is adjusted into the time period of an electric discharge, until remain a switch in closure state.
Preferably, described negative voltage discharge branch road comprises: negative voltage high voltage protective pipe, negative voltage injectron and negative voltage discharge Enable Pin.
Preferably, the source electrode of described negative voltage high voltage protective pipe connects the drain electrode of a PMOS pipe, grounded-grid, and drain electrode connects negative voltage injectron.
Preferably, the current potential at place, negative voltage high voltage protective pipe position described in described negative voltage high voltage protective pipe limiting circuit, for the protection of a described PMOS pipe.
Preferably, the source electrode of described negative voltage injectron connects the drain electrode of negative voltage high voltage protective pipe, and grid connects negative voltage discharge Enable Pin, and drain electrode connects negative voltage.
Preferably, described positive voltage discharge paths comprises: positive voltage high voltage protective pipe, positive voltage injectron and positive voltage electric discharge Enable Pin.
Preferably, the source electrode of described positive voltage high voltage protective pipe connects the drain electrode of the 2nd NMOS pipe, and grid connects builtin voltage, and drain electrode connects positive voltage injectron.
Preferably, the current potential at place, positive voltage high voltage protective pipe position described in described positive voltage high voltage protective pipe limiting circuit, for the protection of described the 2nd NMOS pipe.
Preferably, the source electrode of described positive voltage injectron connects the drain electrode of positive voltage high voltage protective pipe, and grid connects positive voltage electric discharge Enable Pin, and drain electrode connects positive voltage.
Compared with prior art, the application comprises following advantage:
A kind of storer discharge circuit that the application proposes, comprise PMOS (Positive channel-Metal-Oxide-Semiconductor, P-channel metal-oxide-semiconductor) pipe forms P tube current mirror and NMOS (Negative channel-Metal-Oxide-Semiconductor, N NMOS N-channel MOS N) pipe forms N tube current mirror and positive and negative voltage discharge paths, by control, be linked into the quantity of the PMOS pipe in circuit, control the size of generating positive and negative voltage discharge current, in section, the speed of generating positive and negative voltage discharge current is equated at one time.The speed of controlled discharge electric current in whole discharge process, has alleviated the too fast impact on storage life of the velocity of discharge, has delayed the performance degradation of storer; And by adjusting the state that switch is closed or disconnect, time segment is discharged, and has improved the stationarity of electric discharge.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of a kind of storer discharge circuit in prior art;
Fig. 2 is the wave form varies schematic diagram of sparking voltage in prior art;
Fig. 3 is memory erase voltage-drop loading schematic diagram described in the application;
Fig. 4 is a kind of storer discharge circuit schematic diagram described in the embodiment of the present application one;
Fig. 5 is the wave form varies schematic diagram of positive and negative sparking voltage described in the embodiment of the present application one;
Fig. 6 is the preferred version schematic diagram of a kind of storer discharge circuit described in the embodiment of the present application two.
Embodiment
For the application's above-mentioned purpose, feature and advantage can be become apparent more, below in conjunction with the drawings and specific embodiments, the application is described in further detail.
The wiping of storer (erase) operation is the steps necessary to storage unit data writing, need to add negative voltage (VNEG) to the grid of storage unit (gate), and trap (well) is added to positive voltage (VPW).These two kinds of voltages are generally all produced by charge pump.After erase operation finishes, grid voltage and trap voltage all will discharge into GND, and as shown in Figure 3, source is source electrode, and drain is drain electrode.
A kind of storer discharge circuit that the application provides, on traditional discharge circuit basis, P tube current mirror and N tube current mirror have been increased, formed CMOS (Complementary-Metal-Oxide-Semiconductor, complementary metal oxide semiconductor (CMOS)) circuit, and align, negative voltage discharge branch road improves; The size of a part of control pmos discharge current processed in P tube current mirror, another part PMOS pipe copies discharge current; Injectron and high voltage protective pipe in positive and negative discharge paths, have been increased.
Below by enumerating several concrete examples, introduce in detail a kind of storer discharge circuit that the application proposes.
Embodiment mono-, introduces in detail a kind of storer discharge circuit described in the application.
With reference to Fig. 4, show a kind of storer discharge circuit schematic diagram described in the embodiment of the present application one.
Described in the present embodiment, storer discharge circuit comprises:
Builtin voltage VDD; Internal current source Idisc;
The P tube current mirror that PMOS pipe forms;
The N tube current mirror that NMOS pipe forms;
And, negative voltage discharge branch road and positive voltage discharge paths;
Wherein, described P tube current mirror comprises a PMOS pipe MP3 and the 2nd PMOS pipe MP4, and 3 PMOS manage MP0, MP1 and MP2;
The grid of a described PMOS pipe MP3 meets internal current source Idisc, and source electrode meets builtin voltage VDD, and drain electrode connects negative voltage discharge branch road, for copying discharge current;
The grid of described the 2nd PMOS pipe MP4 meets internal current source Idisc, and source electrode meets builtin voltage VDD, and drain electrode connects N tube current mirror, for copying discharge current;
The source electrode of described 3 PMOS pipe MP0, MP1 and MP2 is connected with 3 switch S 0, S1 and S2 respectively, and grid and drain electrode meet internal current source Idisc, and 3 PMOS manage parallel connection between MP0, MP1 and MP2, for the size of controlled discharge electric current;
Described 3 switch S 0, S1 and S2 are respectively used to control whether place in circuit of described 3 PMOS pipe MP0, MP1 and MP2;
Described N tube current mirror comprises a NMOS pipe MN0 and the 2nd NMOS pipe MN1;
The drain and gate of a described NMOS pipe MN0 connects the drain electrode of the 2nd PMOS pipe MP4, source ground;
The grid of described the 2nd NMOS pipe MN1 connects the drain electrode of the 2nd PMOS pipe MP4, and drain electrode connects positive voltage discharge paths, source ground.
Conventionally, if metal-oxide-semiconductor grid and drain electrode are connected together, this connection connects diode, because its performance is similar to a diode.As described in PMOS pipe MP0, MP1 and MP2, the connection of described NMOS pipe MN0 is all that diode connects.
Described in the present embodiment, the principle of work of storer discharge circuit is as follows:
When m switch is closed, m PMOS pipe place in circuit, the discharge current of negative voltage discharge branch road is Idisc/m, the discharge current of positive voltage discharge paths is Idisc/m, 3 >=m >=1, m is positive integer;
By changing the state that switch is closed or disconnect, control the quantity of PMOS pipe place in circuit, adjust the time period of electric discharge.
In the storer discharge circuit described in the embodiment of the present application, described switch is closed, and the PMOS pipe being connected with the switch of closure state is linked in described circuit; Described switch disconnects, and the PMOS pipe being connected with the switch of off-state is not linked in described circuit.For example, when 3 switch S 0, S1 and S2 are closed, 3 PMOS that are connected with these 3 switch S 0, S1 and S2 manage MP0, MP1 and MP2 is linked in circuit, again because in parallel between these 3 PMOS pipe MP0, MP1 and MP2, so, the electric current of internal current source Idisc is through after these 3 PMOS pipe MP0, MP1 in parallel and MP2, and size of current is Idisc/3; After the electric current that the one PMOS pipe MP3 is Idisc/3 by size copies, output to negative voltage discharge branch road; After the electric current that the 2nd PMOS pipe MP4 is Idisc/3 by size copies, output to N tube current mirror, a pair of NMOS pipe in N tube current mirror, after a NMOS pipe MN0 and the 2nd NMOS pipe MN1 transform electric current, outputs to positive voltage discharge paths.
When described 3 switch S 0, S1 and S2 are closed, 3 PMOS that are connected with these 3 switch S 0, S1 and S2 manage MP0, MP1 and MP2 is linked in circuit, be now one discharge time section T0; After any one switch in described 3 switch S 0, S1 and S2 in closure state is disconnected, as cut-off switch S2, now in described circuit, having 2 switch S 0 and S1 closed, have 2 PMOS pipe MP0 and MP1 in parallel to be linked in circuit, is now another discharge time of section T1; By that analogy, after described 2 switch S 0 in closure state and any one switch in S1 are disconnected, as cut-off switch S1, now in described circuit, have 1 switch S 0 closure, PMOS pipe MP0 is linked in circuit, be now next one section T2 discharge time.
Through three discharge time section T0, T1 and the discharge operation of T2, positive voltage VPW and negative voltage VNEG discharge into GND stably, as shown in Figure 5.
In the present embodiment P tube current mirror, except a described PMOS pipe MP3 and described the 2nd PMOS pipe MP4, can also comprise the PMOS pipe that n source electrode is connected with n switch, and grid and the drain electrode of this n PMOS pipe meet internal current source Idisc, in parallel between n PMOS pipe, n >=1, n is positive integer; The quantity of PMOS pipe is not limited to 3 in the present embodiment, can be 2,4,5, or more, should not be construed the restrictive condition to the application herein; When in described circuit, the quantity of PMOS pipe in parallel is more, to the velocity of discharge of discharge circuit, control more accurately; More can adjust more discharge time of section.
In sum, embodiment compared with prior art, comprises following advantage described in the application:
A kind of storer discharge circuit that the application proposes, comprise that P tube current mirror and NMOS that PMOS pipe forms manage N tube current mirror and the positive and negative voltage discharge paths forming, by control, be linked into the quantity of the PMOS pipe in circuit, control the size of generating positive and negative voltage discharge current, in section, the speed of generating positive and negative voltage discharge current is equated at one time.The speed of controlled discharge electric current in whole discharge process, has alleviated the too fast impact on storage life of the velocity of discharge, has delayed the performance degradation of storer; And by adjusting the state that switch is closed or disconnect, time segment is discharged, and has improved the stationarity of electric discharge.
Below by example 2, introduce in detail the preferred version of a kind of storer discharge circuit of the application's proposition.
Embodiment bis-, introduce in detail the preferred version of a kind of storer discharge circuit described in the application.
With reference to Fig. 6, show the preferred version schematic diagram of a kind of storer discharge circuit described in the embodiment of the present application two.
Described in the present embodiment, storer discharge circuit comprises:
Builtin voltage VDD; Internal current source Idisc;
The P tube current mirror that PMOS pipe forms;
The N tube current mirror that NMOS pipe forms;
And, negative voltage discharge branch road and positive voltage discharge paths;
Wherein, preferred, described P tube current mirror comprises a PMOS pipe MP3 and the 2nd PMOS pipe MP4, and 3 PMOS manage MP0, MP1 and MP2;
The grid of a described PMOS pipe MP3 meets internal current source Idisc, and source electrode meets builtin voltage VDD, and drain electrode connects negative voltage discharge branch road, for copying discharge current;
The grid of described the 2nd PMOS pipe MP4 meets internal current source Idisc, and source electrode meets builtin voltage VDD, and drain electrode connects N tube current mirror, for copying discharge current;
The source electrode of described 3 PMOS pipe MP0, MP1 and MP2 is connected with 3 switch S 0, S1 and S2 respectively, and grid and drain electrode meet internal current source Idisc, and 3 PMOS manage parallel connection between MP0, MP1 and MP2, for the size of controlled discharge electric current;
Described 3 switch S 0, S1 and S2 are respectively used to control whether place in circuit of described 3 PMOS pipe MP0, MP1 and MP2;
Preferably, described N tube current mirror comprises a NMOS pipe MN0 and the 2nd NMOS pipe MN1;
The drain and gate of a described NMOS pipe MN0 connects the drain electrode of the 2nd PMOS pipe MP4, source ground;
The grid of described the 2nd NMOS pipe MN1 connects the drain electrode of the 2nd PMOS pipe MP4, and drain electrode connects positive voltage discharge paths, source ground;
Preferably, described negative voltage discharge branch road comprises: negative voltage high voltage protective pipe MH0, negative voltage injectron MH1 and negative voltage discharge Enable Pin SW1;
The source electrode of described negative voltage high voltage protective pipe MH0 connects the drain electrode of a PMOS pipe MP3, grounded-grid, and drain electrode meets negative voltage injectron MH1;
The current potential at place, negative voltage high voltage protective GuanMH0 position described in described negative voltage high voltage protective pipe MH0 limiting circuit, for the protection of a described PMOS pipe MP3;
The source electrode of described negative voltage injectron MH1 connects the drain electrode of negative voltage high voltage protective pipe MH0, and grid meets negative voltage discharge Enable Pin SW1, and drain electrode meets negative voltage VNEG;
Preferably, described positive voltage discharge paths comprises: positive voltage high voltage protective pipe MH3, positive voltage injectron MH2 and positive voltage electric discharge Enable Pin SW2;
The source electrode of described positive voltage high voltage protective pipe MH3 connects the drain electrode of the 2nd NMOS pipe MN1, and grid connects builtin voltage, and drain electrode meets positive voltage injectron MH2;
The current potential at place, positive voltage high voltage protective GuanMH3 position described in described positive voltage high voltage protective pipe MH3 limiting circuit, for the protection of described the 2nd NMOS pipe MN1;
The source electrode of described positive voltage injectron MH2 connects the drain electrode of positive voltage high voltage protective pipe MH3, and grid meets positive voltage electric discharge Enable Pin SW2, and drain electrode meets positive voltage VPW.
Conventionally, if metal-oxide-semiconductor grid and drain electrode are connected together, this connection connects diode, because its performance is similar to a diode.As described in PMOS pipe MP0, MP1 and MP2, the connection of described NMOS pipe MN0 is all that diode connects.
Described in the embodiment of the present application, a kind of principle of work of preferred version of storer discharge circuit is as follows:
When m switch is closed, m PMOS pipe place in circuit, the discharge current of negative voltage discharge branch road is Idisc/m, the discharge current of positive voltage discharge paths is Idisc/m, 3 >=m >=1, m is positive integer;
By changing the state that switch is closed or disconnect, control the quantity of PMOS pipe place in circuit, adjust the time period of electric discharge;
The time period of described adjustment electric discharge comprises:
When described 3 switches are all closed, in circuit, access described 3 PMOS pipes in parallel, be now first discharge time section;
By reducing one by one the number of switches in closure state in described 3 switches, reduce one by one the PMOS pipe quantity in parallel accessing in circuit, the quantity of a Closing Switch of every minimizing, is adjusted into the time period of an electric discharge, until remain a switch in closure state.
In the preferred version of the storer discharge circuit described in the embodiment of the present application, described internal current source Idisc inputs constant electric current, by changing the state that switch S 0, S1 and S2 are closed or disconnect, control respectively whether place in circuit of PMOS pipe MP0, MP1 and MP2, because in parallel between described PMOS pipe MP0, MP1 and MP2, electric current to described internal current source Idisc input has the effect of sharing, the quantity of PMOS pipe in parallel is not limited to 3 herein, it can be 2,4,5, or more, should not be construed the restrictive condition to the application.After PMOS pipe in parallel is shared electric current, a PMOS pipe MP3 and the 2nd PMOS pipe MP4, by after the current replication after sharing, export to respectively negative voltage discharge branch road and N tube current mirror, and N tube current mirror is exported to positive voltage discharge paths after electric current being transformed again.
Negative voltage high voltage protective pipe MH0 in negative voltage discharge branch road and the positive voltage high voltage protective pipe MH3 in positive voltage discharge paths are high-voltage MOS pipes; the main clamping action that rises; limit the current potential at its place, present position, protect respectively a PMOS pipe MP3 and the 2nd NMOS pipe MN1 not to be subject to high-tension impact.
Negative voltage injectron MH1 in negative voltage discharge branch road and the positive voltage injectron MH4 in positive voltage discharge paths are also high-voltage MOS pipes, can be high pressure resistant, and grid is connected with positive voltage electric discharge Enable Pin SW2 with negative voltage discharge Enable Pin SW1 respectively.Because the size of electric current is controlled through sharing of PMOS pipe in parallel, add negative voltage injectron MH1 and the high voltage bearing character of positive voltage injectron MH4, so negative voltage discharge Enable Pin SW1 and positive voltage electric discharge Enable Pin SW2 levels off to perfect condition to the control of electric discharge, can not be subject to the impact of the factors such as voltage and temperature.
A kind of preferred storer discharge circuit proposing by the embodiment of the present application, the erasing voltage of storer is carried out to discharge operation, due to size that can controlled discharge electric current and adjust section discharge time, so the slight change of electric discharge Enable Pin ducting capacity is not enough to have influence on the whole discharge operation to erasing voltage.By control size of current and discharge time section, the speed of controlled discharge on the whole, can obtain the steady discharge waveform of positive and negative erasing voltage.
Each embodiment in this instructions all adopts the mode of going forward one by one to describe, and each embodiment stresses is the difference with other embodiment, between each embodiment identical similar part mutually referring to.
A kind of storer discharge circuit above the application being provided, be described in detail, applied specific case herein the application's principle and embodiment are set forth, the explanation of above embodiment is just for helping to understand the application's method and core concept thereof; Meanwhile, for one of ordinary skill in the art, the thought according to the application, all will change in specific embodiments and applications, and in sum, this description should not be construed as the restriction to the application.
Claims (10)
1. a storer discharge circuit, is characterized in that, comprising:
The P tube current mirror that PMOS pipe forms;
The N tube current mirror that NMOS pipe forms;
Negative voltage discharge branch road and positive voltage discharge paths;
Wherein, the grid of the PMOS pipe in P tube current mirror meets internal current source Idisc, and source electrode meets builtin voltage VDD, and drain electrode connects negative voltage discharge branch road, for copying discharge current;
The grid of the 2nd PMOS pipe in P tube current mirror meets internal current source Idisc, and source electrode meets builtin voltage VDD, and drain electrode connects N tube current mirror, for copying discharge current;
Except a described PMOS pipe and described the 2nd PMOS pipe, described P tube current mirror also comprises n PMOS pipe, and the source electrode of described n PMOS pipe is connected with n switch respectively, grid and drain electrode meet internal current source Idisc, in parallel between n PMOS pipe, for the size of controlled discharge electric current, n >=1;
A described n switch is respectively used to control a described n PMOS and whether manages place in circuit;
The drain and gate of the NMOS pipe in N tube current mirror and the grid of the 2nd NMOS pipe connect the drain electrode of the 2nd PMOS pipe, the source ground of a NMOS pipe;
The drain electrode of the 2nd NMOS pipe in N tube current mirror connects positive voltage discharge paths, source ground;
When m switch is closed, m PMOS pipe place in circuit, the discharge current of negative voltage discharge branch road is Idisc/m, the discharge current of positive voltage discharge paths is Idisc/m, n >=1, n >=m >=1, n and m are positive integer;
By changing the state that switch is closed or disconnect, control the quantity of PMOS pipe place in circuit, adjust the time period of electric discharge.
2. circuit according to claim 1, is characterized in that,
The time period of described adjustment electric discharge comprises:
When a described n switch is all closed, in circuit, access described n PMOS pipe in parallel, be now first discharge time section;
By reducing one by one the number of switches in closure state in a described n switch, reduce one by one the PMOS pipe quantity in parallel accessing in circuit, the quantity of a Closing Switch of every minimizing, is adjusted into the time period of an electric discharge, until remain a switch in closure state.
3. circuit according to claim 1, is characterized in that,
Described negative voltage discharge branch road comprises: negative voltage high voltage protective pipe, negative voltage injectron and negative voltage discharge Enable Pin.
4. circuit according to claim 3, is characterized in that:
The source electrode of described negative voltage high voltage protective pipe connects the drain electrode of a PMOS pipe, grounded-grid, and drain electrode connects negative voltage injectron.
5. circuit according to claim 3, is characterized in that:
The current potential at place, negative voltage high voltage protective pipe position described in described negative voltage high voltage protective pipe limiting circuit, for the protection of a described PMOS pipe.
6. circuit according to claim 3, is characterized in that:
The source electrode of described negative voltage injectron connects the drain electrode of negative voltage high voltage protective pipe, and grid connects negative voltage discharge Enable Pin, and drain electrode connects negative voltage.
7. circuit according to claim 1, is characterized in that,
Described positive voltage discharge paths comprises: positive voltage high voltage protective pipe, positive voltage injectron and positive voltage electric discharge Enable Pin.
8. circuit according to claim 7, is characterized in that:
The source electrode of described positive voltage high voltage protective pipe connects the drain electrode of the 2nd NMOS pipe, and grid connects builtin voltage, and drain electrode connects positive voltage injectron.
9. circuit according to claim 7, is characterized in that:
The current potential at place, positive voltage high voltage protective pipe position described in described positive voltage high voltage protective pipe limiting circuit, for the protection of described the 2nd NMOS pipe.
10. circuit according to claim 7, is characterized in that:
The source electrode of described positive voltage injectron connects the drain electrode of positive voltage high voltage protective pipe, and grid connects positive voltage electric discharge Enable Pin, and drain electrode connects positive voltage.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210207782.7A CN103514937B (en) | 2012-06-18 | 2012-06-18 | A kind of storer discharge circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210207782.7A CN103514937B (en) | 2012-06-18 | 2012-06-18 | A kind of storer discharge circuit |
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| CN103514937A true CN103514937A (en) | 2014-01-15 |
| CN103514937B CN103514937B (en) | 2015-11-25 |
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| CN105280233A (en) * | 2014-06-05 | 2016-01-27 | 力晶科技股份有限公司 | Negative reference voltage generating circuit and negative reference voltage generating system |
| CN109427403A (en) * | 2017-09-01 | 2019-03-05 | 合肥格易集成电路有限公司 | A kind of discharge circuit and memory |
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Also Published As
| Publication number | Publication date |
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| CN103514937B (en) | 2015-11-25 |
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Address after: 502 / 15, building 1, 498 GuoShouJing Road, Zhangjiang High Tech Park, Pudong New Area, Shanghai 201203 Patentee after: SHANGHAI GEYI ELECTRONIC Co.,Ltd. Patentee after: Zhaoyi Innovation Technology Group Co.,Ltd. Address before: 502 / 15, building 1, 498 GuoShouJing Road, Zhangjiang hi tech park, Shanghai, 201203 Patentee before: SHANGHAI GEYI ELECTRONIC Co.,Ltd. Patentee before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. |
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