CN103513208B - A kind of error compensating method of the total timing offset calibration of picosecond integrated circuit test system - Google Patents

Abstract

The error compensating method of the total timing offset calibration of a kind of picosecond integrated circuit test system, including setting up calibrating patterns, is attributed to the calibration of total for integrated circuit test system timing offset the timing accuracy being input to output<i>t</i>_Dr-Cmp, input edge put deviation<i>t</i>_DrDeviation is put with output edge<i>t</i>_CmpThe measurement respectively of three components, the delay time error produced during to each component measurement compensates respectively, the delay time error that during compensation, the factor such as comprehensive assessment calibration interface plate, cable, oscillograph introduces, and finally synthesizes calibration result.Its advantage is: breach the limitation of the qualitative checking of traditional method, achieve accurate, the quantitative measurement of the high speed integrated circuit test total timing offset of system, solve the calibration problem of high speed integrated circuit test system core time-parameters, it is possible to the high speed performance of accurate evaluation test system.

Description

A kind of error compensating method of the total timing offset calibration of picosecond integrated circuit test system

Technical field

The present invention relates to microelectronics field of measuring techniques, particularly to the error compensating method of the total timing offset calibration of a kind of picosecond integrated circuit test system.It is applied to the high speed performance checking of integrated circuit test system, it is possible to the quantitative measurement for the total timing offset of integrated circuit test system provides a unified standard and judgment.

Background technology

In high speed integrated circuit test application, when integrated circuit test system drives or measures a certain signal, it drives along or compares along all causing whole test sequence substantial deviation with the deviation producing for 1 nanosecond expeced time, makes test result lose meaning.Therefore, in high speed integrated circuit test application, the requirement of test system time parameter is abnormal strict.The total timing offset of system is exactly reflect that the signal that test system provides drives along or compares along whether in intended time range, and accurately whether the relative time between each signal material time parameter.Only comprehensively, this parameter of analysis of test system exactly core time, performance and the stability of test system could be ensured.

On the other hand, the lifting of the total timing offset of lifting, particularly system of test system time parameter index will result directly in the cost several times of test system, the even growth of decades of times.Need based on scientific research development and practical application, domestic colleges and universities, scientific research institutions, a large amount of Introduced From Abroad of national defence metrology Zhan Deng mechanism high speed integrated circuit test system, cost in the face of its costliness, but there is no a kind of specification method accurately to verify this parameter, be typically only possible by the supplementary meanss such as eye pattern and judge the high speed performance of system qualitatively.If can be introduced at equipment the stage effectively verify this parameter, it is possible to be substantially reduced the risk of buying, ensure scientific research, being smoothed out of production.

In sum, the total timing offset of system is the core parameter of high speed integrated circuit test system, and the reliability of high speed integrated circuit test is had vital impact, and the calibration of the total timing offset of system is that integrated circuit test system measures the problem needing solution badly.The calibration problem of the total timing offset of solution system, to the reliability ensureing high speed integrated circuit test, it is to avoid potential risk, significant.And the calibration for picosecond signal, the error introduced by requisite intermediate links such as calibration interface plate, adapter, connection cables in calibration process is particularly critical, whole calibration result will be produced very important impact.Therefore, it is necessary to comprehensive assessment considers each factor being likely to result in measurement error comprehensively, and make corresponding compensation.

Summary of the invention

It is an object of the invention to test, at high speed integrated circuit, the measurement Error Compensation problem that solves in the calibration process of the total timing offset of system, the total timing offset of the system that realizes quantitative, accurately measure, the high speed performance of validation integrated circuit test system, improves the calibration of integrated circuit test system time-parameters effectively.

The error compensating method of the total timing offset calibration of a kind of picosecond integrated circuit test system, including setting up calibrating patterns, is attributed to the calibration of total for integrated circuit test system timing offset the timing accuracy t being input to output_Dr-Cmp, input edge put deviation t_DrDeviation t is put with output edge_CmpThe measurement respectively of three components, the delay time error produced during to each component measurement compensates respectively, the delay time error that during compensation, the factor such as comprehensive assessment calibration interface plate, cable, oscillograph introduces, and finally synthesizes calibration result.

Described calibrating patterns is to first pass through to measure the timing accuracy t being input to output_Dr-Cmp, it is determined that deviation t is put at input edge_DrDeviation t is put with output edge_CmpBetween relative position, then respectively measure input edge put deviation and output edge put deviation, after finally the measurement error of three components being compensated respectively, synthesize calibration result.Be input to the timing accuracy of output be test system drive input time delay time intermediate value poor to the relative time compared between output delay time intermediate value, can determine that test system drive along distribution and compares the relative position that edge is distributed by this component；Input drive signal self maximum deviation that may be present that deviation is test system is put at input edge, and showing in Fig. 1 a and Fig. 1 b is exactly all distributions driving edge (including rising edge and trailing edge) to be likely to occur；Output comparison signal self maximum deviation that may be present that deviation is test system is put at output edge, and showing in Fig. 1 a and Fig. 1 b is exactly all comparison along the distribution being likely to occur.

The error compensation that the described timing accuracy being input to output is measured is to be connected in pairs by adjacency channel, and establishment calibration procedure controls all driving along simultaneously driving same figure, adopts suitable test period, and the driving that note programming sets is along bound-time as t_ref, and monitor the comparison edge of every pair of channels by test system simultaneously, find the time point t occurring that comparative result passes through the earliest respectively_minThe time point t that comparative result does not pass through occurs the latest_max.Measure the time delays error t that calibration interface plate introduces_x.The timing accuracy t being input to output after then compensating_Dr-CmpCalculate by formula (3).

It is that the driver to each passage is independently measured that the error compensation of deviation measurement is put at described input edge, will be simultaneously connected to oscillograph by the passage of school passage and reference signal.Establishment calibration procedure controls by a certain figure of school channels drive, adopts suitable test period, at t_progMoment occurs to drive along saltus step, controls reference channel simultaneously and drives, in 0 moment, the non-return-to-zero rising edge signal that an amplitude is equal.Actually occurred the time t of saltus step by school channels drive edge with oscillograph synchro measure_measT actual time with the generation of reference channel rising edge₀.Measure by school passage by total delay time error t of introducing after calibration interface plate_x1, the reference channel signal total delay time error t by introducing after calibration interface plate_x2, then the input edge after compensating is put deviation and is pressed formula (4) calculating.

It is that the comparator to each passage is independently measured that the error compensation of deviation measurement is put at described output edge, will be simultaneously connected to oscillograph by the passage of school passage and reference signal.Establishment calibration procedure controls to be driven a certain figure by the adjacent interconnected channel of school passage, adopts suitable test period, at t_progMoment occurs to drive along saltus step, controls reference channel simultaneously and drives, in 0 moment, the non-return-to-zero rising edge signal that an amplitude is equal.Actually occurred the time t of saltus step by school channels drive edge with oscillograph synchro measure_measT actual time with the generation of reference channel rising edge₀, calibration procedure controls just to be occurred to figure by the comparator reconnaissance probe of school passage the time t of saltus step_search.Measure by school passage by total delay time error t of introducing after calibration interface plate and cable_x1, the reference channel signal total delay time error t by introducing after calibration interface plate and cable_x2, total delay time error t of adjacency channel interconnection introducing on interface board_x3.Output edge after then compensating is put deviation and is pressed formula (5) calculating.

It is adopt time-domain transmission (TDT) measuring method improved that the delay time error that described calibration interface plate, cable, oscillograph etc. introduce compensates, one is launched soon along pulse signal with domain reflectometer (TDR) or pulse signal generator, two isometric cables are connected respectively by power splitter, it is connected to oscillographic two passages, in oscillograph, now make corresponding compensation, make the curve co-insides of two paths.Complete, cable Length discrepancy inconsistent by channel oscilloscope etc. and introduce the calibration of error.Then measured piece (such as cable, adapter, calibration interface plate wire etc.) is joined wherein one between cable and passage, measures the time delay between two signal rising edges.Exchange two cables, again measure, record twice measured value respectively, average, the transmission delay of the one section of measured piece added can be obtained；Especially, the delay time error that short lead on calibration interface plate is introduced, the time-domain transmission measuring method of described improvement is also inapplicable, therefore when calibration interface plate designs, special reserved one piece of region, the impedance design identical with the part employing of practical application, through-hole structure and cabling mode, separately design the wire of several different length, these wires only length is different, other characteristics such as live width, material are identical with practical application part, these wires are utilized to try to achieve the time delay of unit length wire, thus calculating the time delay that calibration interface plate short lead introduces.

Described final synthesis calibration result is to will enter into the timing accuracy t of output_Dr-Cmp, input edge put deviation t_DrDeviation t is put with output edge_CmpThree components are measured respectively, during to each component measurement, assess the delay time error that the factors such as calibration interface plate, cable, oscillograph introduce one by one, compensate respectively.Press formula (1), (2) synthesis calibration result after compensation, take ± max{ | A |, | B | be total timing offset of integrated circuit test system.

The advantage of the error compensating method of the present invention a kind of picosecond integrated circuit test system total timing offset calibration is the limitation breaching the qualitative checking of traditional method, achieve accurate, the quantitative measurement of the high speed integrated circuit test total timing offset of system, solve the calibration problem of high speed integrated circuit test system core time-parameters, it is possible to the high speed performance of accurate evaluation test system.Transmission of quantity value for testing system time parameter is laid a good foundation, and the method for quantitative measuring for the total timing offset of system establishes unified standard, it is achieved value is unified.The reliability and stability ensureing electronic product are significant.Can apply to newly buy high speed performance checking when integrated circuit test system is paid and checked and accepted simultaneously, provide a general touchstone for integrated circuit test system production firm, be applied to the factory calibration of test system.On the other hand, to set up high speed integrated circuit test system calibration specification there is reference.

Accompanying drawing explanation

Fig. 1 a is each component schematic diagram of the total timing offset of system (compares and lag behind situation about driving along distribution midpoint along distribution midpoint).

Fig. 1 b is each component schematic diagram of the total timing offset of system (compares and be ahead of situation about driving along distribution midpoint along distribution midpoint).

Fig. 2 is the measurement block diagram being input to output timing accuracy.

Fig. 3 is the measurement block diagram that deviation is put at input edge.

Fig. 4 is the measurement block diagram that deviation is put at output edge.

Detailed description of the invention

Shown in root Ju Fig. 1 Fig. 4.

1, calibrating patterns explanation

Assume to drive along the time of setting as reference time t₀, total for integrated circuit test system timing offset is decomposed into the composition of each component, as illustrated in figs. ia and ib, is divided into comparing and lags behind driving along distribution midpoint and be ahead of driving along distribution midpoint along distribution midpoint and comparing along distribution two kinds of midpoint situation.

Wherein, t₀: the reference time；

t_Dr-Cmp: it is input to the timing accuracy of output；

t_Dr: deviation, general use ± t are put in input edge_DrRepresent, figure drives along distribution be；

t_Cmp: deviation, general use ± t are put in output edge_CmpRepresent, figure compares along distribution be；

t_mid: compare along distribution midpoint；

In figure ± max{ | A |, | B | } it is total timing offset of test system, wherein A and B calculates as follows.

(1)

(2)

The calibration of total for system timing offset is attributed to the timing accuracy t being input to output by the present invention_Dr-Cmp, input edge put deviation t_DrDeviation t is put with output edge_CmpThe measurement respectively of three components, the delay time error produced during to each component measurement compensates respectively, finally synthesizes calibration result.

2, each error compensation calibrating component measurement

2.1, the error compensation that the timing accuracy of output is measured it is input to

Design calibration adaptable interface plate, connects test system adjacency channel, in pairs as in figure 2 it is shown, dotted portion represents that cabling completes in plate on figure alignment interface board.

Establishment calibration procedure controls all driving along simultaneously driving same figure, adopts suitable test period, and the driving that note programming sets is along bound-time as t_ref, and monitor the comparison edge of every pair of channels by test system simultaneously, find the time point t occurring that comparative result passes through the earliest respectively_minThe time point t that comparative result does not pass through occurs the latest_max.The time delays error t that assessment calibration interface plate introduces_x, then the timing accuracy t being input to output after compensation_Dr-CmpCalculate by formula (3):

(3)

Various different graphics are measured in circulation in aforementioned manners, and different amplitudes, exchange drives and compares passage, and test system is automatically measured and gathers data, the data statistic analysis that finally will obtain.

2.2, the error compensation that deviation is measured is put at input edge

Adopt high bandwidth oscilloscope that the driver of each passage is independently measured.Design calibration interface plate, will be drawn respectively by school passage high speed connector.Choose the driving signal of a certain passage in test system as reference signal, and adopt this passage as reference signal from start to finish.

Oscillograph will be simultaneously connected to, as it is shown on figure 3, bold portion represents by external cable connection calibration interface plate and oscillograph on figure alignment interface board by the passage of school passage and reference signal.Establishment calibration procedure controls by a certain figure of school channels drive, adopts suitable test period, at t_progMoment occurs to drive along saltus step, controls reference channel simultaneously and drives, in 0 moment, the non-return-to-zero rising edge signal that an amplitude is equal.Actually occurred the time t of saltus step by school channels drive edge with oscillograph synchro measure_measT actual time with the generation of reference channel rising edge₀, assess by school passage by total delay time error t of introducing after calibration interface plate_x1, the reference channel signal total delay time error t by introducing after calibration interface plate_x2.Input edge after then compensating is put deviation and is pressed formula (4) calculating:

(4)

Various different graphics are measured in circulation in aforementioned manners, and calibration procedure automatically analyzes statistical data.

2.3, the error compensation that deviation is measured is put at output edge

Adopt high bandwidth oscilloscope that the comparator of each passage is independently measured.To be drawn respectively by school passage high speed connector, choose reference channel as before as driving reference signal.

To be simultaneously connected to oscillograph by the passage of school passage and reference signal, as shown in Figure 4, on figure alignment interface board, dotted portion represents the internal cabling of interface board, and bold portion represents external connecting cables.Establishment calibration procedure controls to be driven a certain figure by the adjacent interconnected channel of school passage, adopts suitable test period, at t_progMoment occurs to drive along saltus step, controls reference channel simultaneously and drives, in 0 moment, the non-return-to-zero rising edge signal that an amplitude is equal.Actually occurred the time t of saltus step by school channels drive edge with oscillograph synchro measure_measT actual time with the generation of reference channel rising edge₀, calibration procedure controls just to be occurred to figure by the comparator reconnaissance probe of school passage the time t of saltus step_search, assess by school passage by total delay time error t of introducing after calibration interface plate and cable_x1, the reference channel signal total delay time error t by introducing after calibration interface plate and cable_x2, total delay time error t of adjacency channel interconnection introducing on interface board_x3.Output edge after then compensating is put deviation and is pressed formula (5) calculating:

(5)

Various different graphics are measured in circulation in aforementioned manners, and calibration procedure automatically analyzes statistical data.

3, the delay time error assessment that calibration interface plate, cable, oscillograph etc. introduce

3.1, the time-domain transmission measuring method improved

Adopt time-domain transmission (TDT) measuring method improved, one is launched soon along pulse signal with domain reflectometer (TDR) or pulse signal generator, connected two isometric cables by power splitter respectively, be connected to oscillographic two passages, measure the time delay between two signal rising edges.Exchange two cables, again measure.Record twice measured value respectively, oscillograph is made corresponding compensation, makes two curve co-insides.Complete, cable Length discrepancy inconsistent by channel oscilloscope etc. and introduce the calibration of error.Then measured piece (such as cable, adapter, calibration interface plate wire etc.) is joined wherein one between cable and passage, the transmission delay of the one section of measured piece added can be obtained.

3.2, the delay time error appraisal procedure that calibration interface plate short lead introduces

Due to short as far as possible in the length setting clocking requirement calibration interface plate cabling, and too short wire is affected by wire two end connector etc., it is difficult to measure result accurately by method described in 3.1.Therefore delay time error wire too short on calibration interface plate introduced compensates and adopts special handling.

The present invention is when calibration interface plate designs, special reserved one piece of region, the impedance design identical with the part employing of practical application, through-hole structure and cabling mode, separately design the wire of several different length, these wires only length is different, and other characteristics such as live width, material are identical with practical application part.Then the time delay of these several different length wires is measured respectively, measurement result is made on coordinate axes length (x-axis) and the graph of a relation of time delay (y-axis), and measurement data is carried out best linear fit, the spread speed of wire can be obtained thereby through the inverse of straight slope, evaluate the transmission delay of the short lead of other known length on interface board.

Claims (2)

1. the error compensating method of the total timing offset calibration of picosecond integrated circuit test system, it is characterised in that: set up calibrating patterns, the calibration of total for integrated circuit test system timing offset is attributed to the timing accuracy t being input to output_Dr-Cmp, input edge put deviation t_DrDeviation t is put with output edge_CmpThe measurement respectively of three components, the delay time error produced during to each component measurement compensates respectively, the delay time error that during compensation, comprehensive assessment calibration interface plate, cable, oscillograph introduce, and finally synthesizes calibration result；

The error compensation that the described timing accuracy being input to output is measured is to be connected in pairs by adjacency channel, and establishment calibration procedure controls all driving along simultaneously driving same figure, adopts suitable test period, and the driving that note programming sets is along bound-time as t_ref, and monitor the comparison edge of every pair of channels by test system simultaneously, find the time point t occurring that comparative result passes through the earliest respectively_minThe time point t that comparative result does not pass through occurs the latest_max, the time delays error t of assessment calibration interface plate introducing_x, then the timing accuracy t being input to output after compensation_Dr-CmpCalculate by formula (3)；Described formula (3) is:

$t_{Dr-Cmp}=t_{ref}-(\frac{t_{min}+t_{max}}{2}-t_x);$

It is that the driver to each passage is independently measured that the error compensation of deviation measurement is put at described input edge, oscillograph will be simultaneously connected to by the passage of school passage and reference signal, establishment calibration procedure controls by a certain figure of school channels drive, adopts suitable test period, at t_progMoment occurs to drive along saltus step, controls reference channel simultaneously and drives, in 0 moment, the non-return-to-zero rising edge signal that an amplitude is equal, is actually occurred the time t of saltus step with oscillograph synchro measure by school channels drive edge_measT actual time with the generation of reference channel rising edge₀, assess by school passage by total delay time error t of introducing after calibration interface plate_x1, the reference channel signal total delay time error t by introducing after calibration interface plate_x2, then the input edge after compensating is put deviation and is pressed formula (4) calculating；Described formula (4) is:

t_Dr=(t_meas-t_x1)-t_prog-(t₀-t_x2)；

It is that the comparator to each passage is independently measured that the error compensation of deviation measurement is put at described output edge, oscillograph will be simultaneously connected to by the passage of school passage and reference signal, establishment calibration procedure controls to be driven a certain figure by the adjacent interconnected channel of school passage, adopt suitable test period, at t_progMoment occurs to drive along saltus step, controls reference channel simultaneously and drives, in 0 moment, the non-return-to-zero rising edge signal that an amplitude is equal, is actually occurred the time t of saltus step with oscillograph synchro measure by school channels drive edge_measT actual time with the generation of reference channel rising edge₀, calibration procedure controls just to be occurred to figure by the comparator reconnaissance probe of school passage the time t of saltus step_search, assess by school passage by total delay time error t of introducing after calibration interface plate and cable_x1, the reference channel signal total delay time error t by introducing after calibration interface plate and cable_x2, total delay time error t of adjacency channel interconnection introducing on interface board_x3, then the output edge after compensating is put deviation and is pressed formula (5) calculating；Described formula (5) is:

t_Cmp=(t_meas-t_x1)-(t_search-t_x3)-(t₀-t_x2)。

2. the error compensating method of the total timing offset calibration of a kind of picosecond integrated circuit test system described in a Ju claim 1, it is characterised in that: described final synthesis calibration result is to will enter into the timing accuracy t of output_Dr-Cmp, input edge put deviation t_DrDeviation t is put with output edge_CmpThree components are measured respectively, during to each component measurement, the delay time error that assessment calibration interface plate, cable, oscillograph introduce one by one, compensate respectively, formula (1), (2) synthesis calibration result is pressed after compensation, take ± max{ | A |, | B | } it is total timing offset of integrated circuit test system；Described formula (1), (2) are respectively as follows:

(1) A=t_Dr+t_Cmp+t_Dr-Cmp,

(2) B=t_Dr+t_Cmp-t_Dr-Cmp。