CN103500565B - A kind of storage means and device - Google Patents

A kind of storage means and device Download PDF

Info

Publication number
CN103500565B
CN103500565B CN201310465949.4A CN201310465949A CN103500565B CN 103500565 B CN103500565 B CN 103500565B CN 201310465949 A CN201310465949 A CN 201310465949A CN 103500565 B CN103500565 B CN 103500565B
Authority
CN
China
Prior art keywords
edid
adv7850
chip
writing
display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201310465949.4A
Other languages
Chinese (zh)
Other versions
CN103500565A (en
Inventor
杜彦哲
孟伟平
李强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xinle Visual Intelligent Electronic Technology Tianjin Co ltd
Leshi Zhixin Electronic Technology Tianjin Co Ltd
Original Assignee
Leshi Zhixin Electronic Technology Tianjin Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Leshi Zhixin Electronic Technology Tianjin Co Ltd filed Critical Leshi Zhixin Electronic Technology Tianjin Co Ltd
Priority to CN201310465949.4A priority Critical patent/CN103500565B/en
Publication of CN103500565A publication Critical patent/CN103500565A/en
Application granted granted Critical
Publication of CN103500565B publication Critical patent/CN103500565B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Landscapes

  • Controls And Circuits For Display Device (AREA)

Abstract

Embodiments of the invention provide a kind of storage means and device, it relates to electronic technology field, it is possible to cancel exterior storage equipment, save hardware cost. The method comprises: the static RAM SRAM of the display data passage DDC port access ADV7850 chip of indicating meter forbidden by controller, then by the I of indicating meter2The interface of C bus switches to the storage space for storing external display device mark data EDID of SRAM, to obtain the first address of the internal memory needed for write EDID, according to the first address of this internal memory, write EDID, finally, calculate the School Affairs of EDID, if School Affairs is preset value, then enable DDC port access EDID.

Description

Storage method and device
Technical Field
The present invention relates to the field of electronic technologies, and in particular, to a storage method and apparatus.
Background
EDID (extended display identification data) is specified by the video electronics standards association and contains basic parameters of the display device, including vendor information, maximum image size, color settings, vendor presets, limits on frequency range, and strings of display name and serial number.
In the related art, EDID of a display is stored in an external storage device, and a signal source device accesses the external storage device through a DDC (display data channel) bus when an HDMI (high definition multimedia interface) or VGA (video graphics array) cable is accessed, reads the EDID stored therein, and then transmits a signal according to a resolution supported by the EDID.
However, since the EDID of the display is stored in the external storage device, i.e., a dedicated chip is required to store the EDID, hardware costs are increased.
Disclosure of Invention
Embodiments of the present invention provide a storage method and apparatus, which solve the problem of high hardware cost caused by storing EDID of a display in an external storage device, and write the EDID in a software manner by using an SRAM (static random access memory) space inside an ADV7850 chip of the display, thereby eliminating the external storage device and saving the hardware cost.
In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:
the embodiment of the invention provides a storage method, when an ADV7850 chip of a display is powered on, the method comprises the following steps:
forbidding a display data channel DDC port of the display to access a Static Random Access Memory (SRAM) of the ADV7850 chip;
i of the display2Switching an interface of a C bus to a storage space of the SRAM for storing the EDID of the external display device to obtain a memory first address required by writing in the EDID;
writing the EDID according to the memory initial address;
calculating a checksum of the EDID;
and if the checksum is a preset value, enabling the DDC port to access the EDID.
The method for prohibiting the display data channel DDC port of the display from accessing the static random access memory SRAM of the ADV7850 chip specifically includes:
through I2And writing an access prohibition command into the ADV7850 chip by using a C bus so that a control register in the ADV7850 chip is set to be 0, and prohibiting a display data channel DDC port of the display from accessing a Static Random Access Memory (SRAM) of the ADV7850 chip.
The I of the display2The method specifically includes the following steps that an interface of a bus C is switched to a storage space of the SRAM, wherein the storage space is used for storing external display device identification data EDID, so that a memory initial address required by writing in the EDID is obtained:
through I2Writing a switching command to the ADV7850 chip by the C bus, and writing the I of the display2And switching an interface of the C bus to a storage space of the SRAM, which is used for storing EDID used by a video interface, so as to obtain a memory first address required by writing in the EDID, wherein the video interface comprises a high-definition multimedia interface (HDMI) and a video graphic matrix (VGA).
The writing the EDID according to the memory head address specifically includes:
through I2And writing a write command into the ADV7850 chip by the C bus so that the ADV7850 chip writes the EDID according to the memory head address.
If the checksum is not the preset value, correcting the EDID;
enabling the DDC port to access the EDID.
If the checksum is a preset value, enabling the DDC port to access the EDID specifically includes:
if the checksum is a preset value, passing through I2The C bus writes an enable access command to the ADV7850 chip to cause a control register in the ADV7850 chip to be set to 1.
An embodiment of the present invention provides a controller, including:
a processing unit for prohibiting the DDC port of the display from accessing the SRAM of the ADV7850 chip, and enabling the I of the display2And switching an interface of the C bus to a storage space of the SRAM for storing the EDID of the external display equipment to obtain a memory initial address required by writing in the EDID, calculating a checksum of the EDID, and enabling the DDC port to access the EDID if the checksum is a preset value.
And the storage unit is used for writing the EDID according to the memory initial address.
The processing unit is specifically used for passing through I2The C bus writes an access prohibition command to the ADV7850 chip toSo that the control register in the ADV7850 chip is set to 0, via I2Writing a switching command to the ADV7850 chip by the C bus, and writing the I of the display2Switching an interface of a C bus to a storage space of the SRAM for storing EDID used by a video interface to acquire a memory head address required by writing in the EDID, wherein the video interface comprises a high-definition multimedia interface (HDMI) and a video graphic matrix (VGA), and if the checksum is a preset value, passing through I2The C bus writes an enable access command to the ADV7850 chip to cause a control register in the ADV7850 chip to be set to 1;
the memory cell, in particular for passing I2And writing a write command into the ADV7850 chip by the C bus so that the ADV7850 chip writes the EDID according to the memory head address.
And the processing unit is further configured to modify the EDID if the checksum is not the preset value, and enable the DDC port to access the EDID after the EDID is modified.
The embodiment of the invention provides a storage method and a storage device, wherein a controller prohibits a display data channel DDC port of a display from accessing a static random access memory SRAM of an ADV7850 chip, and then an I of the display is used2And switching the interface of the C bus to a storage space of the SRAM for storing the identification data EDID of the external display equipment to obtain a memory initial address required by writing the EDID, writing the EDID according to the memory initial address, finally, calculating the checksum of the EDID, and enabling the DDC port to access the EDID if the checksum is a preset value. By the scheme, the EDID of the display is directly stored in the ADV7850 chip of the display, so that an external storage device is omitted, and the hardware cost is saved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a first flowchart illustrating a storage method according to an embodiment of the present invention;
FIG. 2 is a second flowchart illustrating a storage method according to an embodiment of the invention;
fig. 3 is a first schematic structural diagram of a controller according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
EDID (extended display identification data) is standardized by the video electronics standards institute, and the display transmits standard data information to the computer host through a DDC (display data channel). The EDID is divided into 128 bytes and 256 bytes in terms of the amount of data information. It contains the basic parameters of the display device including vendor information, maximum image size, color settings, vendor presets, limits on frequency range, and a string of display names and serial numbers.
EDID data interchange is a standardized method for the display to communicate with the source device to illustrate its performance. This communication is intended to allow the display to transmit its own performance characteristics (e.g., native resolution) to the source device, allowing the device to generate video characteristics appropriate for the display requirements. The user does not need to manually adjust and can furthest improve the compatibility between the devices, thereby reducing the influence on the display image and the overall reliability of the system caused by incorrect setting and adjustment.
HDMI (high definition multimedia interface) is a fully digital image and sound transmission interface that can transmit uncompressed audio and video signals. HDMI can be used in set-top boxes, DVD players, personal computers, video players, integrated amplifiers, digital stereos and televisions. HDMI can convey audio frequency and audio-visual signal simultaneously, because audio frequency and video signal adopt same cable, has simplified the installation of system greatly.
The HDMI supports EDID, so the device with the HDMI has the characteristic of plug and play, the signal source and the display device can automatically perform negotiation, and the most suitable video/audio format can be automatically selected.
VGA (video graphics array) is a video transmission standard, has the advantages of high resolution, fast display speed, rich colors, etc., is widely applied in the field of color displays, and is suitable for various VGA interfaces of electronic and electric appliances, such as connecting wires of computers, high-definition DVDs, computer displays, projectors, high-definition digital televisions, rear projectors, plasma televisions, etc.
The ADV7850 chip is a high quality, single chip, multi-format video decoder and graphics digitizer integrated with a 4:1 multiplexed HDMI receiver. The chip supports four-way HDMI and analog input modes, thus allowing fast switching between analog video input and HDMI. The ADV7850 is internally provided with a four-input HDMI compatible receiver, supports all high-definition television formats up to 3D1080P60Hz and 2160P24Hz, can be switched between HDMI ports quickly, and can be used for synchronous measurement and state monitoring. Each HDMI port has a dedicated 5V detect and hot plug set pin. The HDMI receiver integrates internal EDID support and can be used in full power, power down and power down modes. The ADV7850 chip may be used in high definition televisions, set top boxes, audiovisual receivers, projectors, and video matrix switchers.
Example one
An embodiment of the present invention provides a storage method, as shown in fig. 1, when an ADV7850 chip of a display is powered on, the method includes:
s101, the controller prohibits a display data channel DDC port of the display from accessing a Static Random Access Memory (SRAM) of the ADV7850 chip.
The ADV7850 chip of the display comprises a control register, a status register and an SRAM, and the invention writes EDID into the SRAM by utilizing the SRAM space in the ADV7850 chip. When EDID is written, DDC ports need to be forbidden to pass through I2The C bus accesses the SRAM to prevent an external device from accessing the SRAM through the DDC port during writing EDID, and meanwhile, the correctness of writing EDID is guaranteed.
Specifically, the controller passes through I2The C bus writes an inhibit access command to the ADV7850 chip to cause a control register in the ADV7850 chip to be set to 0.
S102, the controller displays the I of the display2And switching the interface of the C bus to a storage space of the SRAM for storing the identification data EDID of the external display equipment so as to obtain a memory first address required by writing in the EDID.
The control register of SRAM in ADV7850 chip is set to 0, namely DDC port is forbidden to pass through I2After the C bus accesses the SRAM, EDID starts to be written into the SRAM.
The ADV7850 chip is a high quality, single chip, multi-format video decoder and graphics digitizer integrated with a 4:1 multiplexed HDMI receiver. The chip supports four paths of HDMI and one path of VGA, so that the supported EDID is divided into two groups of EDI, one group of EDID used by the HDMI and the other group of EDID used by the VGA. When the EDID is written in the SRAM, the memory head address needs to be acquired for different EDIDs.
Specifically, the controller passes through I2The C bus writes a switching command into the ADV7850 chip to change the I of the display2And the interface of the C bus is switched to a storage space of the SRAM, which is used for storing the EDID used by the video interface, so as to obtain a memory first address required by writing in the EDID, wherein the video interface comprises an HDMI and a VGA.
And S103, writing the EDID into the controller according to the memory first address.
And after the controller obtains the memory initial address of the EDID, writing the EDID according to the memory initial address, and writing the EDID to store the EDID in the SRAM in the ADV7850 chip.
And S104, the controller calculates the checksum of the EDID.
The checksum of the EDID is used for checking whether the data is illegally modified or whether transmission errors exist, the setting principle of the byte is that the sum of 128 bytes of the EDID is 00h or the sum of 256 bytes of the EDID is 00h, and if the sum exceeds the representation range of one byte in the summation process, the bit cannot be represented, the bit is automatically lost.
After the controller writes EDID in the SRAM of the ADV7850 chip, the checksum of the EDID is calculated to ensure the correctness of the EDID writing.
And S105, if the checksum is a preset value, enabling the DDC port to access the EDID by the controller.
Wherein, the preset value can be that the sum of the EDID bytes is 00 h.
Specifically, if the sum of the bytes of the EDID is 00h, the EDID in the SRAM of the ADV7850 chip is correctly stored, and the controller passes through I2And writing an enable access command into the ADV7850 chip by the C bus, and setting a control register in the ADV7850 chip to be 1, so that the signal source equipment accesses the ADV7850 chip through the DDC bus when the video interface cable is accessed, reads the EDID stored in the SRAM of the ADV7850 chip, and then sends a signal according to the resolution supported by the EDID.
The inventionThe embodiment provides a storage method, a controller forbids a display data channel DDC port of a display to access a static random access memory SRAM of an ADV7850 chip, and then the I of the display is2And switching the interface of the C bus to a storage space of the SRAM for storing the identification data EDID of the external display equipment to obtain a memory initial address required by writing the EDID, writing the EDID according to the memory initial address, finally, calculating the checksum of the EDID, and enabling the DDC port to access the EDID if the checksum is a preset value. By the scheme, the EDID of the display is directly stored in the ADV7850 chip of the display, so that an external storage device is omitted, and the hardware cost is saved.
Example two
An embodiment of the present invention provides a storage method, as shown in fig. 2, when an ADV7850 chip of a display is powered on, the method includes:
s201, the controller prohibits a display data channel DDC port of the display from accessing a Static Random Access Memory (SRAM) of the ADV7850 chip.
The ADV7850 chip of the display contains a control register, a status register and an SRAM. When the ADV7850 chip is powered on, the chip automatically performs hardware reset, namely, the contents in the control register, the status register and the SRAM are completely cleared.
The invention utilizes the SRAM space in the ADV7850 chip to write EDID into the SRAM. In order to ensure validity and correctness of writing EDID data, external equipment is prevented from accessing SRAM through DDC port, and when EDID is written, DDC port is first prohibited from passing I2The C-bus accesses the SRAM.
Specifically, the controller passes through I2The C bus writes an inhibit access command to the ADV7850 chip to cause a control register in the ADV7850 chip to be set to 0.
S202, the controller displays the I of the display2Interface switching of C bus to SRAM for storing external display device identification data EDIDAnd storing the space to obtain the memory first address required by writing the EDID.
After the control register of the SRAM in the ADV7850 chip is set to 0, the DDC port is forbidden to pass through I2And after the C bus accesses the SRAM, writing EDID into the SRAM, wherein when the EDID is written, the EDID is written according to the memory first address of the EDID.
The ADV7850 chip is a high quality, single chip, multi-format video decoder and graphics digitizer integrated with a 4:1 multiplexed HDMI receiver. The chip supports four paths of HDMI and one path of VGA, so that the supported EDID is divided into two groups of EDID, one group of HDMI is used for a high-definition multimedia interface, and the other group of HDMI is used for a video graphic matrix VGA.
Specifically, the controller passes through I2The C bus writes a switching command into the ADV7850 chip to change the I of the display2The interface of the C bus is switched to a storage space of the SRAM for storing the EDID used by the HDMI to obtain a memory first address required by writing the EDID used by the HDMI, and four paths of HDMI in the ADV7850 chip share one EDID memory first address;
or,
controller through I2The C bus writes a switching command into the ADV7850 chip to change the I of the display2And the interface of the C bus is switched to a storage space of the SRAM for storing the EDID used by the VGA to obtain the first memory address required by writing in the EDID used by the VGA.
Note that the controller will display the I of the display2The order in which the interface of the C bus is switched to the memory space of the SRAM for storing the EDID for HDMI and the controller switches the interface of the I2C bus of the display to the memory space of the SRAM for storing the EDID for VGA is determined according to actual use conditions, and the present invention is not limited thereto.
And S203, writing the EDID into the controller according to the memory first address.
And after the controller obtains the memory initial address of the EDID, the EDID is written according to the memory initial address, namely the EDID is stored in the SRAM in the ADV7850 chip.
Specifically, after the controller obtains the memory head address of the EDID used by the HDMI, the EDID used by the HDMI is written in according to the memory head address;
or,
and when the controller obtains the memory first address of the VGA used by the HDMI, the EDID used by the VGA is written in according to the memory first address.
And S204, the controller calculates the checksum of the EDID.
The checksum of the EDID is used for checking whether the data is illegally modified or whether transmission errors exist, the setting principle of the byte is that the sum of 128 bytes of the EDID is 00h or the sum of 256 bytes of the EDID is 00h, and if the sum exceeds the representation range of one byte in the summation process, the bit cannot be represented, the bit is automatically lost.
After the controller writes the EDID in the SRAM of the ADV7850 chip, the controller calculates the checksum of the EDID so as to ensure the correctness of the EDID.
It should be noted that, whether the EDID is for HDMI or VGA, the checksum thereof needs to be calculated.
S205, if the checksum is not the preset value, the controller corrects the EDID, and enables the DDC port to access the EDID after the EDID is corrected.
Wherein, the preset value can be that the sum of the EDID bytes is 00 h.
Specifically, if the EDID is illegally changed or transmission errors occur, the sum of EDID bytes is not 00h, the controller automatically corrects the EDID, the EDID is correctly stored in the SRAM of the ADV7850 chip after the EDID is corrected, and the controller enables the DDC port to access the EDID.
And S206, if the checksum is a preset value, enabling the DDC port to access the EDID by the controller.
Wherein, the preset value can be that the sum of the EDID bytes is 00 h.
Specifically, if the EDID is not illegally changed and has transmission errors in the writing process, the sum of the bytes is 00h, the EDID in the SRAM of the ADV7850 chip is correctly stored, and the controller passes through the I2And writing an enable access command into the ADV7850 chip by the C bus, and setting a control register in the ADV7850 chip to be 1, so that the signal source equipment accesses the ADV7850 chip through the DDC bus when the video interface cable is accessed, reads the EDID stored in the SRAM of the ADV7850 chip, and then sends a signal according to the resolution supported by the EDID.
The embodiment of the invention provides a storage method, wherein a controller prohibits a display data channel DDC port of a display from accessing a static random access memory SRAM of an ADV7850 chip, and then an I of the display is used2And switching the interface of the C bus to a storage space of the SRAM for storing the identification data EDID of the external display equipment to obtain a memory initial address required by writing the EDID, writing the EDID according to the memory initial address, finally, calculating the checksum of the EDID, and enabling the DDC port to access the EDID if the checksum is a preset value. By the scheme, the EDID of the display is directly stored in the ADV7850 chip of the display, so that an external storage device is omitted, and the hardware cost is saved.
EXAMPLE III
An embodiment of the present invention provides a controller, as shown in fig. 3, including:
a processing unit 10, configured to prohibit a DDC port of the display from accessing the SRAM of the ADV7850 chip, and set I of the display to the I2And switching an interface of the C bus to a storage space of the SRAM for storing the EDID of the external display equipment to obtain a memory initial address required by writing in the EDID, calculating a checksum of the EDID, and enabling the DDC port to access the EDID if the checksum is a preset value.
And the storage unit 11 is configured to write the EDID according to the memory first address.
Further, the processing unit is specifically used for passing through I2Writing an access disable command to the ADV7850 chip via the C bus such that a control register in the ADV7850 chip is set to 0, via I2Writing a switching command to the ADV7850 chip by the C bus, and writing the I of the display2Switching an interface of a C bus to a storage space of the SRAM for storing identification data EDID of external display equipment used by a video interface to acquire a memory initial address required by writing in the EDID, wherein the video interface comprises a high-definition multimedia interface (HDMI) and a video graphic matrix (VGA), and if the checksum is a preset value, passing through I2The C bus writes an enable access command to the ADV7850 chip to cause a control register in the ADV7850 chip to be set to 1.
Further, the memory cell is specifically used for passing through I2And writing a write command into the ADV7850 chip by the C bus so that the ADV7850 chip writes the EDID according to the memory head address.
Further, the processing unit is further configured to modify the EDID if the checksum is not the preset value, and enable the DDC port to access the EDID after the EDID is modified.
The embodiment of the invention provides a controller which mainly comprises a processing unit and a storage unit. The controller inhibits the DDC port of the display from accessing the SRAM of the ADV7850 chip, and then sets the I of the display to be zero2And switching the interface of the C bus to a storage space of the SRAM for storing the identification data EDID of the external display equipment to obtain a memory initial address required by writing the EDID, writing the EDID according to the memory initial address, finally, calculating the checksum of the EDID, and enabling the DDC port to access the EDID if the checksum is a preset value. By the scheme, the EDID of the display is directly stored in the ADV7850 chip of the display, so that an external storage device is omitted, and the hardware cost is saved.
It will be clear to those skilled in the art that, for convenience and simplicity of description, the foregoing division of the functional modules is merely used as an example, and in practical applications, the above function distribution may be performed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to perform all or part of the above described functions. For the specific working processes of the system, the apparatus and the unit described above, reference may be made to the corresponding processes in the foregoing method embodiments, and details are not described here again.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the modules or units is only one logical division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims (9)

1. A storage method, when an ADV7850 chip of a display is powered on, the method comprising:
forbidding a display data channel DDC port of the display to access a Static Random Access Memory (SRAM) of the ADV7850 chip;
through I2Writing a switching command to the ADV7850 chip by the C bus, and writing the I of the display2Switching the interface of the C bus to a storage space of the SRAM for storing EDID used by the video interface to obtain a memory first address required by writing in the EDID, wherein the videoThe frequency interface comprises a high-definition multimedia interface HDMI and a video graphic matrix VGA;
writing the EDID according to the memory initial address;
calculating a checksum of the EDID;
and if the checksum is a preset value, enabling the DDC port to access the EDID.
2. The method according to claim 1, wherein the step of prohibiting the DDC port of the display from accessing the SRAM of the ADV7850 chip comprises:
through I2Writing an access prohibition command to the ADV7850 chip by the C bus so that a control register in the ADV7850 chip is set to 0 and a Display Data Channel (DDC) port of the display is prohibited from passing through the I2C, accessing a Static Random Access Memory (SRAM) of the ADV7850 chip.
3. The storage method according to claim 1, wherein the writing the EDID according to the memory head address specifically includes:
through I2And writing a write command into the ADV7850 chip by the C bus so that the ADV7850 chip writes the EDID according to the memory head address.
4. The storage method according to claim 1,
if the checksum is not the preset value, correcting the EDID;
enabling the DDC port to access the EDID.
5. The storage method according to claim 1, wherein if the checksum is a preset value, enabling the DDC port to access the EDID specifically comprises:
if the checksum is a preset value, passing through I2Write enable of C bus to ADV7850 chipA command is accessed to cause a control register in the ADV7850 chip to be set to 1.
6. A controller, comprising:
a processing unit for inhibiting the display data channel DDC port of the display from accessing the SRAM of the ADV7850 chip via I2Writing a switching command to the ADV7850 chip by the C bus, and writing the I of the display2Switching an interface of a C bus to a storage space of the SRAM, wherein the storage space is used for storing EDID used by a video interface, so as to obtain a memory initial address required by writing in the EDID, the video interface comprises a high-definition multimedia interface (HDMI) and a video graphics matrix (VGA), calculating a checksum of the EDID, and enabling the DDC port to access the EDID if the checksum is a preset value;
and the storage unit is used for writing the EDID according to the memory initial address.
7. The controller of claim 6,
the processing unit is specifically used for passing through I2Writing an access prohibition command into the ADV7850 chip by the C bus so that a control register in the ADV7850 chip is set to be 0, and if the checksum is a preset value, passing through I2The C bus writes an enable access command to the ADV7850 chip to cause a control register in the ADV7850 chip to be set to 1.
8. The controller of claim 6,
the memory cell, in particular for passing I2And writing a write command into the ADV7850 chip by the C bus so that the ADV7850 chip writes the EDID according to the memory head address.
9. The controller of claim 6,
and the processing unit is further configured to modify the EDID if the checksum is not the preset value, and enable the DDC port to access the EDID after the EDID is modified.
CN201310465949.4A 2013-09-30 2013-09-30 A kind of storage means and device Active CN103500565B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310465949.4A CN103500565B (en) 2013-09-30 2013-09-30 A kind of storage means and device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310465949.4A CN103500565B (en) 2013-09-30 2013-09-30 A kind of storage means and device

Publications (2)

Publication Number Publication Date
CN103500565A CN103500565A (en) 2014-01-08
CN103500565B true CN103500565B (en) 2016-06-08

Family

ID=49865769

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310465949.4A Active CN103500565B (en) 2013-09-30 2013-09-30 A kind of storage means and device

Country Status (1)

Country Link
CN (1) CN103500565B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104092959A (en) * 2014-07-15 2014-10-08 山东超越数控电子有限公司 DVI video signal switching achieving method
CN106657854A (en) * 2016-12-05 2017-05-10 广州视源电子科技股份有限公司 Method and system for changing extended display identification data information
CN111783113A (en) * 2020-06-22 2020-10-16 济南浪潮高新科技投资发展有限公司 Data access authority control method based on SAS Controller
CN113592703A (en) * 2021-07-30 2021-11-02 北京小米移动软件有限公司 Display device, display device control method and device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003029729A (en) * 2001-07-17 2003-01-31 Nec Mitsubishi Denki Visual Systems Kk Device and method for controlling input channel switching for display monitor
CN101355672A (en) * 2007-07-26 2009-01-28 株式会社东芝 Image processing device and image processing method
CN101841682A (en) * 2009-03-16 2010-09-22 三星电子株式会社 Handle the Apparatus for () and method therefor of digital interface signal
CN101883204A (en) * 2009-05-05 2010-11-10 康佳集团股份有限公司 TV EDID self-checking and updating method and TV core plate

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1917032A (en) * 2005-08-18 2007-02-21 明基电通股份有限公司 Display screen, and method for reading and writing extension of displaying identified data
CN101051434A (en) * 2006-04-05 2007-10-10 深圳Tcl新技术有限公司 Copying and detecting method for flat panel display product EDID
KR100744077B1 (en) * 2006-08-21 2007-07-30 옵티시스 주식회사 Ddc(display data channel) communication module
CN102110473B (en) * 2011-01-05 2013-06-26 深圳创维－Rgb电子有限公司 Method and system for programming and checking EDID (Extended Display Identification Data) of display device
CN102385849A (en) * 2011-11-29 2012-03-21 黄冈新北环电子科技有限公司 Intelligent EDID (Extended Display Identification Data) burning method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003029729A (en) * 2001-07-17 2003-01-31 Nec Mitsubishi Denki Visual Systems Kk Device and method for controlling input channel switching for display monitor
CN101355672A (en) * 2007-07-26 2009-01-28 株式会社东芝 Image processing device and image processing method
CN101841682A (en) * 2009-03-16 2010-09-22 三星电子株式会社 Handle the Apparatus for () and method therefor of digital interface signal
CN101883204A (en) * 2009-05-05 2010-11-10 康佳集团股份有限公司 TV EDID self-checking and updating method and TV core plate

Also Published As

Publication number Publication date
CN103500565A (en) 2014-01-08

Similar Documents

Publication Publication Date Title
US9418618B2 (en) Video signal transmission apparatus, play system and video signal transmission method
CN107003968B (en) Virtual display output port configuration
EP2660808A2 (en) Transmission of alternative content over standard device connectors
US9554179B2 (en) Method and apparatus for transmitting and receiving data using HDMI
US7818466B2 (en) HDMI controller circuit for transmitting digital data to compatible audio device using address decoder where values are written to registers of sub-circuits
CN103500565B (en) A kind of storage means and device
CN105308977A (en) Transmission device, high-dynamic range image data transmission method, reception device, high-dynamic range image data reception method, and program
CN103686314A (en) Demultiplex device and method adopting HD (high definition) video channel to transmit SD (standard definition) videos
CN109120973B (en) Method, device and storage medium for rewriting EDID data
CN107589931A (en) Multi-screen display method, device and the electronic equipment with split screen display available function
CN103546741A (en) Hot plugging detection method and device
CN101257591A (en) Digital multimedia receiving apparatus and extending display identification data reading method thereof
US10607564B2 (en) Signal relaying device and signal relaying method
CN203522947U (en) Multi-path HDMI (high-definition multimedia interface) signal source output circuit and HDMI signal source device
US9756384B2 (en) Electronic device with different processing modes
US10319340B2 (en) Real-time color mapping system and method
US10917603B2 (en) Interface circuit, transmission system, and transmission direction control method
KR101101815B1 (en) Display apparatus and control method of the same
WO2019146566A1 (en) Semiconductor device, display device, graphic processor, electronic device, and image processing method
CN201557195U (en) High-definition player
CN213846895U (en) HDMI signal adjusting device
EP4303857A1 (en) Electronic device supporting multi-edid read operation and operating method
KR102346000B1 (en) Electronic apparatus and contlolling method thereof
US20240073355A1 (en) Sink device, source device, and method for controlling the same
CN100592771C (en) Digital film playing system with the DVI output content protection

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
PP01 Preservation of patent right

Effective date of registration: 20170721

Granted publication date: 20160608

PP01 Preservation of patent right
PD01 Discharge of preservation of patent
PD01 Discharge of preservation of patent

Date of cancellation: 20200721

Granted publication date: 20160608

CP03 Change of name, title or address
CP03 Change of name, title or address

Address after: 300453 Tianjin Binhai New Area, Tianjin Eco-city, No. 126 Animation and Animation Center Road, Area B1, Second Floor 201-427

Patentee after: Xinle Visual Intelligent Electronic Technology (Tianjin) Co.,Ltd.

Address before: 300467 Tianjin Binhai New Area, Tianjin ecological city animation Middle Road, building, No. two, B1 District, 201-427

Patentee before: LE SHI ZHI XIN ELECTRONIC TECHNOLOGY (TIANJIN) Ltd.

Address after: Room 301-1, Room 301-3, Area B2, Animation Building, No. 126 Animation Road, Zhongxin Eco-city, Tianjin Binhai New Area, Tianjin

Patentee after: LE SHI ZHI XIN ELECTRONIC TECHNOLOGY (TIANJIN) Ltd.

Address before: 300453 Tianjin Binhai New Area, Tianjin Eco-city, No. 126 Animation and Animation Center Road, Area B1, Second Floor 201-427

Patentee before: Xinle Visual Intelligent Electronic Technology (Tianjin) Co.,Ltd.

PP01 Preservation of patent right
PP01 Preservation of patent right

Effective date of registration: 20210201

Granted publication date: 20160608