CN103490654B - Fault-tolerant control method of chained mode grid-connected inverter based on dual-zero-sequence-voltage injection - Google Patents

Fault-tolerant control method of chained mode grid-connected inverter based on dual-zero-sequence-voltage injection Download PDF

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CN103490654B
CN103490654B CN201310479229.3A CN201310479229A CN103490654B CN 103490654 B CN103490654 B CN 103490654B CN 201310479229 A CN201310479229 A CN 201310479229A CN 103490654 B CN103490654 B CN 103490654B
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voltage
phase
fault
direct current
tolerant
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CN103490654A (en
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季振东
赵剑锋
朱泽安
刘巍
孙毅超
姚晓君
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Southeast University
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Abstract

The invention discloses a fault-tolerant control method of a chained mode grid-connected inverter based on dual-zero-sequence-voltage injection. The fault-tolerant control method can comprise the following steps of (1) direct current side optimization and control: optimizing and calculating a direct current side command value on the basis of traditional positive sequence current decoupling control; (2) balance control of inter-phase direct current side voltage: calculating a zero sequence voltage injection command value for balancing the inter-phase direct current side by virtue of a formula; (3) fault-tolerant control: calculating a zero sequence voltage injection command value for the fault-tolerant control by virtue of a formula; (4) balance control and the pulse generation on the inter-phase direct current side. According to the method, the balancing and fault-tolerant control of the direct current side voltage are comprehensively considered, the output current cannot be suddenly changed when a fault unit is processed, and the inter-phase power regulation and the voltage balancing of the direct current side can be rapidly realized; and meanwhile, by optimizing a direct current side voltage command value, the fault-tolerant capacity of the chained mode grid-connected inverter is enhanced.

Description

The chain type combining inverter fault tolerant control method of a kind of pair of injected zero-sequence voltage
Technical field
The invention belongs to the applied technical field of high-voltage and high-power power electronic technology in electric power system, relate to a kind of fault tolerant control method of chained convert device.
Background technology
H bridge chain structure becomes the focus of research in fields such as parallel network reverse, energy storage, electric power electric transformers, it has great importance for cooperation regenerative resource large-scale grid connection, extensive energy storage and enhancing stability of power system.The combining inverter device of this type can access high-voltage fence by transformer-free, structure is easy to modular implementation, and has comparatively low switching losses and harmonic wave, but the switching device Numerous used, along with the increase of chain unit number, failure rate also can improve.
Faults-tolerant control about H bridge chain structure has some processing methods.Have document to propose in chain type STATCOM, use symmetrical the method for bypass, carry out bypass process to the non-faulting unit of same layer, this proposes very high requirement to device redundancey degree, is not suitable for the process of more cell failure.Also have document to propose by only doing the method increasing process to the unit output voltage of fault phase, fault-tolerant ability improves than symmetrical bypass, but still is not suitable for the more situation of single-phase fault unit.The central point deflection method that research is concentrated the most can be used for the faults-tolerant control of high voltage converter, asymmetric phase voltage is exported when each mutually remaining unit number is unequal, still retention wire voltage is consistent, but the method is unanimously considered based on each unit output voltage, do not take into account alternate flow of power, be unfavorable for the balance of DC voltage, be not suitable for the faults-tolerant control of combining inverter.
Summary of the invention
Goal of the invention: for above-mentioned Problems existing, the object of the invention is to propose a kind of fault tolerant control method for chain type combining inverter, current break can be there is not in the method when handling failure unit, realize seamless switching, realize the balance of voltage of alternate power adjustments and DC side fast, thus strengthen the fault-tolerant ability of chain type combining inverter while assurance device stable operation.
Technical scheme: for achieving the above object, the technical solution used in the present invention is a kind of chain type combining inverter fault tolerant control method optimized based on two injected zero-sequence voltage and DC side, and the method comprises the steps:
Step 1: DC side optimal control
Step 1.1: the output voltage modulating wave utilizing each phase calculate the overall DC side voltage instruction value after optimal control
Step 1.2: by total DC voltage average and instruction magnitude of voltage after comparing, through proportional and integral controller, obtain instruction active current value
Step 1.3: utilize the positive sequence component in system voltage and electric current to convert through abc/dq, even if three phase static coordinate is transformed to the conversion of two cordic phase rotators, d, q axle component e of the system voltage obtained and electric current d, e q, i d, i q, by calculating each phase output voltage modulating wave
Step 2: alternate DC side balance controls;
Step 2.1: calculate each phase DC voltage mean value respectively with total DC voltage average through proportional and integral controller after comparing, and be multiplied by each normal unit number run mutually, obtain each active power Δ P needing to adjust mutually a, Δ P b, Δ P c;
Step 2.2: respectively need the active power Δ P adjusted mutually a, Δ P b, Δ P cΔ P a, Δ P b, Δ P ccarry out abc/ α β to convert, namely three phase static coordinate is transformed to the change of two-phase static coordinate, obtains the active power adjustment amount Δ P under α β coordinate system α, Δ P β;
Step 2.3: utilize Δ P α, Δ P βand inverter exports the amplitude of forward-order current, calculate the required balance residual voltage injected amplitude, phase place;
Step 3: faults-tolerant control
Step 3.1: each phase fault unit number n when obtaining generating unit fault by detecting a, n b, n cand the amplitude of positive sequence voltage that exports of inverter and phase angle V p,
Step 3.2: each phase fault unit number n when utilizing generating unit fault a, n b, n cwith amplitude and the phase angle V of the positive sequence voltage of inverter output p, calculate the required fault-tolerant residual voltage injected amplitude and phase place;
Step 4: mutually, DC side balance controls and pulse generate
Step 4.1: each phase output voltage modulating wave the output voltage modulating wave u of unit is obtained by DC side balance control module in mutually ai, u bi, u ci;
Step 4.2: the pulse signal generating each switching device eventually through phase-shifting carrier wave Pulse width modulation module.
Beneficial effect:
(1) when realizing chain type combining inverter bypass trouble unit, grid-connected current is without impact, reaches seamless switching;
(2) balance of voltage of alternate power adjustments and DC side is realized under fault fast;
(3) carry out optimal control to DC voltage, widening can the quantity of by-pass unit, thus enhances the fault-tolerant ability of chain type combining inverter;
(4) algorithm adopts dq rotating coordinate system, realizes fast simple and convenient, clear physics conception, can the fine astatic control that must realize current on line side.
Accompanying drawing explanation
Fig. 1 chain type combining inverter topological diagram;
The topology diagram of Fig. 2 unit module;
Fig. 3 master control block diagram.
Embodiment
The present invention is mainly used in chain H bridge combining inverter faults-tolerant control, and Fig. 1 is the chain type combining inverter structure chart of Y-connection, to be wherein respectively single-phasely in series by N number of H-bridge unit, adopts Y-connection between three-phase.Fig. 2 is the topology diagram of unit module, and each unit is made up of bypass mechanism (I part), H bridge module (II part), isolation DC/DC conversion module (III part).
A kind of chain type combining inverter fault tolerant control method optimized based on two injected zero-sequence voltage and DC side provided by the invention, the method comprises the steps:
Step 1: DC side optimal control
Step 1.1: the output voltage modulating wave utilizing each phase calculate the overall DC side voltage instruction value after optimal control
Step 1.2: by total DC voltage average and instruction magnitude of voltage after comparing, through proportional and integral controller, obtain instruction active current value
Step 1.3: utilize the positive sequence component in system voltage and electric current through d, q axle component e of abc/dq conversion (three phase static coordinate the is transformed to two cordic phase rotators) system voltage that obtains and electric current d, e q, i d, i q, by calculating each phase output voltage modulating wave
Step 2: alternate DC side balance controls;
Step 2.1: calculate each phase DC voltage mean value respectively with total DC voltage average through proportional and integral controller after comparing, and be multiplied by each normal unit number run mutually, obtain each active power Δ P needing to adjust mutually a, Δ P b, Δ P c;
Step 2.2: respectively need the active power Δ P adjusted mutually a, Δ P b, Δ P cΔ P a, Δ P b, Δ P ccarry out abc/ α β and convert the active power adjustment amount Δ P that (three phase static coordinate is transformed to two-phase static coordinate) obtain under α β coordinate system α, Δ P β;
Step 2.3: utilize Δ P α, Δ P βand inverter exports the amplitude of forward-order current, calculate the required balance residual voltage injected amplitude, phase place;
Step 3: faults-tolerant control
Step 3.1: each phase fault unit number n when obtaining generating unit fault by detecting a, n b, n cand the amplitude of positive sequence voltage that exports of inverter and phase angle V p,
Step 3.2: each phase fault unit number n when utilizing generating unit fault a, n b, n cwith amplitude and the phase angle V of the positive sequence voltage of inverter output p, calculate the required fault-tolerant residual voltage injected amplitude and phase place;
Step 4: mutually, DC side balance controls and pulse generate
Step 4.1: each phase output voltage modulating wave the output voltage modulating wave u of unit is obtained by DC side balance control module in mutually ai, u bi, u ci;
Step 4.2: eventually through phase-shifting carrier wave PWM(pulse width modulation) pulse signal of each switching device of CMOS macro cell.
Suppose with electrical network A phase voltage for reference; V p, for amplitude and the phase angle of the positive sequence voltage of inverter output; V z, the amplitude for the residual voltage of each phase power adjustments and dc-voltage balance and phase angle; I pfor the amplitude of the forward-order current that inverter exports; n a, n b, n cbe respectively the trouble unit quantity of each phase, thus by the non-faulting unit output voltage instantaneous value u of each phase ai, u bi, u ciand each phase current instantaneous value i a, i b, i cbe expressed as:
i A = I p sin ( ωt ) i B = I p sin ( ωt - 2 3 π ) i C = I p sin ( ωt - 2 3 π ) - - - ( 2 )
So, inverter respectively produce mutually average power be expressed as:
From formula (3), the active power that each phase positive sequence voltage component produces is equal, and it is zero that zero sequence voltage component injects the active power three-phase sum produced, and does not have an impact to gross power, and by regulating V zwith size, can regulate each single-phase active power.When load or the power balance of unit, each phase active power is distributed and can be expressed as:
P A n - n A = P B n - n B = P C n - n C - - - ( 4 )
Thus calculate desirable zero-sequence component injection (i.e. the zero-sequence component of faults-tolerant control) according to formula (3) and (4):
Wherein,
g ( x ) = 1 x < 0 0 x > 0 - - - ( 7 )
In alternate DC side balance control module with be calculated as follows:
The changed power that injected zero-sequence voltage produces such as formula (3), the active power that residual voltage is wherein produced after abc/ α β converts, convolution (8) thus obtain V zand computational methods (alternate DC side balance residual voltage)
Wherein, g (x)definition cotype (7).
The method of DC side optimal control is the fixing direct voltage command value of use one in normal condition; When generating unit fault, choose DC side command voltage to ensure that each unit ovennodulation does not occur, and meet the condition of formula (11):
V DC min &le; U dc * &le; V DC max - - - ( 11 )
Concrete computational methods are:
By adjustment direct current command voltage value by phase command voltage output level be adjusted to n-n according to peak value x-1 and n-n xbetween, and choose the maximum in three-phase.
As shown in Figure 3, the output of DC side optimal control module by the injected zero-sequence voltage amount that alternate dc-voltage balance control module exports with the injected zero-sequence voltage amount of fault-tolerant control module input two injected zero-sequence voltage corrections, thus obtain the output voltage modulating wave of each phase the output voltage modulating wave u of unit is drawn again by DC side balance control module in mutually ai, u bi, u ci, finally by the pulse signal of each switching device of phase-shifting carrier wave PWM CMOS macro cell.
In Fig. 3, dotted line frame I is DC side optimal control block diagram, selects different DC voltage command value according to invertor operation in different situations that are normal or generating unit fault and by forward-order current uneoupled control output voltage modulating wave
In Fig. 3, dotted line frame II is alternate DC side balance control block diagram, exports the injected zero-sequence voltage amount controlled for the balance of alternate DC voltage
In Fig. 3, dotted line frame III is faults-tolerant control block diagram, exports the injected zero-sequence voltage amount being used for faults-tolerant control
In Fig. 3, dotted line frame IV is that interior DC side balance controls and pulse generate block diagram mutually, output switch device pulse signal.

Claims (1)

1. a chain type combining inverter fault tolerant control method for two injected zero-sequence voltage, it is characterized in that, the method comprises the steps:
Step 1: DC side optimal control;
Step 1.1: the output voltage modulating wave utilizing each phase calculate the overall DC side voltage instruction value after optimal control
Step 1.2: by total DC voltage average and instruction magnitude of voltage after comparing, through proportional and integral controller, obtain instruction active current value
Step 1.3: utilize the positive sequence component in system voltage and electric current to convert through abc/dq, d, q axle component e of the system voltage that the conversion that namely three phase static coordinate is transformed to two cordic phase rotators obtains and electric current d, e q, i d, i q, by calculating each phase output voltage modulating wave
Step 2: alternate DC side balance controls;
Step 2.1: calculate each phase DC voltage mean value respectively with total DC voltage average through proportional and integral controller after comparing, and be multiplied by each normal unit number run mutually, obtain each active power Δ P needing to adjust mutually a, Δ P b, Δ P c;
Step 2.2: respectively need the active power Δ P adjusted mutually a, Δ P b, Δ P ccarry out abc/ α β to convert, the change that namely three phase static coordinate is transformed to two-phase static coordinate obtains the active power adjustment amount Δ P under α β coordinate system α, Δ P β;
Step 2.3: utilize Δ P α, Δ P βand inverter exports the amplitude of forward-order current, calculate the required balance residual voltage injected amplitude, phase place;
Step 3: faults-tolerant control
Step 3.1: each phase fault unit number n when obtaining generating unit fault by detecting a, n b, n cand the amplitude of positive sequence voltage that exports of inverter and phase angle
Step 3.2: each phase fault unit number n when utilizing generating unit fault a, n b, n cwith amplitude and the phase angle of the positive sequence voltage of inverter output calculate the required fault-tolerant residual voltage injected amplitude and phase place;
Step 4: mutually, DC side balance controls and pulse generate
Step 4.1: each phase output voltage modulating wave the output voltage modulating wave u of unit is obtained by DC side balance control module in mutually ai, u bi, u ci;
Step 4.2: the pulse signal generating each switching device eventually through phase-shifting carrier wave Pulse width modulation module.
CN201310479229.3A 2013-10-14 2013-10-14 Fault-tolerant control method of chained mode grid-connected inverter based on dual-zero-sequence-voltage injection Expired - Fee Related CN103490654B (en)

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CN105375508B (en) * 2015-09-16 2018-06-19 南京工程学院 The control method of Cascade-type photovoltaic grid-connected inverter low voltage crossing
CN105471312B (en) * 2015-12-22 2018-01-19 合肥工业大学 The alternate method for controlling power balance of three-phase cascaded H-bridges photovoltaic combining inverter
CN105577008A (en) * 2015-12-31 2016-05-11 东南大学 Three-phase rectification type power electronic transformer and DC voltage coordinative control method thereof
CN105870944B (en) * 2016-03-30 2018-08-07 国网智能电网研究院 A kind of alternate Power balance control method of electric power electric transformer
CN106487258A (en) * 2016-11-29 2017-03-08 西安奥特迅电力电子技术有限公司 A kind of control method of the three level neutral-point potential balance tape verifying corrections based on injected zero-sequence voltage
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CN110336477B (en) * 2019-07-31 2021-04-13 天津大学 Closed-loop zero-sequence voltage injection method applied to cascaded H-bridge converter
CN110336476B (en) * 2019-07-31 2020-11-27 天津大学 Closed-loop zero-sequence voltage optimization injection method for cascaded H-bridge converter
CN111600494A (en) * 2019-08-09 2020-08-28 青岛鼎信通讯股份有限公司 Control method for improving running performance of power electronic transformer after redundancy
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102185331A (en) * 2011-04-28 2011-09-14 中国电力科学研究院 Zero-sequence-voltage-based current conversion chain average DC voltage control method
CN102638049A (en) * 2012-04-10 2012-08-15 西安交通大学 Direct-current bus inter-phase voltage balancing control method for chained type triangular connection STATCOM (Static Synchronous Compensator)
CN103219908A (en) * 2013-03-26 2013-07-24 东南大学 Method for controlling balance of direct current side of cascaded grid-connected inverter based on zero sequence and negative sequence voltage injection

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102185331A (en) * 2011-04-28 2011-09-14 中国电力科学研究院 Zero-sequence-voltage-based current conversion chain average DC voltage control method
CN102638049A (en) * 2012-04-10 2012-08-15 西安交通大学 Direct-current bus inter-phase voltage balancing control method for chained type triangular connection STATCOM (Static Synchronous Compensator)
CN103219908A (en) * 2013-03-26 2013-07-24 东南大学 Method for controlling balance of direct current side of cascaded grid-connected inverter based on zero sequence and negative sequence voltage injection

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