CN103489388B - Gate drive apparatus - Google Patents
Gate drive apparatus Download PDFInfo
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- CN103489388B CN103489388B CN201210190794.3A CN201210190794A CN103489388B CN 103489388 B CN103489388 B CN 103489388B CN 201210190794 A CN201210190794 A CN 201210190794A CN 103489388 B CN103489388 B CN 103489388B
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Abstract
A kind of gate drive apparatus, including first grid driving chip and N number of second grid driving chip, N is positive integer.First grid driving chip has input pin and the first current output pin, and first grid driving chip receives with reference to electric signal by input pin and produces reference current, the first current output pin output reference current according to reference to electric signal.Each second grid driving chip has electric current input pin and the second current output pin, and is received reference current and by input pin output reference current by electric current input pin.Wherein, first grid driving chip and second grid driving chip also produce at least one first output signal and the most N number of second output signal respectively according to reference current.
Description
Technical field
The invention relates to a kind of gate drive apparatus.
Background technology
Refer to Fig. 1, Fig. 1 and illustrate the block chart of known gate drive apparatus 100.Known gate drive apparatus 100
Grid drive chip 110 and 120 including concatenation.Grid drive chip 110 has input pin INPAD1 and output connecting pin
OUPAD1, grid drive chip 120 then has input pin INPAD2 and output connecting pin OUPAD2.Wherein, grid drive chip
The output connecting pin OUPAD1 of 110 is coupled to the input pin INPAD2 of grid drive chip 120, grid drive chip 110 defeated
Enter pin INPAD1 and then receive voltage VB.Bias circuit 112 in grid drive chip 110 is connect by input pin INPAD1
Receive voltage VB and make the mac function circuit 111 of grid drive chip 110 produce output signal (raster data model according to voltage VB
Signal) GD1.It addition, in grid drive chip 110, input pin INPAD1 and output connecting pin OUPAD1 is interconnective,
And thereby by voltage VB by the bias plasma inputting pin INPAD1 and being sent to via output connecting pin OUPAD1 grid drive chip 120
Road 122.
Mac function circuit 111 and 112 meeting foundation bias circuit 112 and 122 respectively is according to its received voltage
VB and electric current I1 and I2 that produce respectively produces output signal GD1 and GD2 respectively.But, due to grid drive chip
The difference of 110 and 120 process parameter, bias circuit 111 and 112 the electric current I1 that produces respectively according to voltage VB with
And I2 is likely to be inconsistent, therefore, mac function circuit 111 and 112 produces respectively output signal GD1 and
GD2 also can produce inconsistent phenomenon.
Summary of the invention
The present invention provides multiple gate drive apparatus so that it is in multiple grid drive chip not because of the difference between processing procedure
Produce the output signal of different qualities.
The present invention proposes a kind of gate drive apparatus, drives core including first grid driving chip and N number of second grid
Sheet, N is positive integer.First grid driving chip has input pin and the first current output pin, and first grid drives core
Sheet receives with reference to electric signal by input pin and produces reference current, the first current output pin according to reference to electric signal
Output reference current.Second grid driving chip coupled in series, each second grid driving chip have electric current input pin and
Second current output pin, and received reference current and by input pin output reference current, the first order by electric current input pin
Second grid driving chip electric current input pin be coupled to the first current output pin to receive reference current.Wherein,
One grid drive chip and second grid driving chip also produce at least one first output signal respectively according to reference current
And the most N number of second output signal.
The present invention also proposes a kind of gate drive apparatus, including multiple grid drive chip and current generator.Each grid
Pole driving chip has shared pin, and the shared pin of grid drive chip is mutually coupled.One end of current generator is coupled to
The shared pin of each grid drive chip, the other end of current generator is coupled to reference to ground voltage, wherein, each raster data model
Chip produces at least one output signal, and, each grid drive chip makes output signal draw high to driving according to control signal
Voltage or make current generator drag down to output signal to reference to ground voltage.
Based on above-mentioned, the present invention is by providing the reference electricity that the multiple grid drive chip in gate drive apparatus are identical
Stream, and make each gate drive apparatus according to the identical reference current received to produce output signal.Consequently, it is possible to each grid
The variation of the process parameter between driving chip will not impact the characteristic of output signal, effectively promotes gate drive apparatus and is produced
The uniformity of raw multiple output signals.
For the features described above of the present invention and advantage can be become apparent, special embodiment below, and coordinate institute's accompanying drawings
It is described in detail below.
Accompanying drawing explanation
Fig. 1 illustrates the block chart of known gate drive apparatus 100.
Fig. 2 illustrates the schematic diagram of the gate drive apparatus 200 of one embodiment of the invention.
Fig. 3 A illustrates the schematic diagram of the gate drive apparatus 300 of another embodiment of the present invention.
Fig. 3 B～3C illustrates multiple embodiments of the gate drive apparatus 300 of the embodiment of the present invention respectively.
Fig. 4 A illustrates the schematic diagram of the gate drive apparatus 400 of another embodiment of the present invention.
Fig. 4 B～4C illustrates multiple embodiments of the gate drive apparatus 400 of the embodiment of the present invention respectively.
Fig. 5 A illustrates an embodiment of the first grid driving chip of the gate drive apparatus of the embodiment of the present invention.
Fig. 5 B illustrates an embodiment of the selector 512 of the embodiment of the present invention.
Fig. 6 illustrates the schematic diagram of the gate drive apparatus 600 of yet another embodiment of the invention.
Fig. 7 A illustrates the schematic diagram of the gate drive apparatus 700 of a present invention more embodiment.
Fig. 7 B illustrates an embodiment of the programmable reference electric signal generator 701 of the embodiment of the present invention.
Fig. 8 A illustrates the schematic diagram of the gate drive apparatus 800 of the embodiment of the present invention.
Fig. 8 B～8E illustrates the different embodiments of the gate drive apparatus 800 of the embodiment of the present invention respectively.
Fig. 9 A～9C illustrates the different embodiments of the gate drive apparatus 900 of the embodiment of the present invention respectively.
[main element label declaration]
100,200,300,400,500,600,700,800,900: gate drive apparatus
110,120,810～8N0,910,920: grid drive chip
811～813,911～91N, 921～92N: gate driver circuit
111: mac function circuit 112,122: bias circuit
210,310,410,510,610,710: first grid driving chip
221～22N, 321,421,521: second grid driving chip
211,2211～22N1,311,3211,411,4211,511,611,6211: mac function circuit
512: selector 701: programmable reference electric signal generator
7011: order buffer 7012: with reference to electric signal generator
801,901: current generator 811,821: controller
8111～811N, 9111～911M: sub-drive circuit
OT: outfan R: resistance
SGD11: sub-output signal CT1: sub-controller
VGH, VGHM, VGL: driving voltage INPAD1～INPADN: input pin
OUPAD1～OUPADN: output connecting pin ES1, VS1: with reference to electric signal
IR: reference current GD1～GDN: output signal
VB: voltage TRIM: adjust signal
MR11, MR12, MR21, MR22: current mirror
IS1, IS2: with reference to electric signal generator
T1～T6, TN1, TN2, TP1, TP2: transistor
GND: with reference to ground voltage SW1～SW4: switch
TL1: transfer wire SPIS: programmable interface is to receive command signal
EPAD1～EPADN: share pin
Detailed description of the invention
Refer to the schematic diagram that Fig. 2, Fig. 2 illustrate the gate drive apparatus 200 of one embodiment of the invention.Gate drive apparatus
200 include first grid driving chip 210 and second grid driving chip 221～22N.First grid driving chip 210 has
Having input pin INPAD1 and current output pin OUPAD1, second grid driving chip 221～22N is then respectively provided with electric current
Input pin INPAD2～INPADN and current output pin OUPAD2～OUPADN.In the present embodiment, first grid drives
Dynamic chip 210 is received with reference to electric signal ES1 by its input pin INPAD1.First grid driving chip 210 foundation ginseng
Examine electric signal ES1 and produce reference current IR.Wherein, reference current IR is transferred into the electric current of first grid driving chip 210
Output connecting pin OUPAD1, reference current IR and by current output pin OUPAD1 be transferred into the first order second grid drive
Chip 221.
First grid driving chip 210 also includes mac function circuit 211, and reference current IR is except being transferred into electric current output
Outside pin OUPAD1, also it is transferred into mac function circuit 211.Mac function circuit 211 is then according to the reference current received
IR produces output signal GD1.Specifically a little illustrating, output signal GD1 produced by first grid driving chip 210 is permissible
It is used as the gate drive signal of display floater.It is to say, output signal GD1 be one for driving in display floater
The raster data model high voltage of thin film transistor (TFT) is with the signal of transition between gate pole low voltage level.When output signal GD1 is by grid
When driving high voltage transition to grid low-voltage level, mac function circuit 211 can drag down output according to reference current IR
The voltage level of signal GD1.
Subsidiary one carries, and mac function circuit 211 can produce one or more output signals GD1.
The electric current input pin INPAD2 of second grid driving chip 221 is defeated with the electric current of first grid driving chip 210
Go out pin OUPAD1 phase to couple, and, second grid driving chip 221 receives reference current by electric current input pin INPAD2
IR, and reference current IR is sent to its current output pin OUPAD2.It addition, reference current IR is then by second grids at different levels
Couple relation between driving chip 221～22N, reference current IR is sent to second grid driving chip 221～22N.
Second grid driving chip 221～22N includes mac function circuit 2211～22N1, mac function circuit respectively
2211～22N1 then accept and produce output signal GD2～GDN respectively according to reference current IR.Significantly, since
The mac function circuit 2211～22N1 of second grid driving chip 221～22N received and dragged down according to this output signal GD2～
The reference current of GDN is all identical reference current IR, and, the mac function circuit 211 of first grid driving chip 210 is also
It is based on reference current IR equally to drag down output signal GD1 produced by it, therefore, produced by gate drive apparatus 200
Output signal GD1～GDN will not be because of between first grid driving chip 210 and second grid driving chip 221～22N
The difference of process parameter, and cause produced output signal GD1～GDN being pulled low to equal under grid low-voltage level
Difference on reduction of speed degree.It is to say, the uniformity of output signal GD1 of gate drive apparatus 200～GDN can be by effectively
Promote.
Subsidiary one carries, and mac function circuit 2211～22N1 can produce one or more output signals GD2 respectively
～GDN.
Hereinafter refer to the schematic diagram that Fig. 3 A, Fig. 3 A illustrate the gate drive apparatus 300 of another embodiment of the present invention.Grid
Driving means 300 includes with reference to electric signal generator IS1, first grid driving chip 310 and second grid driving chip
321.In the present embodiment, it is a current source with reference to electric signal generator IS1, and is coupled in first grid driving chip
Between the input pin INPAD1 and operation voltage VCC of 310.The reference electricity of current signal is produced with reference to electric signal generator IS1
Gas signal ES1 is using as reference current IR, and transmits reference current IR by input pin INPAD1 and drive core to first grid
Mac function circuit 311 in sheet 310 and current output pin OUPAD1 of first grid driving chip 310.
The electric current input pin INPAD2 of second grid driving chip 321 is coupled to the electricity of first grid driving chip 310
Stream output connecting pin OUPAD1 also receives reference current IR.Reference current IR is also sent to second by electric current input pin INPAD2
Mac function circuit 3211 in grid drive chip 321 and the current output pin in second grid driving chip 321
OUPAD2。
By above-mentioned explanation it is known that the mac function circuit 311 in first grid driving chip 310 and second gate
Mac function circuit 3211 in pole driving chip 321 is to receive identical reference current IR, the most therefore, mac function circuit
311 and output signal GD1 that produces respectively of mac function circuit 3211 and GD2 can not be by first grid driving chip
310 and the impact of 321 process parameter of second grid driving chip and produce difference to each other.It is to say, grid drives
Produced by dynamic device 300, the uniformity of output signal GD1 and GD2 can be elevated.
Hereinafter refer to Fig. 3 B～3C, Fig. 3 B～3C and illustrate the gate drive apparatus more than 300 of the embodiment of the present invention respectively
Individual embodiment.In figure 3b, first grid driving chip 300 also includes current mirror MR11 and MR12.Wherein, current mirror
MR11 receives reference electric signal ES1 provided with reference to electric signal generator IS1, and mirror comes with reference to electric signal ES1
Produce reference current IR, wherein, be current signal with reference to electric signal ES1.Current mirror MR12 then receives and mirrored current mirror
Reference current IR produced by MR11, with the current output pin OUPAD1 output reference current coupled at current mirror MR12
IR。
Subsidiary one carries, and also includes transistor T1, and transmit reference by the drain electrode of transistor T1 in current mirror MR12
Electric current IR is to mac function circuit 311.Wherein, transistor T1 comes by mirror mode with the ratio of 1:1, to transmit reference current
IR is to mac function circuit 311.
Second grid driving chip 321 the most also includes that current mirror MR21 and MR22, current mirror MR21 are coupled to second gate
The electric current input pin INPAD2 of pole driving chip 321 is to receive reference current IR.Current mirror MR21 by the way of mirror
So that reference current IR is sent to current mirror MR22.Current mirror MR22 then receives reference current IR, and by the way of mirror with
Reference current IR is sent to current output pin OUPAD2 that current mirror MR22 is coupled.
Similarly, current mirror MR22 also includes transistor T2, and transmits reference current by the drain electrode of transistor T2
IR is to mac function circuit 3211.Wherein, transistor T2 comes by mirror mode with the ratio of 1:1, to transmit reference current IR
To mac function circuit 3211.
In fig. 3 c, first grid driving chip 310 and second grid driving chip 321 the most only have an electricity
Stream mirror MR11 and MR22.Wherein, the current mirror MR11 in first grid driving chip 310 be the transistor TN1 utilizing N-type with
And TN2 carrys out construction, the current mirror MR22 in second grid driving chip 321 be then utilize p-type transistor TP1 and
TP2 carrys out construction.Fig. 3 C embodiment is identical with the details of operation of the embodiment depicted in Fig. 3 B, below pardons few superfluous
State.
It should be noted that current mirror MR11 and MR22 receives adjustment signal TRIM1 and TRIM2 respectively.Current mirror
MR11 and MR22 can carry out the adjustment of produced reference current IR respectively according to adjustment signal TRIM1 and TRIM2.On
The method of adjustment of the reference current IR stated can by adjust signal TRIM1 and TRIM2 come to transistor TN1, TN2, TP1 with
And at least one of length-width ratio of TP2 could be adjusted to reach.And the details adjusted about transistor length-width ratio is ability
Technology known to field technique personnel, below pardons and seldom repeats.
Hereinafter refer to the schematic diagram that Fig. 4 A, Fig. 4 A illustrate the gate drive apparatus 400 of another embodiment of the present invention.Grid
Driving means 400 includes with reference to electric signal generator VS1, first grid driving chip 410 and second grid driving chip
420.In the present embodiment, it is a voltage source with reference to electric signal generator VS1, and is coupled in first grid driving chip
Between the input pin INPAD1 and reference ground voltage GND of 310.The ginseng of voltage signal is produced with reference to electric signal generator VS1
Examining electric signal ES1, first grid driving chip 410 convert reference electric signal ES1 are to produce reference current IR, and pass through
Input pin INPAD1 transmits reference current IR to the mac function circuit 411 and first in first grid driving chip 410
Current output pin OUPAD1 of grid drive chip 410.
The electric current input pin INPAD2 of second grid driving chip 421 is coupled to the electricity of first grid driving chip 410
Stream output connecting pin OUPAD1 also receives reference current IR.Reference current IR is also sent to second by electric current input pin INPAD2
Mac function circuit 4211 in grid drive chip 421 and the current output pin in second grid driving chip 421
OUPAD2。
By above-mentioned explanation it is known that the mac function circuit 411 in first grid driving chip 410 and second gate
Mac function circuit 4211 in pole driving chip 421 is to receive identical reference current IR, the most therefore, mac function circuit
311 and output signal GD1 that produces respectively of mac function circuit 4211 and GD2 can not be by first grid driving chip
410 and the impact of 421 process parameter of second grid driving chip and produce difference to each other.It is to say, grid drives
Produced by dynamic device 400, the uniformity of output signal GD1 and GD2 can be elevated.
Hereinafter refer to Fig. 4 B～4C, Fig. 4 B～4C and illustrate the gate drive apparatus more than 400 of the embodiment of the present invention respectively
Individual embodiment.In figure 4b, first grid driving chip 400 also includes voltage current adapter 412, voltage current adapter
412 couple input pin INPAD1 to receive with reference to electric signal VS1.Wherein, with reference to electric signal ES1 using as with reference to electricity
Pressure, voltage current adapter 412 carries out changing to produce reference current IR according to reference voltage.Voltage current adapter 412 wraps
Include current mirror MR11 and MR12.Current mirror MR11 receives with reference to electric signal ES1 using as bias voltage and electric according to reference
Gas signal ES1 produces reference current IR.Reference current IR is sent to and current mirror by current mirror MR11 also by mirror mode
The current mirror MR12 that MR11 couples.
Current mirror MR12 is coupled between current mirror MR11 and current output pin OUPAD2.Current mirror MR12 receives ginseng
Examine electric current IR and by the way of mirror, reference current IR be sent to current output pin OUPAD2.
In figure 4 c, voltage current adapter 412 only includes one group of current mirror MR11, and second grid driving chip 421
The most only include one group of current mirror MR21.Wherein, the kenel of the transistor of composition current mirror MR11 and the type forming current mirror MR21
State is complementary.Further, Fig. 4 C embodiment is identical with the action details of the embodiment depicted in Fig. 4 B, below pardons not
Repeat more.
Refer to first grid driving chip one real that Fig. 5 A, Fig. 5 A illustrates the gate drive apparatus of the embodiment of the present invention
Execute mode.In the present embodiment, first grid driving chip 510 includes mac function circuit 511, selector 512, reference electricity
Gas signal generator 513, input pin INPAD1 and current output pin OUPAD1.With reference in electric signal generator 513
It build in first grid driving chip 510.Selector 512 is then coupled in reference to electric signal generator 513 and input pin
Between INPAD1.Selector 512 selecting reference electric signal generator 513 produced with reference to electric signal ESI and by
One of them of reference electric signal ESO that outside is inputted by input pin INPAD1 exports.First grid drives
Dynamic chip 510 then produces reference current IR according to the result (with reference to electric signal ES1) selected by selector 512.
It is to say, when being voltage signal with reference to electric signal ES1, first grid driving chip 510 can be by electricity
Pressure turns the mode of electric current and comes according to reference electric signal ES1 to produce reference current IR.And when reference electric signal ES1 is electric current
During signal, first grid driving chip 510 can use with reference to electric signal ES1 using as reference current IR.
Refer to the embodiment that Fig. 5 B, Fig. 5 B illustrates the selector 512 of the embodiment of the present invention.Selector 512 includes
Switch SW1 and SW2, switch SW1 are serially connected between the outfan OT of input pin INPAD1 and selector 512, and switch SW2 is then
It is serially connected between the outfan OT with reference to electric signal generator 513 and selector 512.When switching SW1 conducting, switch SW1
Select to transmit input reference electric signal ESO that reached of pin INPAD1 to the outfan OT of selector 512.Relatively, when
During switch SW2 conducting, switch SW2 selects and transmits the reference electric signal ESI selector reached with reference to electric signal generator 513
The outfan OT of 512.Further, switch SW1 and SW2 will not be switched on simultaneously.
Refer to the schematic diagram that Fig. 6, Fig. 6 illustrate the gate drive apparatus 600 of yet another embodiment of the invention.Raster data model fills
Put 600 and include first grid driving chip 610 and second grid driving chip 621.First grid driving chip 610 includes merit
Energy block circuit 611, switch SW3, reference electric signal generator IS2, input pin INPAD1 and current output pin
OUPAD1.Second grid driving chip 621 then includes mac function circuit 6211, switch SW4, transfer wire TL1, input pin
INPAD2 and current output pin OUPAD2.Wherein, in first grid driving chip 610, with reference to electric signal generator
IS2 is current source, is used for providing reference current IR.Between first grid driving chip 610 and second grid driving chip 621,
Input pin INPAD2 is coupled to current output pin OUPAD1, and uses and transmitted with reference to electricity by first grid driving chip 610
Stream IR is to second grid driving chip 621.In second grid driving chip 621, transfer wire TL1 is coupled in input pin
Between INPAD2 and current output pin OUPAD2, it is used for transmitting reference current IR to the second grid driving chip of next stage.
Switch SW3 is serially connected in mac function circuit 611 and with reference between electric signal generator IS2, switch SW4 is then serially connected in
Between mac function circuit 6211 and reference electric signal generator IS2.When switching SW3 and SW4 and being switched on, it is respectively transmitted reference
Electric current IR is to mac function circuit 611 and mac function circuit 6211.
Refer to the schematic diagram that Fig. 7 A, Fig. 7 A illustrates the gate drive apparatus 700 of a present invention more embodiment.Raster data model
Device 700 includes first grid driving chip 710 and programmable reference electric signal generator 701.Programmable reference is electric
Signal generator 701 is coupled to the input pin INPAD1 of first grid driving chip 710 to transmit with reference to electric signal ES1.
Current output pin OUPAD1 of first grid driving chip 710 is then coupled to the second grid driving chip of the first order and (does not paints
Show).
Programmable reference electric signal generator 701 has programmable interface to receive command signal SPIS.Ginseng able to programme
Examine electric signal generator 701 and according to command signal SPIS to produce with reference to electric signal ES1.Wherein, programmable interface can
To be serial circumference interface.
Refer to the enforcement that Fig. 7 B, Fig. 7 B illustrates the programmable reference electric signal generator 701 of the embodiment of the present invention
Mode.Programmable reference electric signal generator 701 includes order buffer 7011 and with reference to electric signal generator 7012.
Order buffer 7011 receives and keeps in the order data that command signal SPIS is transmitted.With reference to electric signal generator 7012 coupling
Meet order buffer 7011 and input pin INPAD1.Produce according to command signal with reference to electric signal generator 7012
And/or adjust with reference to electric signal ES1.
By programmable reference electric signal generator 701, the gate drive apparatus 700 of the present embodiment can provide use
One programmable interface of person, adjusts the size of reference current in gate drive apparatus 700, enters to adjust produced by it defeated
Go out the speed of the voltage pull-down of signal.
Refer to the schematic diagram that Fig. 8 A, Fig. 8 A illustrates the gate drive apparatus 800 of the embodiment of the present invention.Gate drive apparatus
800 include grid drive chip 810～8N0 and current generator 801.Grid drive chip 810～8N0 is respectively provided with shared
Pin EPAD1～EPADN, and shared pin EPAD1～EPADN of grid drive chip 810～8N0 be mutually coupled.Electric current produces
One end of raw device 801 is coupled to shared pin EPAD1～EPADN of grid drive chip 810～8N0, current generator 801
The other end is coupled to reference to ground voltage GND.Current generator 801 is in order to be connect by each the shared of grid drive chip 810～8N0
Foot EPAD1～EPADN draws reference current IR to reference to ground voltage GND.Wherein, each grid drive chip 810～8N0 produces
At least one output signal GD1～GDN.Each grid drive chip according to control signal make output signal GD1～GDN draw high to
Driving voltage or make current generator 801 drag down output signal GD1～GDN to reference to ground voltage GND.
It should be noted that in the present embodiment, all of grid drive chip 810～8N0 is used for dragging down output signal
The reference current IR of GD1～GDN is provided by current generator 801.Therefore, grid drive chip 810～8N0 drags down
The ability that drags down of output signal GD1～GDN is all identical.It is to say, the speed that is pulled low of output signal GD1～GDN is
Identical.
It addition, can also be able to be maybe non-zero free voltage level with the voltage of 0 voltage level with reference to ground voltage GND
Voltage.
Hereinafter refer to Fig. 8 B～8E, Fig. 8 B～8D and illustrate the gate drive apparatus 800 of the embodiment of the present invention respectively not
Same embodiment.In the fig. 8b, gate drive apparatus 800 includes grid drive chip 810,820, and grid drive chip 810
Including the gate driver circuit being made up of controller 811 and transistor T1 and T2, grid drive chip 820 then includes by controlling
The gate driver circuit that device 821 processed and transistor T3 and T4 are constituted.Controller 811 and 821 is respectively according to clock signal
CKV provides grid and the grid of transistor T3～T4 controlling signal to transistor T1～T2.In grid drive chip 810
In, first end of transistor T1 is coupled to the second reference voltage (the second reference voltage is driving voltage VGH in the present embodiment),
The control end of transistor T1 is its grid, and second end of transistor T1 produces output signal GD1.The first end coupling of transistor T2
Being connected to second end of transistor T1, the control end of transistor T2 is its grid, and second end of transistor T2 is coupled to raster data model
The shared pin EPAD1 of chip 810.
In grid drive chip 820, first end of transistor T3 is coupled to driving voltage VGH, the control of transistor T3
End is its grid, and second end of transistor T3 produces output signal GD2.First end of transistor T4 is coupled to transistor T3's
Second end, the control end of transistor T4 is its grid, and second end of transistor T4 is coupled to the shared of grid drive chip 820 and connects
Foot EPAD2.
In the present embodiment, current generator 801 is resistance R, resistance R be serially connected in shared pin EPAD1～EPAD2 and
Between the first reference voltage (the first reference voltage is with reference to ground voltage GND in the present embodiment).It is being switched on as transistor T2
Time, output signal GD1 is pulled low by reference current IR produced by resistance R, and makes output signal GD1 drop to equal to reference
Ground voltage GND.
In Fig. 8 C, current generator 801 is then current source IS3.Current source IS3 is in order to provide by shared pin EPAD1
～one of them of EPAD2 flows to the reference current IR of reference ground voltage GND to drag down output signal GD1 or GD2.
In Fig. 8 D, grid drive chip 810 includes multiple gate driver circuit 811～813.All of raster data model electricity
Road 811～813 is commonly coupled to share pin EPAD1, and is connected to current generator 801 by shared pin EPAD1.
In Fig. 8 E, the gate driver circuit in grid drive chip 810,820 also includes many sub-drive circuits.With grid
Pole driving chip 810 is example, and grid drive chip 810 includes many sub-drive circuits 8111～811N.Again with son therein
Drive circuit 8111 is example, and sub-drive circuit 8111 includes sub-controller CT1, transistor T5 and T6.Sub-controller CT1 produces
Raw sub-control signal, and sub-control signal is sent to the control end of transistor T5 and T6.First end of transistor T5 receives
Output signal GD1, second end of transistor T5 then produces sub-output signal SGD11.First end of transistor T6 receives son output
Signal SGD11, its second end is coupled to the 3rd reference voltage (the 3rd reference voltage of the present embodiment is driving voltage VGL).
Hereinafter refer to Fig. 9 A～9C, Fig. 9 A～9C and illustrate the gate drive apparatus 900 of the embodiment of the present invention respectively not
Same embodiment.In figure 9 a, gate drive apparatus 900 includes grid drive chip 910 and 920 and current generator 901.
Grid drive chip 910 and 920 is respectively provided with shared pin EPAD1 and EPAD2, shares pin EPAD1 and EPAD2 mutual
Couple.One end of current generator 901 is coupled to shared pin EPAD1 and EPAD2 of grid drive chip 910 and 920.
The other end of current generator 901 is coupled to the first reference voltage, and (the first reference voltage is driving voltage in the present embodiment
VGH).Current generator 901 is respectively at shared pin EPAD1 and EPAD2 and the driving electricity of grid drive chip 910 and 920
Reference current is provided between pressure VGH.
Grid drive chip 910 includes at least one gate driver circuit 911～91N, grid drive chip 920 then include to
A few gate driver circuit 921～92N.With gate driver circuit 911 as example, gate driver circuit 911 includes controller CT1
And transistor T1 and T2.Transistor T1 has the first end, the second end and controls end.First end of transistor T1 is coupled to
Two reference voltages (the second reference voltage is with reference to ground voltage GND in the present embodiment), its second end produces output signal
GD1, wherein, control signal produced by the control termination admission controller CT1 of transistor T1.Transistor T2 have the first end,
Two ends and control end.First end of transistor T2 is coupled to second end of transistor T1, and the control end of transistor T2 receives control
Control signal produced by device CT1 processed, and second end of transistor T2 be coupled to correspondence shared pin EPAD1.In this enforcement
In mode, current generator 901 is by the construction of resistance R institute.
In figures 9 b and 9, different from the embodiment of Fig. 9 A, current generator 901 is by the construction of current source IS3 institute.
Additionally, in Fig. 9 C, the gate driver circuit 911 in grid drive chip 910 also includes many sub-drive circuits
9111～911M.With sub-drive circuit 9111 as example, sub-drive circuit 9111 includes sub-controller CT11 and transistor T5
And T6.First end of transistor T6 receives output signal GD1, and its second end produces sub-output signal SGD11, wherein, crystal
The control end of pipe T6 receives sub-control signal produced by sub-controller CT11.First end of transistor T5 couples sub-output signal
SGD11, its second end receives the first reference voltage (the 3rd reference voltage of the present embodiment is equal to driving voltage VGH), wherein, brilliant
The control end of body pipe T5 receives sub-control signal produced by sub-controller CT11.
Subsidiary one carries, and the current generator 901 in the present embodiment is serially connected in shared pin EPAD1, EPAD2 and driving electricity
Between pressure VGHM.
In sum, the present invention is by providing the reference electricity that the multiple grid drive chip in gate drive apparatus are identical
Stream, and make each gate drive apparatus drag down and/or draw high produced output signal according to the identical reference current received.
And use the uniformity maintaining output signal, promote the usefulness of gate drive apparatus.
Although the present invention is disclosed above with embodiment, so it is not limited to the present invention, any art
Middle tool usually intellectual, without departing from the spirit and scope of the present invention, when making a little change and retouching, therefore the present invention
Protection domain when being as the criterion depending on the defined person of scope of the appended claims.
Claims (7)
1. a gate drive apparatus, including:
Multiple grid drive chip, respectively this grid drive chip has and shares pin, sharing of the plurality of grid drive chip
Pin is mutually coupled；And
One current generator, one end of this current generator is coupled to the shared pin of respectively this grid drive chip, and this electric current produces
The other end of raw device is coupled to one first reference voltage, this current generator this respectively this grid drive chip shared pin with
A reference current is provided between this first reference voltage,
Wherein, respectively this grid drive chip produces at least one output signal, and respectively this grid drive chip is come according to a control signal
This output signal is made to carry out transition between this first reference voltage and one second reference voltage.
Gate drive apparatus the most according to claim 1, respectively this grid drive chip includes at least one raster data model
Circuit, this gate driver circuit includes:
One the first transistor, have the first end, the second end and control end, the first end of this first transistor be coupled to this second
Reference voltage, its second end produces this output signal, wherein controls end and receives this control signal；And
One transistor seconds, have the first end, the second end and control end, the first end of this transistor seconds be coupled to this first
Second end of transistor, the control end of this transistor seconds receives this control signal, and the second end of this transistor seconds couples
To this corresponding shared pin.
Gate drive apparatus the most according to claim 2, wherein when this first reference voltage is a reference ground voltage,
This second reference voltage is a driving voltage, when this first reference voltage is a driving voltage, and this second reference voltage is a ginseng
Examine ground voltage.
Gate drive apparatus the most according to claim 2, wherein this gate driver circuit also includes:
Many sub-drive circuits, receive this output signal, and respectively this sub-drive circuit includes:
One sub-controller, produces a sub-control signal；
One third transistor, has the first end, the second end and controls end, and the first end of this third transistor receives this output letter
Number, its second end produces a sub-output signal, wherein controls end and receives this sub-control signal；And
One the 4th transistor, has the first end, the second end and controls end, and the first end of the 4th transistor couples this sub-output
Signal, its second end is coupled to one the 3rd reference voltage, wherein controls end and receives this sub-control signal.
Gate drive apparatus the most according to claim 1, wherein this current generator is a resistance, and this resistance is serially connected in respectively
Between the shared pin of this grid drive chip and this first reference voltage.
Gate drive apparatus the most according to claim 5, wherein this resistance is variable resistance.
Gate drive apparatus the most according to claim 1, wherein this current generator is a current source, in order to produce this ginseng
Examine electric current.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210190794.3A CN103489388B (en) | 2012-06-11 | 2012-06-11 | Gate drive apparatus |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210190794.3A CN103489388B (en) | 2012-06-11 | 2012-06-11 | Gate drive apparatus |
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| CN103489388A CN103489388A (en) | 2014-01-01 |
| CN103489388B true CN103489388B (en) | 2016-12-14 |
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| CN109661701A (en) * | 2016-09-01 | 2019-04-19 | 夏普株式会社 | Active-matrix substrate and display device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003076346A (en) * | 2001-09-03 | 2003-03-14 | Samsung Electronics Co Ltd | Liquid crystal display device |
| TW201211972A (en) * | 2010-09-13 | 2012-03-16 | Chimei Innolux Corp | Control board for amorphous silicon gate |
| TW201214968A (en) * | 2010-09-21 | 2012-04-01 | Au Optronics Corp | Nth shift register capable of increasing driving capability and method for increasing driving capability of a shift register |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI409528B (en) * | 2010-07-02 | 2013-09-21 | Chunghwa Picture Tubes Ltd | Display panel |
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2012
- 2012-06-11 CN CN201210190794.3A patent/CN103489388B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003076346A (en) * | 2001-09-03 | 2003-03-14 | Samsung Electronics Co Ltd | Liquid crystal display device |
| TW201211972A (en) * | 2010-09-13 | 2012-03-16 | Chimei Innolux Corp | Control board for amorphous silicon gate |
| TW201214968A (en) * | 2010-09-21 | 2012-04-01 | Au Optronics Corp | Nth shift register capable of increasing driving capability and method for increasing driving capability of a shift register |
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