CN103488916A - On-missile software encipherment protection method - Google Patents
On-missile software encipherment protection method Download PDFInfo
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- CN103488916A CN103488916A CN201310347652.8A CN201310347652A CN103488916A CN 103488916 A CN103488916 A CN 103488916A CN 201310347652 A CN201310347652 A CN 201310347652A CN 103488916 A CN103488916 A CN 103488916A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/51—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems at application loading time, e.g. accepting, rejecting, starting or inhibiting executable software based on integrity or source reliability
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/52—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
Abstract
The invention belongs to the field of the computer information security, and particularly relates to an on-missile software encipherment protection method. The on-missile software encipherment protection method has the technical scheme that a target program plaintext is generated after core software is designed, developed and debugged on the basis of the traditional method. The on-missile software encipherment protection method disclosed by the invention is characterized in that an encipherment flow is added, the target program plaintext is encrypted into a ciphertext by a high-safety encipherment algorithm, and then the ciphertext is programmed into a missile-borne computer read only memory, which is different from the traditional method that the program plaintext is directly programmed into the missile-borne computer read only memory. In the hardware framework of the missile-borne computer, a hardware protection module is added and is mainly used for decrypting the program ciphertext stored in the read only memory. After the missile-borne computer system is electrified, the hardware protection module reads the program ciphertext from the read only memory to decrypt the ciphertext by the self algorithm logic to obtain the target program plaintext, then the plaintext is handed to the processer to be loaded and executed, and the subsequent work is kept consistent with the starting operation flow of the traditional missile-borne computer.
Description
Technical field
The invention belongs to field of computer information security.Be specifically related to a kind of software encryption and protection method on bullet.
Background technology
Guided missile is most important weaponry in modern war.Along with improving constantly of China's Missile Information level, the missile-borne computer system that supports the Missile Equipment systemic-function reaches software on the bullet moved thereon and also becomes increasingly complex.Yet; under the Missile Equipment system condition of current China; the kernel software that has comprised a lot of important informations is not all done in the storage unit that any protection is stored in embedded system; software executable code can be read easily; the running environment that adds software is almost transparent, by conversed analysis and dis-assembling means, can obtain core algorithm and the critical data be hidden in software.Like this, the technology that war industry designs and develops a large amount of painstaking effort of personnel, time and fund of having condensed very easily is cracked and steals.For the model software of Missile Equipment, particularly for foreign trade guided missile model, if on bullet, kernel software is cracked, not only be related to the soft ware autonomous intellecture property of model, be related to especially national interests and national defense safety.Therefore, need to take corresponding safety precautions to the kernel software in Missile Equipment, guarantee the safety of core algorithm, data and index parameter.
For realizing the safeguard protection to the Missile Equipment kernel software, need fully to understand general missile-borne computer and start and workflow.As shown in Figure 1, the start-up course of system is tradition missile-borne computer system architecture: after a) system powers on, cpu reset signal is by unified control on circuit board, and on plate, reset signal makes CPU start operation after dragging down; B) at first CPU reads the bios program in ROM on plate, is loaded into RAM and carries out, and the one-level of completion system starts; C) after bios program completes corresponding initial work, be directed to curing storer (EPROM or Flash) program memory address, CPU reads the target program that solidifies preservation and is loaded in RAM, and carries out, this has just completed the secondary startup, and target program has moved corresponding systemic-function subsequently.
Summary of the invention
(1) technical matters that will solve
The technical problem to be solved in the present invention is: how for general missile-borne computer system architecture; by design hardware protection module and working-flow; how to realize encryption storage and the online decipher operation of kernel software in in-line memory; prevent that kernel software from being read easily and cracking, thereby improve the security of kernel software.
(2) technical scheme
For solving the problems of the technologies described above, the invention provides a kind of software encryption and protection method on bullet, described method is implemented based on the hardware protection module, described hardware protection module communicates by bus and CPU, for controlling reset signal and the debug signal of central processor CPU of missile-borne computer, simultaneously, described hardware protection module connects curing storer; Described hardware protection module comprises: programmable gate array FPGA and SRAM; Wherein, pass through gate array logic realization cryptographic algorithm in described FPGA, for deciphering the target program ciphertext; Described SRAM deciphers the plaintext obtained after the target program ciphertext for buffer memory; Wherein,
Described method comprises the steps:
Step S1: after design, exploitation and debugging based on carrying out kernel software under classic method, generate target program expressly; Host computer adopts the cryptographic algorithm of high security that the target program plain text encryption is become to ciphertext, then by the ciphertext programming in the curing storer of missile-borne computer;
Step S2: after system powers on, cpu reset signal, by the hardware protection module controls, maintains the reset signal high-end trim after the hardware protection module powers on, and stops CPU to start;
Step S3: the hardware protection module reads and solidifies the target program ciphertext of preserving from solidify storer, by inner decipherment algorithm, by decrypt ciphertext, synchronously the plaintext obtained after deciphering is saved in the SRAM of hardware protection inside modules;
Step S4: after completing the whole deciphering of target program, target program expressly in the whole internal SRAM that is kept at the hardware protection module after, the hardware protection module drags down cpu reset signal;
At first step S5:CPU reads the bios program in ROM on plate, is loaded into RAM and carries out, and the one-level of completion system starts;
After step S6:BIOS program completes corresponding initial work, be directed to the address mapping of hardware protection inside modules SRAM, CPU is usingd hardware protection inside modules SRAM as the curing storer under conventional architectures, the target program that reads buffer memory in SRAM expressly is loaded in RAM, and carry out, complete secondary and start;
Step S7: subsequently, the target program operation, complete corresponding systemic-function.
Wherein, the cryptographic algorithm that the cryptographic algorithm that described host computer adopts and described hardware protection module adopt is symmetric encipherment algorithm each other; decipherment algorithm in cryptographic algorithm in host computer and hardware protection module is consistent, simultaneously cryptographic algorithm key used also will with key agreement used during deciphering in the hardware protection module.
Wherein, the cryptographic algorithm that the cryptographic algorithm that described host computer adopts and described hardware protection module adopt is the AES cryptographic algorithm.
Wherein, the cryptographic algorithm that the cryptographic algorithm that described host computer adopts and described hardware protection module adopt is the close algorithm of commercial cryptographic algorithm or state.
(3) beneficial effect
By adopting, reliability is high in the present invention, the close algorithm of commercial cryptographic algorithm or state of safety on cryptography, to after missile-borne computer kernel software code encryption, store again, can prevent the reading of kernel software program, inverting and crack analysis, effectively raising the security of core knowledge property right.
The accompanying drawing explanation
Fig. 1 is traditional missile-borne computer system architecture.
Fig. 2 is the principle schematic of technical solution of the present invention.
Fig. 3 is the missile-borne computer framework in the present invention.
Embodiment
For making purpose of the present invention, content and advantage clearer, below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.
For solving the problem of prior art, technical solution of the present invention, after design, exploitation and debugging based on carrying out kernel software under classic method, generates target program expressly.Be different under classic method and directly the programming of program plaintext solidified to the way in storer to missile-borne computer, increased an encryption flow in the present invention, expressly adopt the cryptographic algorithm of high security to be encrypted to ciphertext target program, then the ciphertext programming is solidified in storer to missile-borne computer.
In the missile-borne computer hardware structure, increased a hardware protection module, major function is to be decrypted solidifying the program ciphertext of preserving in storer.Like this; after the missile-borne computer system powers on; the hardware protection module is the fetch program ciphertext from solidify storer; utilize the algorithm logic of self to decrypt ciphertext; obtain target program expressly; plaintext is given to processor again and loaded and carry out, the startup operational scheme of follow-up work and traditional missile-borne computer is consistent.
Particularly, as shown in Figure 2, software encryption and protection method on bullet provided by the present invention, it is implemented based on the hardware protection module, described hardware protection module communicates by bus and CPU, for controlling reset signal and the debug signal of central processor CPU of missile-borne computer, simultaneously, described hardware protection module connects solidifies storer; Described hardware protection module comprises: programmable gate array FPGA and SRAM; Wherein, pass through gate array logic realization cryptographic algorithm in described FPGA, for deciphering the target program ciphertext; Described SRAM deciphers the plaintext obtained after the target program ciphertext for buffer memory; Wherein,
Described method comprises the steps:
Step S1: after design, exploitation and debugging based on carrying out kernel software under classic method, generate target program expressly; Host computer adopts the cryptographic algorithm of high security that the target program plain text encryption is become to ciphertext, then by the ciphertext programming in the curing storer of missile-borne computer;
Step S2: after system powers on, cpu reset signal, by the hardware protection module controls, maintains the reset signal high-end trim after the hardware protection module powers on, and stops CPU to start;
Step S3: the hardware protection module reads and solidifies the target program ciphertext of preserving from solidify storer, by inner decipherment algorithm, by decrypt ciphertext, synchronously the plaintext obtained after deciphering is saved in the SRAM of hardware protection inside modules;
Step S4: after completing the whole deciphering of target program, target program expressly in the whole internal SRAM that is kept at the hardware protection module after, the hardware protection module drags down cpu reset signal;
At first step S5:CPU reads the bios program in ROM on plate, is loaded into RAM and carries out, and the one-level of completion system starts;
After step S6:BIOS program completes corresponding initial work, be directed to the address mapping of hardware protection inside modules SRAM, CPU is usingd hardware protection inside modules SRAM as the curing storer under conventional architectures, the target program that reads buffer memory in SRAM expressly is loaded in RAM, and carry out, complete secondary and start;
Step S7: subsequently, the target program operation, complete corresponding systemic-function.
Wherein, the cryptographic algorithm that the cryptographic algorithm that described host computer adopts and described hardware protection module adopt is symmetric encipherment algorithm each other; decipherment algorithm in cryptographic algorithm in host computer and hardware protection module is consistent, simultaneously cryptographic algorithm key used also will with key agreement used during deciphering in the hardware protection module.
Wherein, the cryptographic algorithm that the cryptographic algorithm that described host computer adopts and described hardware protection module adopt is the AES cryptographic algorithm.
Wherein, the cryptographic algorithm that the cryptographic algorithm that described host computer adopts and described hardware protection module adopt is the close algorithm of commercial cryptographic algorithm or state.
Below in conjunction with specific embodiment, describe in detail.
Embodiment
As shown in Figure 2, the core of the present embodiment scheme is to solidify storage after target program is encrypted to the present embodiment, and system is real time decrypting operation again after starting.In order to guarantee the speed of encrypting/separating; the cryptographic algorithm adopted in host computer encryption and hardware protection module is symmetric encipherment algorithm; as AES(Advanced Encryption Standard, Advanced Encryption Standard) cryptographic algorithm, the close algorithm of commercial cryptographic algorithm or its other country.In realization, require cryptographic algorithm in host computer and the decipherment algorithm in the hardware protection module to be consistent, simultaneously cryptographic algorithm key used also will with key agreement used during deciphering in the hardware protection module.
(2) design of hardware protection module.The hardware protection module is emphasis of the present invention, and as shown in Figure 3, this module is realized by programmable gate array FPGA and the design of SRAM static RAM, wherein, in FPGA, by gate array logic realization cryptographic algorithm, can decipher the target program ciphertext; SRAM deciphers the plaintext obtained after the target program ciphertext for buffer memory.
(3) in the present embodiment, the startup workflow of missile-borne computer has been compared to partly change with classic method, in detail as shown in Figure 3.The key distinction be the reset signal of central processor CPU of missile-borne computer and debug signal by the hardware protection module controls, solidify storer simultaneously and be not connected to cpu bus, but be connected with the hardware protection module.The concrete start-up course of system is:
A) after system powers on, cpu reset signal, by the hardware protection module controls, maintains the reset signal high-end trim after the hardware protection module powers on, and stops CPU to start;
B) the hardware protection module reads and solidifies the target program ciphertext of preserving from solidify storer, by inner decryption logic, by decrypt ciphertext, synchronously the plaintext obtained after deciphering is saved in the internal SRAM of hardware protection module;
C) after completing the whole deciphering of target program, target program expressly in the whole internal SRAM that is kept at the hardware protection module after, the hardware protection module drags down cpu reset signal;
D) similar with conventional situation, at first CPU reads the bios program in ROM on plate, is loaded into RAM and carries out, and the one-level of completion system starts;
E) after bios program completes corresponding initial work, be directed to the address mapping of hardware protection inside modules SRAM, like this, curing storer under the conventional architectures that CPU just treats as hardware protection inside modules SRAM, the target program that CPU reads buffer memory in SRAM expressly is loaded in RAM, and carry out, this has just completed the secondary startup;
F) target program operation subsequently, complete corresponding systemic-function, with consistent under conventional architectures.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the technology of the present invention principle; can also make some improvement and distortion, these improvement and distortion also should be considered as protection scope of the present invention.
Claims (4)
1. software encryption and protection method on a bullet, it is characterized in that, described method is implemented based on the hardware protection module, described hardware protection module communicates by bus and CPU, for controlling reset signal and the debug signal of central processor CPU of missile-borne computer, simultaneously, described hardware protection module connects curing storer; Described hardware protection module comprises: programmable gate array FPGA and SRAM; Wherein, pass through gate array logic realization cryptographic algorithm in described FPGA, for deciphering the target program ciphertext; Described SRAM deciphers the plaintext obtained after the target program ciphertext for buffer memory; Wherein,
Described method comprises the steps:
Step S1: after design, exploitation and debugging based on carrying out kernel software under classic method, generate target program expressly; Host computer adopts the cryptographic algorithm of high security that the target program plain text encryption is become to ciphertext, then by the ciphertext programming in the curing storer of missile-borne computer;
Step S2: after system powers on, cpu reset signal, by the hardware protection module controls, maintains the reset signal high-end trim after the hardware protection module powers on, and stops CPU to start;
Step S3: the hardware protection module reads and solidifies the target program ciphertext of preserving from solidify storer, by inner decipherment algorithm, by decrypt ciphertext, synchronously the plaintext obtained after deciphering is saved in the SRAM of hardware protection inside modules;
Step S4: after completing the whole deciphering of target program, target program expressly in the whole internal SRAM that is kept at the hardware protection module after, the hardware protection module drags down cpu reset signal;
At first step S5:CPU reads the bios program in ROM on plate, is loaded into RAM and carries out, and the one-level of completion system starts;
After step S6:BIOS program completes corresponding initial work, be directed to the address mapping of hardware protection inside modules SRAM, CPU is usingd hardware protection inside modules SRAM as the curing storer under conventional architectures, the target program that reads buffer memory in SRAM expressly is loaded in RAM, and carry out, complete secondary and start;
Step S7: subsequently, the target program operation, complete corresponding systemic-function.
2. software encryption and protection method on bullet as claimed in claim 1; it is characterized in that; the cryptographic algorithm that the cryptographic algorithm that described host computer adopts and described hardware protection module adopt is symmetric encipherment algorithm each other; decipherment algorithm in cryptographic algorithm in host computer and hardware protection module is consistent, simultaneously cryptographic algorithm key used also will with key agreement used during deciphering in the hardware protection module.
3. software encryption and protection method on bullet as claimed in claim 1, is characterized in that, the cryptographic algorithm that the cryptographic algorithm that described host computer adopts and described hardware protection module adopt is the AES cryptographic algorithm.
4. software encryption and protection method on bullet as claimed in claim 1, is characterized in that, the cryptographic algorithm that the cryptographic algorithm that described host computer adopts and described hardware protection module adopt is the close algorithm of commercial cryptographic algorithm or state.
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| CN109255258A (en) * | 2018-08-27 | 2019-01-22 | 重庆天箭惯性科技股份有限公司 | Encrypt navigational computer circuit |
| CN111814208A (en) * | 2020-07-02 | 2020-10-23 | 国家广播电视总局广播电视科学研究院 | Method for preventing fault injection during safe starting of soc security chip |
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Cited By (15)
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| CN105528548A (en) * | 2015-12-09 | 2016-04-27 | 乐鑫信息科技（上海）有限公司 | Method for encoding and automatically decoding codes in chip OutNvMem in batches |
| CN106066829A (en) * | 2016-06-13 | 2016-11-02 | 江西洪都航空工业集团有限责任公司 | A kind of missile-borne time-consuming real-time computing technique of embedded Control software cycle |
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| CN107808099B (en) * | 2016-09-08 | 2021-03-16 | 北京自动化控制设备研究所 | Embedded software encryption/decryption system and method |
| CN108881223A (en) * | 2018-06-17 | 2018-11-23 | 张红卫 | A method of protecting computer software is realized based on network communication |
| CN109255258A (en) * | 2018-08-27 | 2019-01-22 | 重庆天箭惯性科技股份有限公司 | Encrypt navigational computer circuit |
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| CN111814208A (en) * | 2020-07-02 | 2020-10-23 | 国家广播电视总局广播电视科学研究院 | Method for preventing fault injection during safe starting of soc security chip |
| CN111814208B (en) * | 2020-07-02 | 2023-07-28 | 国家广播电视总局广播电视科学研究院 | Method for defending fault injection during secure start of soc national security chip |
| CN112417521A (en) * | 2020-11-05 | 2021-02-26 | 中国航空工业集团公司西安航空计算技术研究所 | Information security system based on FPGA + processor architecture and working method thereof |
| CN112417521B (en) * | 2020-11-05 | 2023-09-05 | 中国航空工业集团公司西安航空计算技术研究所 | Information security system based on FPGA+processor architecture and working method thereof |
| CN112363956A (en) * | 2020-11-11 | 2021-02-12 | 上海磐启微电子有限公司 | Method and device for encrypting and decrypting FLASH memory |
| CN112685758A (en) * | 2020-12-31 | 2021-04-20 | 南方电网科学研究院有限责任公司 | Data encryption system based on elliptic curve encryption algorithm |
| CN112685758B (en) * | 2020-12-31 | 2024-02-06 | 南方电网科学研究院有限责任公司 | Data encryption system based on elliptic curve encryption algorithm |
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