CN103488223B - A kind of output voltage controlling circuit - Google Patents
A kind of output voltage controlling circuit Download PDFInfo
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- CN103488223B CN103488223B CN201310413101.7A CN201310413101A CN103488223B CN 103488223 B CN103488223 B CN 103488223B CN 201310413101 A CN201310413101 A CN 201310413101A CN 103488223 B CN103488223 B CN 103488223B
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Abstract
The invention discloses a kind of output voltage controlling circuit, by feeding back to the size of the electric current of voltage stabilizing chip in input logic signal control circuit, and then controlling the size of the voltage that described mu balanced circuit exports, to provide stable output voltage.In addition, whether worked by two voltage stabilizing chips in input logic signal control circuit, with in varied situations for system provides different output voltages.Realize while guarantee system is normally run, for system saves electric quantity of power supply.And circuit structure is simple, realize easily, more adequately to control the conversion of output voltage.
Description
Technical field
The present invention relates to circuit engineering field, particularly relate to a kind of output voltage controlling circuit.
Background technology
At present, along with the renewal day by day of product, efficient power management is one of key factor becoming circuit design.
Because system is under different operating state, be different to the demand of voltage.Such as, when needs process mass data time, use the voltage that amplitude is higher, when calculated amount is little, or when being under holding state, the voltage that amplitude is lower can be used.
If power supply provides high voltage always, then may cause the waste of electricity.If provide low voltage always, then can run by influential system, cannot extensive calculation process be carried out.
Therefore, now on the design field of power-efficient, one of them is exactly must provide different output voltages for the different operating situation of system, to realize while guarantee system is normally run, for system saves electric quantity of power supply.
Summary of the invention
The embodiment of the present invention provides a kind of output voltage controlling circuit, for realizing while guarantee system is normally run, for system saves electric quantity of power supply.
A kind of output voltage controlling circuit, comprise: the first voltage input end mouth (101), voltage output end mouth (102), first logic input terminal mouth (103), second logic input terminal mouth (104), 3rd logic input terminal mouth (105), second voltage input end mouth (106), tertiary voltage input port (107), first mu balanced circuit (108), feedback circuit (109), first logic control circuit (110), second mu balanced circuit (111), second logic control circuit (112), 3rd mu balanced circuit (113) and the 3rd logic control circuit (114),
Wherein, described first mu balanced circuit (108) one end is connected with described voltage input end mouth (101), and the other end of described first mu balanced circuit (108) is connected with described second mu balanced circuit (111);
Described feedback circuit (109) one end is connected with described second mu balanced circuit (111), and described feedback circuit (109) other end is connected with described first mu balanced circuit (108);
First logic control circuit (110) one end is connected with described first logic input terminal mouth (103), and the other end of described first logic control circuit (110) is connected with feedback circuit (109);
Institute's the first logic control circuit (110), according to from the first logic control signal of receiving of the first logic input terminal mouth (103), control the size that described feedback circuit (109) feeds back to the feedback current of described first mu balanced circuit (108); Described first mu balanced circuit (108) varies in size according to the feedback current received, exports the voltage of corresponding size to described second mu balanced circuit (111);
One end of described second mu balanced circuit (111) is connected with described first mu balanced circuit (108) and described feedback circuit (109), and the other end of described second mu balanced circuit (111) is connected with the second logic control circuit (112); One end again of described second mu balanced circuit (111) is connected with described voltage output end mouth (102);
Described second logic control circuit (112) is connected with described second logic input terminal mouth (104), the second voltage input end mouth (106) and tertiary voltage input port (107) respectively;
One end of described 3rd mu balanced circuit (113) is connected with described tertiary voltage input port (107), and the other end of described 3rd mu balanced circuit (113) is connected with the 3rd logic control circuit (114); One end again of described second mu balanced circuit (111) is connected with described voltage output end mouth (102);
Described 3rd logic control circuit (114) is connected with described 3rd logic input terminal mouth (105), the second voltage input end mouth (106) and tertiary voltage input port (107) respectively;
Wherein, described second logic control circuit (112) receives the second logic control signal by the second logic input terminal mouth (104), controls the whether conducting of described second mu balanced circuit (111) according to the second logic control signal received; Described 3rd logic control circuit (114) receives the 3rd logic control signal by the 3rd logic input terminal mouth (105), controls the whether conducting of described 3rd mu balanced circuit (113) according to the 3rd logic control signal received; When described second mu balanced circuit (111) or described 3rd mu balanced circuit (113) conducting, output voltage is to described voltage output end (102).
Preferably, described first mu balanced circuit (108) comprises the first voltage stabilizing chip (1081) and inductance (1082); Described feedback circuit (109) comprises the first resistance (1091), the second resistance (1092) and the 3rd resistance (1093); Described first logic control circuit (110) comprises the first triode (1101) and the 4th resistance (1102);
Wherein, the first port of described first voltage stabilizing chip (1081) is connected with described first voltage input end mouth (101); Second port of described first voltage stabilizing chip (1081) is connected with described second mu balanced circuit (111) by described inductance (1082);
Described first resistance (1091), the second resistance (1092) and the 3rd resistance (1093) are connected between described second mu balanced circuit (111) and ground, and the 3rd port of described first voltage stabilizing chip (1081) is connected between described first resistance (1091) and the second resistance (1092);
The collector of described first triode (1101) is connected between described second resistance (1092) and the 3rd resistance (1093); The grounded emitter of described first triode (1101); The base stage of described first triode (1101) is by the 4th resistance (1102) ground connection, and meanwhile, the base stage of described first triode (1101) is connected with described first logic input terminal mouth (103).
Preferably, described second mu balanced circuit (111) comprises the second voltage stabilizing chip (1111); Described second logic control circuit (112) comprising: the 5th resistance (1121), the 6th resistance (1122), the 7th resistance (1123) and the second triode (1124);
First port of described second voltage stabilizing chip (1111) is connected with described inductance (1082) and described first resistance (1091); 3rd port of described second voltage stabilizing chip (1111) is connected with described voltage output end mouth (102);
Described 5th resistance (1121) one end is connected with described second voltage input end mouth (106), and described 5th resistance (1121) other end is connected with the second port of described second voltage stabilizing chip (1111);
Described 6th resistance (1122) one end is connected with described second logic input terminal mouth (104), and described 6th resistance (1122) other end is connected with the base stage of described second triode (1124);
One end of described 7th resistance (1123) is connected with described tertiary voltage input port (107), and described 7th resistance (1123) other end is connected with described second logic input terminal mouth (104);
The collector of described second triode (1124) is connected with the second port of described second voltage stabilizing chip (1111), the grounded emitter of described second triode (1124).
Preferably, described 3rd mu balanced circuit (113) comprises the 3rd voltage stabilizing chip (1131); Described 3rd logic control circuit (114) comprising: the 8th resistance (1141), the 9th resistance (1142), the tenth resistance (1143) and the 3rd triode (1144);
First port of described 3rd voltage stabilizing chip (1131) is connected with described tertiary voltage input port (107); 3rd port of described 3rd voltage stabilizing chip (1131) is connected with described voltage output end mouth (102);
Described 8th resistance (1141) one end is connected with described second voltage input end mouth (106), and described 8th resistance (1141) other end is connected with the second port of described 3rd voltage stabilizing chip (1131);
Described 9th resistance (1142) one end is connected with described 3rd logic input terminal mouth (105), and described 9th resistance (1142) other end is connected with the base stage of described 3rd triode (1144);
One end of described tenth resistance (1143) is connected with described tertiary voltage input port (107), and described tenth resistance (1143) other end is connected with described 3rd logic input terminal mouth (105);
The collector of described 3rd triode (1144) is connected with the second port of described 3rd voltage stabilizing chip (1131), the grounded emitter of described 3rd triode (1144).
The output voltage controlling circuit of the present embodiment, by feeding back to the size of the electric current of voltage stabilizing chip in input logic signal control circuit, and then controls the size of the voltage that described mu balanced circuit exports, to provide stable output voltage.In addition, whether worked by two voltage stabilizing chips in input logic signal control circuit, with in varied situations for system provides different output voltages.Realize while guarantee system is normally run, for system saves electric quantity of power supply.And circuit structure is simple, realize easily, more adequately to control the conversion of output voltage.
Other features and advantages of the present invention will be set forth in the following description, and, partly become apparent from instructions, or understand by implementing the present invention.Object of the present invention and other advantages realize by structure specifically noted in write instructions, claims and accompanying drawing and obtain.
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Accompanying drawing explanation
Accompanying drawing is used to provide a further understanding of the present invention, and forms a part for instructions, together with embodiments of the present invention for explaining the present invention, is not construed as limiting the invention.In the accompanying drawings:
Fig. 1 is the structural representation of output voltage controlling circuit in the embodiment of the present invention;
Fig. 2 is the electrical block diagram of output voltage controlling circuit in the embodiment of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the preferred embodiments of the present invention are described, should be appreciated that preferred embodiment described herein is only for instruction and explanation of the present invention, is not intended to limit the present invention.
Because system is under different operating state, be different to the demand of voltage.The invention provides a kind of conversion that can realize simply, quickly and accurately electric power output voltage.
As shown in Figure 1, the output voltage controlling circuit of the embodiment of the present invention, comprising:
First voltage input end mouth 101, voltage output end mouth 102, first logic input terminal mouth 103, second logic input terminal mouth 104, the 3rd logic input terminal mouth 105, second voltage input end mouth 106, tertiary voltage input port 107, first mu balanced circuit 108, feedback circuit 109, first logic control circuit 110, second mu balanced circuit 111, second logic control circuit 112, the 3rd mu balanced circuit 113 and the 3rd logic control circuit 114.
Wherein, first mu balanced circuit 108 one end is connected with voltage input end mouth 101, and the other end of the first mu balanced circuit 108 is connected with the second mu balanced circuit 111.
Feedback circuit 109 one end is connected with the second mu balanced circuit 111, and feedback circuit 109 other end is connected with the first mu balanced circuit 108.
First logic control circuit 110 one end is connected with the first logic input terminal mouth 103, and the other end of the first logic control circuit 110 is connected with feedback circuit 109.
First logic control circuit 110, according to from the first logic control signal of receiving of the first logic input terminal mouth 103, feedback control circuit 109 feeds back to the size of the feedback current of the first mu balanced circuit 108; First mu balanced circuit 108 varying in size according to the feedback current received, exports the voltage of corresponding size to the second mu balanced circuit 111.
One end of second mu balanced circuit 111 is connected with the first mu balanced circuit 108 and feedback circuit 109, and the other end of the second mu balanced circuit 111 is connected with the second logic control circuit 112; One end again of second mu balanced circuit 111 is connected with voltage output end mouth 102.
Second logic control circuit 112 is connected with the second logic input terminal mouth 104, second voltage input end mouth 106 and tertiary voltage input port 107 respectively.
One end of 3rd mu balanced circuit 113 is connected with tertiary voltage input port 107, and the other end of the 3rd mu balanced circuit 113 is connected with the 3rd logic control circuit 114; One end again of 3rd mu balanced circuit 113 is connected with voltage output end mouth 102.
3rd logic control circuit 114 is connected with the 3rd logic input terminal mouth 105, second voltage input end mouth 106 and tertiary voltage input port 107 respectively.
Wherein, the second logic control circuit 112, by the second logic input terminal mouth 104 receive logic control signal, controls the whether conducting of the second mu balanced circuit 111 according to the second logic control signal received; 3rd logic control circuit 114 receives the 3rd logic control signal by the 3rd logic input terminal mouth 105, controls the whether conducting of the 3rd mu balanced circuit 113 according to the 3rd logic control signal received; When the second mu balanced circuit 111 or the 3rd mu balanced circuit 113 conducting, output voltage is to voltage output end 102.
Preferably, as shown in Figure 2, the first mu balanced circuit 108 comprises the first voltage stabilizing chip 1081 and inductance 1082; Feedback circuit 109 comprises the first resistance 1091, second resistance 1092 and the 3rd resistance 1093; First logic control circuit 110 comprises the first triode 1101 and the 4th resistance 1102.
Wherein, the first port IN of the first voltage stabilizing chip 1081 is connected with the first voltage input end mouth 101; Second port OUT of the first voltage stabilizing chip 1081 is connected with the second mu balanced circuit 111 by inductance 1082.
First resistance 1091, second resistance 1092 and the 3rd resistance 1093 are connected between the second mu balanced circuit 111 and ground, and the 3rd port FB of the first voltage stabilizing chip 1081 is connected between the first resistance 1091 and the second resistance 1092.
The collector of the first triode 1101 is connected between the second resistance 1092 and the 3rd resistance 1093; The grounded emitter of the first triode 1101; The base stage of the first triode 1101 is by the 4th resistance 1102 ground connection, and meanwhile, the base stage of the first triode 1101 is connected with the first logic input terminal mouth 103.
Preferably, as shown in Figure 2, the second mu balanced circuit 111 comprises the second voltage stabilizing chip 1111; Second logic control circuit 112 comprises: the 5th resistance 1121, the 6th resistance 1122, the 7th resistance 1123 and the second triode 1124.
First port S2 of the second voltage stabilizing chip 1111 is connected with inductance 1082 and the first resistance 1091; 3rd port D2 of the second voltage stabilizing chip 1111 is connected with voltage output end mouth 102.
5th resistance 1121 one end is connected with the second voltage input end mouth 106, and the 5th resistance 1121 other end is connected with the second port Q2 of the second voltage stabilizing chip 1111.
6th resistance 1122 one end is connected with the second logic input terminal mouth 104, and the 6th resistance 1122 other end is connected with the base stage of the second triode 1124.
One end of 7th resistance 1123 is connected with tertiary voltage input port 107, and the 7th resistance 1123 other end is connected with the second logic input terminal mouth 104.
The collector of the second triode 1124 is connected with the second port of the second voltage stabilizing chip 1111, the grounded emitter of the second triode 1124.
Preferably, as shown in Figure 2, the 3rd mu balanced circuit 113 comprises the 3rd voltage stabilizing chip 1131; 3rd logic control circuit 114 comprises: the 8th resistance 1141, the 9th resistance 1142, the tenth resistance 1143 and the 3rd triode 1144.
First port S3 of the 3rd voltage stabilizing chip 1131 is connected with tertiary voltage input port 107; 3rd port D3 of the 3rd voltage stabilizing chip 1131 is connected with voltage output end mouth 102.
8th resistance 1141 one end is connected with the second voltage input end mouth 106, and the 8th resistance 1141 other end is connected with the second port Q3 of the 3rd voltage stabilizing chip 1131.
9th resistance 1142 one end is connected with the 3rd logic input terminal mouth 105, and the 9th resistance 1142 other end is connected with the base stage of the 3rd triode 1144.
One end of tenth resistance 1143 is connected with tertiary voltage input port 107, and the tenth resistance 1143 other end is connected with the 3rd logic input terminal mouth 105.
The collector of the 3rd triode 1144 is connected with the second port of the 3rd voltage stabilizing chip 1131, the grounded emitter of the 3rd triode 1144.
Below the specific works principle of the output voltage controlling circuit of the embodiment of the present invention is described.
Under different operating state, the demand of system to voltage is different.System can be operated in two kinds of voltage modes, 3.3V and 5V, when needs process mass data time, uses 5V voltage, when calculated amount is little, or when being under holding state, uses 3.3V voltage.
The first logic control signal arranging the first logic input terminal mouth input is 0 or 1.By controlling the closure or openness as the first triode 1101 of switch, make the 3rd resistance 1093 place in circuit in feedback circuit 109 or by short circuit, change the feedback current being supplied to the first voltage stabilizing chip 1081, to change the output voltage of the first mu balanced circuit 108.
In the present embodiment, by the first logic control signal received, the stably output 5V voltage of the first mu balanced circuit 108 can be controlled.
When the first stabilized circuit outputting voltage is less, can arrange the first logic control signal is 0, and being equivalent to provides a low level in the first triode 1101 base stage, and the first triode 1101 is opened, and the 3rd resistance 1093 is linked in circuit.At this moment, because the first resistance 1091, second resistance 1092 and the 3rd resistance 1093 are connected, feedback circuit 109 resistance increases, electric current on this series circuit reduces, thus the feedback current that the 3rd port FB of the first voltage stabilizing chip 1081 obtains also reduces, the voltage that second port OUT of the first voltage stabilizing chip 1081 exports increases, and makes the voltage exporting 5V at the output terminal of the first mu balanced circuit 108.
When the first stabilized circuit outputting voltage is larger, can arrange the first logic control signal is 1, and being equivalent to provides a high level in the first triode 1101 base stage, and the first triode 1101 closes, and makes the 3rd resistance 1093 by short circuit.At this moment, because the first resistance 1091 and the second resistance 1092 are connected, feedback circuit 109 resistance reduces, electric current on this series circuit increases, thus the feedback current that the 3rd port FB of the first voltage stabilizing chip 1081 obtains also increases, the voltage that second port OUT of the first voltage stabilizing chip 1081 exports reduces, and makes the voltage exporting 5V at the output terminal of the first mu balanced circuit 108.
In the present embodiment, the second voltage input end mouth 106 input voltage is 5V, and tertiary voltage input port 107 input voltage is 3.3V.
The second logic control signal arranging the second logic input terminal mouth 104 input is 0 or 1, and the 3rd logic control signal that the 3rd logic input terminal mouth 105 inputs is 0 or 1.Control the second voltage stabilizing chip or the 3rd voltage stabilizing chip conducting by second and third logic control signal, make the voltage exporting different amplitude at voltage output end mouth 102.
As shown in table 1 below, be that to receive the 3rd logic control signal be 1 to the 0, three logic input terminal mouth 105 when the second logic input terminal mouth 104 receives the second logic control signal.Be equivalent to provide a low level in the base stage of the second triode 1124, second triode 1124 is opened, collector, the emitter current of the second triode 1124 are 0, are equivalent to the off-state of switch between collector and emitter, and the second triode 1124 works in cut-off region.A high level is provided in the base stage of the 3rd triode 1144,3rd triode 1144 closes, the collector and emitter of the 3rd triode 1144 has electric current, is equivalent to the conducting state of switch between collector and emitter, and the 3rd triode 1144 works in saturation region.
Because the second triode 1124 works in cut-off region, at the second port Q2 of the second voltage stabilizing chip 1111, obtain a high level by the 5th resistance 1121, make the second voltage stabilizing chip 1111 conducting; And the 3rd triode 1144 works in saturation region, due to the shunting of triode, make to obtain a low level at the second port Q3 of the 3rd voltage stabilizing chip 1131, the 3rd voltage stabilizing chip 1131 is closed.Therefore, the voltage exported at voltage output end mouth 102 is 5V.
In like manner, be 1 when the second logic input terminal mouth 104 receives the second logic control signal, when the 3rd logic control signal that 3rd logic input terminal mouth 105 receives is 0, be equivalent to provide a high level in the base stage of the second triode 1124, the second triode 1124 closes; There is provided a low level in the base stage of the 3rd triode 1144, the 3rd triode 1144 is opened.Second voltage stabilizing chip 1111 is closed, the 3rd voltage stabilizing chip 1131 conducting, the voltage exported at voltage output end mouth 102 is 3.3V.
Table 1
| Second logic control signal | 3rd logic control signal | Voltage output end |
| 0 | 1 | 5V |
| 1 | 0 | 3.3V |
The output voltage controlling circuit of the embodiment of the present invention, by feeding back to the size of the electric current of voltage stabilizing chip in input logic signal control circuit, and then controls the size of the voltage that described mu balanced circuit exports, to provide stable output voltage.In addition, whether worked by two voltage stabilizing chips in input logic signal control circuit, with in varied situations for system provides different output voltages.Realize while guarantee system is normally run, for system saves electric quantity of power supply.And circuit structure is simple, realize easily, more adequately to control the conversion of output voltage.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (3)
1. an output voltage controlling circuit, it is characterized in that, comprise: the first voltage input end mouth (101), voltage output end mouth (102), first logic input terminal mouth (103), second logic input terminal mouth (104), 3rd logic input terminal mouth (105), second voltage input end mouth (106), tertiary voltage input port (107), first mu balanced circuit (108), feedback circuit (109), first logic control circuit (110), second mu balanced circuit (111), second logic control circuit (112), 3rd mu balanced circuit (113) and the 3rd logic control circuit (114),
Wherein, described first mu balanced circuit (108) one end is connected with described first voltage input end mouth (101), and the other end of described first mu balanced circuit (108) is connected with described second mu balanced circuit (111);
Described feedback circuit (109) one end is connected with described second mu balanced circuit (111), and described feedback circuit (109) other end is connected with described first mu balanced circuit (108);
Described first logic control circuit (110) one end is connected with described first logic input terminal mouth (103), and the other end of described first logic control circuit (110) is connected with feedback circuit (109);
Described first logic control circuit (110), according to the first logic control signal received from described first logic input terminal mouth (103), control the size that described feedback circuit (109) feeds back to the feedback current of described first mu balanced circuit (108); Described first mu balanced circuit (108) varies in size according to the feedback current received, exports the voltage of corresponding size to described second mu balanced circuit (111);
One end of described second mu balanced circuit (111) is connected with described first mu balanced circuit (108) and described feedback circuit (109), and the other end of described second mu balanced circuit (111) is connected with the second logic control circuit (112); One end again of described second mu balanced circuit (111) is connected with described voltage output end mouth (102);
Described second logic control circuit (112) is connected with described second logic input terminal mouth (104), the second voltage input end mouth (106) and tertiary voltage input port (107) respectively;
One end of described 3rd mu balanced circuit (113) is connected with described tertiary voltage input port (107), and the other end of described 3rd mu balanced circuit (113) is connected with the 3rd logic control circuit (114); One end again of described 3rd mu balanced circuit (113) is connected with described voltage output end mouth (102);
Described 3rd logic control circuit (114) is connected with described 3rd logic input terminal mouth (105), the second voltage input end mouth (106) and tertiary voltage input port (107) respectively;
Wherein, described second logic control circuit (112) receives the second logic control signal by the second logic input terminal mouth (104), controls the whether conducting of described second mu balanced circuit (111) according to the second logic control signal received; Described 3rd logic control circuit (114) receives the 3rd logic control signal by the 3rd logic input terminal mouth (105), controls the whether conducting of described 3rd mu balanced circuit (113) according to the 3rd logic control signal received; When described second mu balanced circuit (111) or described 3rd mu balanced circuit (113) conducting, output voltage is to described voltage output end mouth (102);
Described first mu balanced circuit (108) comprises the first voltage stabilizing chip (1081) and inductance (1082); Described feedback circuit (109) comprises the first resistance (1091), the second resistance (1092) and the 3rd resistance (1093); Described first logic control circuit (110) comprises the first triode (1101) and the 4th resistance (1102);
Wherein, the first port of described first voltage stabilizing chip (1081) is connected with described first voltage input end mouth (101); Second port of described first voltage stabilizing chip (1081) is connected with described second mu balanced circuit (111) by described inductance (1082);
Described first resistance (1091), the second resistance (1092) and the 3rd resistance (1093) are connected between described second mu balanced circuit (111) and ground, and the 3rd port of described first voltage stabilizing chip (1081) is connected between described first resistance (1091) and the second resistance (1092);
The collector of described first triode (1101) is connected between described second resistance (1092) and the 3rd resistance (1093); The grounded emitter of described first triode (1101); The base stage of described first triode (1101) is by the 4th resistance (1102) ground connection, and meanwhile, the base stage of described first triode (1101) is connected with described first logic input terminal mouth (103).
2. circuit according to claim 1, is characterized in that, described second mu balanced circuit (111) comprises the second voltage stabilizing chip (1111); Described second logic control circuit (112) comprising: the 5th resistance (1121), the 6th resistance (1122), the 7th resistance (1123) and the second triode (1124);
First port of described second voltage stabilizing chip (1111) is connected with described inductance (1082) and described first resistance (1091); 3rd port of described second voltage stabilizing chip (1111) is connected with described voltage output end mouth (102);
Described 5th resistance (1121) one end is connected with described second voltage input end mouth (106), and described 5th resistance (1121) other end is connected with the second port of described second voltage stabilizing chip (1111);
Described 6th resistance (1122) one end is connected with described second logic input terminal mouth (104), and described 6th resistance (1122) other end is connected with the base stage of described second triode (1124);
One end of described 7th resistance (1123) is connected with described tertiary voltage input port (107), and described 7th resistance (1123) other end is connected with described second logic input terminal mouth (104);
The collector of described second triode (1124) is connected with the second port of described second voltage stabilizing chip (1111), the grounded emitter of described second triode (1124).
3. circuit according to claim 1 and 2, is characterized in that, described 3rd mu balanced circuit (113) comprises the 3rd voltage stabilizing chip (1131); Described 3rd logic control circuit (114) comprising: the 8th resistance (1141), the 9th resistance (1142), the tenth resistance (1143) and the 3rd triode (1144);
First port of described 3rd voltage stabilizing chip (1131) is connected with described tertiary voltage input port (107); 3rd port of described 3rd voltage stabilizing chip (1131) is connected with described voltage output end mouth (102);
Described 8th resistance (1141) one end is connected with described second voltage input end mouth (106), and described 8th resistance (1141) other end is connected with the second port of described 3rd voltage stabilizing chip (1131);
Described 9th resistance (1142) one end is connected with described 3rd logic input terminal mouth (105), and described 9th resistance (1142) other end is connected with the base stage of described 3rd triode (1144);
One end of described tenth resistance (1143) is connected with described tertiary voltage input port (107), and described tenth resistance (1143) other end is connected with described 3rd logic input terminal mouth (105);
The collector of described 3rd triode (1144) is connected with the second port of described 3rd voltage stabilizing chip (1131), the grounded emitter of described 3rd triode (1144).
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| CN203038149U (en) * | 2012-09-28 | 2013-07-03 | 中兴通讯股份有限公司 | Programmable low dropout linear regulator and sampling and feedback circuit thereof |
| CN102957886A (en) * | 2012-11-13 | 2013-03-06 | 广东长虹电子有限公司 | System and method for controlling television set backlight |
| CN103218003A (en) * | 2013-04-26 | 2013-07-24 | 无锡中星微电子有限公司 | Low-dropout voltage stabilizer with multiple power sources input |
| CN203444380U (en) * | 2013-09-11 | 2014-02-19 | 天脉聚源(北京)传媒科技有限公司 | Output voltage control circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103488223A (en) | 2014-01-01 |
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Denomination of invention: A kind of output voltage controlling circuit Effective date of registration: 20170401 Granted publication date: 20151125 Pledgee: Silicon Valley Bank Co.,Ltd. Pledgor: TVMINING (BEIJING) MEDIA TECHNOLOGY Co.,Ltd. Registration number: 2017310000019 |
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