CN103475355A

CN103475355A - Single-particle resistant transient pulse CMOS circuit

Info

Publication number: CN103475355A
Application number: CN2013104496088A
Authority: CN
Inventors: 宿晓慧; 毕津顺; 罗家俊; 韩郑生; 郝乐
Original assignee: Institute of Microelectronics of CAS
Current assignee: Institute of Microelectronics of CAS
Priority date: 2013-09-24
Filing date: 2013-09-24
Publication date: 2013-12-25

Abstract

The invention provides a single-particle resistant transient pulse CMOS circuit which comprises a first buffer (101), a second buffer (102), four MOS tubes and an output inverter. The input end of the first buffer (101) is connected with input signals to output first buffer signals (out1) to be used for eliminating low-high-low type pulses, the input end of the second buffer (102) is connected with the input signals to output second buffer signals (out2) to be used for eliminating high-low-high type pulses, when the electric level of the first buffer signals (out1) and the electric level of the second buffer signals (out2) are equal, the electric level which is equal to the electric level of the first buffer signals (out1) and the electric level of the second buffer signals (out2) is output (out put) through the output inverter, otherwise the electric level is kept unchanged, and accordingly the single-particle resistant transient pulse is achieved. Required MOSs in the single-particle transient pulse resistant CMOS circuit are fewer, and the single-particle resistant transient pulse CMOS circuit is small in size and good in filtering effect.

Description

Anti-single particle transient pulse cmos circuit

Technical field

The present invention relates to radiation hardened circuit engineering field, specifically, the present invention relates to a kind of anti-single particle transient pulse circuit.

Background technology

Space technology is to weigh the important symbol of a modernization of the country level and overall national strength, and integrated circuit is as the core of spacecraft, and oneself becomes one of main indexes of various spacecraft performances its performance and function.In order to tackle the challenge of current and following space technology development, each state is all actively developing the integrated circuit of high-performance, highly anti-radiation ability.Rapidly, the anti-irradiation integrated circuits of great AEROSPACE APPLICATION such as the manned astro-engineering, lunar exploration engineering, " Big Dipper " navigation positioning system, " Heavenly Palace " have proposed urgent demand in China's aerospace industry development in recent years.

Single particle effect, refer to the high energy particle existed in the radiation environments such as space flight and ground, causes the radiation damage effect that ionising radiation produces in the chip internal sensitizing range.Ionising radiation produces intensive electrons pair on the Particles Moving track, when these electrons, when being collected by circuit node, may change the circuit normal operating conditions, causes error in data, works not normal, and chip such as burns at the serious consequence.

Single particle effect mainly can be divided into two large classes:

Hard error: refer to and cause the permanent damage of device own, as single event burnout, the single-particle grid are worn etc.;

Soft error: refer to that the circuit logic level changes, the storage data make a mistake, but device itself does not cause permanent damage.Its topmost two types is single-particle inversion and single-event transients.

Single-particle inversion refers to that radiation causes the memory circuit state to overturn, and usually occurs in the Mass storage array such as SRAM DRAM, and the error rate that single-particle inversion produces is with the clock frequency-independent;

Single-ion transient state SET (Si ngl e Event Transi ent) refers to that radiation causes circuit node voltage, electric current to produce transient change, produce single event transient pulse, this pulse is propagated and can be caused phase-locked loop in circuit, the analog circuit operation irregularities such as operational amplifier, also may be transferred to the input of memory circuit, cause the write error data.The error rate that single-event transients produces increases with the increase of clock frequency is linear.

Along with the increase of process reduction and clock frequency, single particle effect causes that the inefficacy of integrated circuit is more and more serious, and single event transient pulse has surpassed the main source that single-particle inversion becomes soft error.Therefore design a kind of circuit, filtering single event transient pulse signal, can effectively prevent that the continuation of transient pulse from propagating, and avoids the impact on late-class circuit, will significantly improve the anti-single particle level of circuit.

Main anti-single particle transient pulse circuit mainly contains two classes at present: time redundancy method, spatial redundancy method.Delay-ruling circuit is common time redundancy method, and the method refers to the output of combinational logic, respectively through 2 different time-delay access, original signal and two inhibit signals to be inputed to the ruling circuit, and the ruling circuit determines final output by majority voting.Common spatial redundancy method is three times of redundant circuits, makees three the same combinational circuits, and the three exports to the ruling circuit, according to majority voting output correct result, needs the area of primary circuit more than 3 times.Improved dual-redundancey structure, also need original area more than 2 times.And the time redundancy method also needs larger area to realize that two-way postpones path.

At present, the somebody has proposed by improving the time redundancy Sampling techniques of end timing unit, and the output with the clock of out of phase at a plurality of time point sampling latch combinational logics carrys out filtering SET pulse by sampled result relatively.Adopt the method also to need to realize two-stage phase delay, and three latchs and ruling circuit, hardware consumption is larger.

Summary of the invention

The object of the present invention is to provide a kind of anti-single particle transient pulse circuit that can address the above problem.

In one aspect, the invention provides a kind of anti-single particle transient pulse cmos circuit,

Comprise:

The first buffer, its input receives input signal, and its output is exported the first buffering signals, for eliminating " low height " type pulse;

The second buffer, its input receives input signal, and its output is exported the second buffering signals, for eliminating " height is high " type pulse;

The one PMOS pipe, the 2nd PMOS pipe, a NMOS pipe and the 2nd NMOS pipe, wherein the source of a PMOS pipe connects supply voltage, the drain terminal of the one PMOS pipe connects the source of the 2nd PMOS pipe, the drain terminal of the 2nd PMOS pipe connects the drain terminal of a NMOS pipe, the source of the one NMOS pipe connects the drain terminal of the 2nd NMOS pipe, the source ground connection of the 2nd NMOS pipe;

The output inverter, its input connects the drain terminal of a NMOS pipe, and the output signal of output inverter is as the output signal of anti-single particle transient pulse cmos circuit, wherein

The grid of the one PMOS pipe connects any in the second buffering signals and the first buffering signals, and the grid of the 2nd PMOS pipe connects another in the second buffering signals and the first buffering signals; The grid of the one NMOS pipe connects any in the second buffering signals and the first buffering signals, and the grid of the 2nd PMOS pipe connects another in the second buffering signals and the first buffering signals.

The first buffer (101) consists of the even number of inverters cascade, what connect input signal is first order inverter, wherein, in the odd level inverter, the PMOS pipe is greater than the ratio of electron mobility and hole mobility with the ratio of NMOS pipe breadth length ratio, and in the even level inverter, the PMOS pipe is less than the ratio of electron mobility and hole mobility with the ratio of NMOS pipe breadth length ratio.

The second buffer (102) consists of the even number of inverters cascade, what connect input signal is first order inverter, wherein, in the odd level inverter, the PMOS pipe is less than the ratio of electron mobility and hole mobility with the ratio of NMOS pipe breadth length ratio, and in the even level inverter, the ratio of the wide same NMOS pipe breadth length ratio of PMOS pipe is greater than the ratio of electron mobility and hole mobility.

Because the breadth length ratio of inverter PMOS pipe and NMOS pipe in buffer is not mated, cause on inverter to draw/drop-down driving force is asymmetric, makes the output signal rise/fall postpone different, thus realize output pulse stretching/compression.For the first buffer, input " low height " type pulse, output pulse width will compress, input " height is high " type pulse, the output pulse is by broadening.And the ratio of metal-oxide-semiconductor breadth length ratio is larger with difference between the ratio of electron mobility and hole mobility, and inverter progression is more, output pulse stretching/suppressed range is larger.Pulse duration according to wanted filtering, by selecting applicable metal-oxide-semiconductor breadth length ratio and inverter progression, while making input pulsewidth scope be positioned at " low height " type pulse of filtering scope, output pulse width will be compressed to 0, output keeps low level, realizes the purpose of " low height " type pulse of filtering.In like manner, the second buffer can filtering pulsewidth scope be positioned at " height is high " type pulse of filtering scope, and output keeps high level.

The present invention utilizes 4 metal-oxide-semiconductors and inverter, and while making output signal level when the first buffer and the second buffer identical, anti-single particle impulse circuit output signal equals the output signal of the first buffer and the second buffer; And, when the two is different, anti-single particle transient pulse circuit output signal remains unchanged.While due to input signal, being subject to the single-particle impulse disturbances, the output signal pulses of the first buffer and the second buffer respectively can filtering and broadening, cause the two output level difference, now by metal-oxide-semiconductor and inverter effect, to make output level not be subject to the single-particle impulse disturbances, thus realize can filtering " low height " again can filtering " height is high " type pulse purpose.

Adopt the present invention can the filtering single event transient pulse to the interference of input signal, there is anti-single particle transient pulse ability strong, simple in structure, the advantage such as area is little, low in energy consumption.By regulating size and the progression of buffer circuits, can regulate width range and the output delay of the single-particle pulse of filtering.For example increase PMOS pipe in buffer with the breadth length ratio of NMOS pipe with electron mobility the difference with the ratio of hole mobility, perhaps increase inverter progression separately, can enlarge the filtering pulse width range, but output delay increases thereupon, otherwise, the filtering scope diminishes, but output delay also reduces thereupon.Can based on the actual application requirements, be chosen.

The accompanying drawing explanation

The structural representation of the Anti-single event transient circuit that Fig. 1 provides for one embodiment of the invention;

The electrical block diagram of the first buffer that Fig. 2 provides for one embodiment of the invention;

The electrical block diagram of the second buffer that Fig. 3 provides for one embodiment of the invention;

The Anti-single event transient circuit work wave schematic diagram that Fig. 4 provides for one embodiment of the present of invention.

Embodiment

For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and, with reference to accompanying drawing, the present invention is described in more detail.

Fig. 1 shows the structural representation of the anti-single particle transient pulse cmos circuit that one embodiment of the present of invention provide.Comprise:

The first buffer 101, its input receives input signal i nput, and its output is exported the first buffering signals out1, for eliminating " low height " type pulse;

The second buffer 102, its input receives input signal i nput, and its output is exported the second buffering signals out2, for eliminating " height is high " type pulse;

The one PMOS pipe the 103, the 2nd PMOS pipe the 104, the one NMOS pipe the 105 and the 2nd NSOS pipe 106, wherein the source of a PMOS pipe 103 connects supply voltage, the drain terminal of the one PMOS pipe 103 connects the source of the 2nd PMOS pipe 104, the drain terminal of the 2nd PMOS pipe 104 connects the drain terminal of a NMOS pipe 105, the source of the one NMOS pipe 105 connects the drain terminal of the 2nd NMOS pipe 106, the source ground connection of the 2nd NMOS pipe 106;

Output inverter 107, its input connects the drain terminal of a NMOS pipe 105, and the output signal out put of output inverter 107 is as the output signal of anti-single particle transient pulse cmos circuit, wherein:

The grid of the one PMOS pipe 103 connects any in the second buffering signals out2 and the first buffering signals out1, and the grid of the 2nd PMOS pipe 104 connects another in the second buffering signals out2 and the first buffering signals out1; The grid of the one NMOS pipe 105 connects any in the second buffering signals out2 and the first buffering signals out1, and the grid of the 2nd PMOS pipe 106 connects another in the second buffering signals out2 and the first buffering signals out1.

In embodiments of the invention, by type and the width range of the single event transient pulse of filtering as required, determine type, the sum of series size of buffer.Embodiments of the invention can adopt 0.18 micrometre CMOS process to realize, under deep submicron process, electron mobility is 2 ~ 3 with the ratio of hole mobility, and in buffer, the metal-oxide-semiconductor breadth length ratio is different larger with this value difference, and buffer broadening/compressed capability is stronger.For the present embodiment, it can filter the single-particle pulse signal that pulsewidth is no more than 1ns designing requirement.

Owing to there being two kinds of dissimilar single-particle pulses, i.e. " low-Gao-low " type pulse and the pulse of " high-low-high " type, therefore, need two kinds of dissimilar buffers to carry out respectively filtering.

The first buffer 101 is designed for elimination " low-Gao-low " type pulse.For this reason, the first buffer 101 can consist of the even number of inverters cascade, what connect input signal is first order inverter, wherein, in the odd level inverter, the PMOB pipe is greater than the ratio of electron mobility and hole mobility with the ratio of NMOS pipe breadth length ratio, and in the even level inverter, the PMOS pipe is less than the ratio of electron mobility and hole mobility with the ratio of NMOS pipe breadth length ratio.While in order to make, inputting the 1ns pulse, output pulse width is reduced to 0, in one embodiment, considers metal-oxide-semiconductor breadth length ratio ratio and buffer progression, by emulation, determines, the first buffer 101 consists of 4 inverter cascades.As shown in Figure 2,

PMOS pipe

201 and 205,

NMOS pipe

204 and 208 breadth length ratios all are made as 10 microns/0.18 micron, and

PM3B pipe

203 and 207,

NMOS pipe

202 and 206 breadth length ratios all are made as 0.5 micron/0.18 micron.

The second buffer 101 is designed for the pulse of elimination " high-low-high " type.For this reason, the second buffer 102 can consist of the even number of inverters cascade, and what connect input signal be first order inverter, and wherein, the ratio that in the odd level inverter, the PMOS pipe is managed breadth length ratio with NMOS is less than the ratio of electron mobility and hole mobility; In the even level inverter, the PMOS pipe is greater than the ratio of electron mobility and hole mobility with the ratio of NMOS pipe breadth length ratio.In one embodiment, the second buffer 102 consists of 4 inverter cascades, and as shown in Figure 3,

PMOS pipe

303 and 307,

NMOS pipe

302 and 306 breadth length ratios are 10 microns/0.18 micron;

PMOB pipe

301 and 305,

NMOS pipe

304 and 308 breadth length ratios are 0.5 micron/0.18 micron.

In one embodiment, it is 9 microns/0.18 micron that PMOS pipe the 103 and the 2nd PMOS manages 104 breadth length ratios, and it is 3 microns/0.18 micron that NMOS pipe the 105 and the 2nd NMOS manages 106 breadth length ratios.

In one embodiment, in output inverter 107, PMOB pipe breadth length ratio is 9 microns/0.18 micron, and NMOS pipe breadth length ratio is 3 microns/0.18 micron.

The Anti-single event transient circuit work wave schematic diagram that Fig. 4 provides for one embodiment of the present of invention, power supply is pressed 1.8V, is respectively from top to bottom circuit input signal i nput, circuit output signal out put, internal signal out1, internal signal out2.As shown in the figure, during circuit working, i nput is as the input signal of

buffer

101 and 102, the output signal that out1 is buffer 101, the output signal that out2 is buffer 102.

After Ons, i nput is high level, and out1 and out2 are high level, 103 and 104 cut-offs of PMOS pipe, and NMOS manages 105 and 106 conductings, and inverter 107 input signals are low level, and inverter 107 output signal out put are high level.

When 10ns, i nput produces " height is high " type impulse disturbances of a 1ns, observe known, buffer 102 filtering interfering pulses, out2 is stable high level; Buffer 101 output pulse stretchings, the out1 output pulse width is about " height is high " type pulse signal of 2.2ns.When out1 is low level, 103 conductings, 104 cut-offs, 105 conductings, 106 cut-offs, because the out1 low level time is extremely short, interior electric leakage during this period of time is very little, makes 107 input Level holds constant, is always low level, and out put is always high level.When out1 reverts to high level, 103 and 104 cut-offs, 105 and 106 conductings, 107 input signal low levels, output signal out put is still high level, has realized the purpose of filtering " height is high " type disturbing pulse.

When 20ns, i nput becomes low level, out1 output low level now, and the out2 output low level, 103 and 104 conductings, 105 and 106 cut-offs, 107 input signals are high level, output signal out put is low level.

When 30ns, " low height " type disturbing pulse that it is 1ns that i nput produces a pulse duration, this disturbing pulse of now buffer 101 filterings, out1 is low level, this pulse of buffer 102 broadenings, out2 exports the high level of about 2.3ns.When out2 is high level, 103 conductings, 104 cut-offs, 105 conductings, 106 cut-offs, because this period is very short, make electric leakage very little, so the input signal of inverter 107 remains unchanged, and is always high level, and out put is low level.When out2 reverts to high level, 103 and 104 conductings, 105 and 106 cut-offs, 107 input signals are high level, output signal out put is still low level.Realized the purpose of filtering " low height " type disturbing pulse.

When 40ns, i nput becomes high level, now out1 output high level, and out2 exports high level, 103 and 104 cut-offs, 105 and 106 conductings, 107 input signals are low level, output signal out put is high level.

In design process, the ratio of the breadth length ratio of increase NMOS pipe and PMOS pipe is the difference with the ratio of hole mobility with electron mobility, perhaps increase the progression of inverter in buffer, the first buffer 101 and the second buffer 102 can filtering pulse duration will be larger, but the broadening of paired pulses is also more obvious, make the delay of output signal out put also will become large, therefore in actual design, adopt the size design of 10 microns/0.18 micron and 0.5 micron/0.18 micron, 4 grades of inverter structures, can the filtering pulse duration be not more than the pulse of 1ns, out put postpones for 1.4ns with respect to i nput trailing edge, rise edge delay is 1.3ns.

Because adopting the

buffer

101 and 102 of different drop-down driving forces, the present invention carrys out the disturbing pulse of filtering corresponding " low height " or " height is high " form, adopt 4 metal-oxide-semiconductors and 1 inverter to utilize 101 and 102 output signals to produce the anti-single particle pulse signal, due to without delay circuit, therefore only adopt in an embodiment 22 metal-oxide-semiconductors, metal-oxide-semiconductor full-size used is only 10 microns/0.18 micron, if adopt Muller C method at least to need the metal-oxide-semiconductor that 30 full-sizes are 10 microns/0.18 micron, show that area of the present invention is little, low in energy consumption; Simultaneously because single event transient pulse is no more than 1ns usually, but adopt all filterings of the present embodiment, and output waveform shows that smoothly without burr anti-single particle transient pulse ability of the present invention is strong, filtration result is good.

Above-described embodiment is preferably execution mode of the present invention; but embodiments of the present invention are not restricted to the described embodiments; other any do not deviate from change, the modification done under Spirit Essence of the present invention and principle, substitutes, combination, simplify; all should be equivalent substitute mode, within being included in protection scope of the present invention.

Claims

1. an anti-single particle transient pulse cmos circuit comprises:

The first buffer (101), its input receives input signal (i nput), and its output is exported the first buffering signals (out1), for eliminating " low height " type pulse;

The second buffer (102), its input receives input signal (i nput), and its output is exported the second buffering signals (out2), for eliminating " height is high " type pulse;

The one PMOS pipe (103), the 2nd PMOS pipe (104), a NMOS pipe (105) and the 2nd NMOS pipe (106), wherein the source of a PMOS pipe (103) connects supply voltage, the drain terminal of the one PMOS pipe (103) connects the source of the 2nd PMOS pipe (104), the drain terminal of the 2nd PMOS pipe (104) connects the drain terminal of a NMOS pipe (105), the source of the one NMOS pipe (105) connects the drain terminal of the 2nd NMOS pipe (106), the source ground connection of the 2nd NMOS pipe (106):

Output inverter (107), its input connects the drain terminal of a NMOS pipe (105), and the output signal (out put) of output inverter (107) is as the output signal of anti-single particle transient pulse cmos circuit, wherein

The grid of the one PMOS pipe (103) connects any in the second buffering signals (out2) and the first buffering signals (out1), and the grid of the 2nd PMOS pipe (104) connects another in the second buffering signals (out2) and the first buffering signals (out1); The grid of the one NMOS pipe (105) connects any in the second buffering signals (out2) and the first buffering signals (out1), and the grid of the 2nd PMOS pipe (106) connects another in the second buffering signals (out2) and the first buffering signals (out1).

2. circuit according to claim 1, it is characterized in that, described the first buffer (101) consists of the even number of inverters cascade, what connect input signal is first order inverter, wherein, in the odd level inverter, the PMOS pipe is greater than the ratio of electron mobility and hole mobility with the ratio of NMOS pipe breadth length ratio, and in the even level inverter, the PMOS pipe is less than the ratio of electron mobility and hole mobility with the ratio of NMOS pipe breadth length ratio.

3. circuit according to claim 1, it is characterized in that, described the second buffer (102) consists of the even number of inverters cascade, what connect input signal is first order inverter, wherein, in the odd level inverter, the PMOS pipe is less than the ratio of electron mobility and hole mobility with the ratio of NMOS pipe breadth length ratio, and in the even level inverter, the PMOS pipe is greater than the ratio of electron mobility and hole mobility with the ratio of NMOS pipe breadth length ratio.