CN103456698A - Chip package structure and chip packaging method - Google Patents
Chip package structure and chip packaging method Download PDFInfo
- Publication number
- CN103456698A CN103456698A CN2012101762111A CN201210176211A CN103456698A CN 103456698 A CN103456698 A CN 103456698A CN 2012101762111 A CN2012101762111 A CN 2012101762111A CN 201210176211 A CN201210176211 A CN 201210176211A CN 103456698 A CN103456698 A CN 103456698A
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- China
- Prior art keywords
- chip
- sidewall
- circuit board
- weld pad
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
A chip package structure comprises a circuit board, a chip disposed on the circuit board, and a protective frame disposed on the circuit board. The chip is electrically connected to the circuit board through a plurality of leads. The protective frame comprises a side wall enclosing the chip. The side wall is provided with a plurality of through holes passing through the inner and outer surfaces of the side wall. The protective frame is filled with package glue which covers the chip and the leads and which is combined to the inner surface of the side wall. The outer surface of the side wall is coated with a cover layer which locates outside the through holes and which is used for sealing the through holes. The side wall of the protective frame is provided with the through holes; the through holes are filled with a small part of the package glue when the package glue is heated and expands; accordingly, internal stress generated by the package glue is relieved through the through holes, and the glue is prevented from pressing the leads and damaging the leads. The cover layer can prevent moisture outside the protective frame from entering the protective frame through the side wall. The invention further relates to a chip packaging method.
Description
Technical field
The present invention relates to a kind of chip-packaging structure and method.
Background technology
Existing a kind of chip-packaging structure comprises a chip, a circuit board and a bearer bar.Chip is reached and is electrically connected to by wire-bonded (wire bonding) with circuit board.Bearer bar is arranged on circuit board and comprises the sidewall be located in outside chip; be filled with the packing colloid of being combined with the inner surface of sidewall in bearer bar; by packing colloid, chip and lead-in wire are encapsulated to protect chip and lead-in wire, bearer bar is bonded on circuit board by packing colloid.In order to prevent that the outside steam of bearer bar from entering bearer bar and affect chip from sidewall, sidewall is typically designed to continuous atresia.Yet; chip can produce amount of heat and heat is reached to packing colloid when work; due to packing colloid and the bearer bar materials variances larger; also there is larger difference in thermal coefficient of expansion; packing colloid is heated and will expands and produce internal stress extruding bearer bar; so cause the packing colloid swaged lead and may damage lead-in wire, reduced the reliability that chip is electrically connected to circuit board.
Summary of the invention
In view of this, be necessary to provide a kind of chip-packaging structure and chip packaging method that can improve chip and circuit board reliability of electrical connection.
A kind of chip-packaging structure, comprise a circuit board, chip and a bearer bar be arranged on circuit board be arranged on described circuit board.Described chip is electrically connected and described circuit board by many lead-in wires.Described bearer bar comprises that is located in the outer sidewall of described chip, and described sidewall offers a plurality of inner surface of described sidewall and through holes of outer surface of running through.Be filled with in described bearer bar and cover described chip and packing colloid described lead-in wire and that be combined with the inner surface of sidewall.Be coated with the covering layer for shutoff described through hole of one deck outside described through hole on the outer surface of described sidewall.
A kind of chip packaging method, comprise the steps:
A circuit board and a chip are provided, and described chip is arranged on described circuit board and by many lead-in wires and is electrically connected to described circuit board;
A bearer bar is provided, describedly comprises that one comprises that is located in the outer sidewall of described chip, described sidewall offers a plurality of inner surface of described sidewall and through holes of outer surface of running through;
Fill packing colloid in described bearer bar, described packing colloid covers described chip and described lead-in wire and is combined with the inner surface of sidewall;
Be coated with the covering layer for shutoff described through hole of one deck outside described through hole on the outer surface of described sidewall.
With respect to prior art, the sidewall of described bearer bar offers a plurality of through holes, when described packing colloid expanded by heating, the sub-fraction packing colloid will be inserted in through hole, the internal stress that therefore described packing colloid produces can discharge by described through hole, avoid described colloid swaged lead and damage lead-in wire, improve the reliability of electrical connection between described chip and described circuit board; In addition, described covering layer can prevent that the steam of bearer bar outside from entering described bearer bar from described sidewall.
The accompanying drawing explanation
Fig. 1 is the schematic cross-section of chip-packaging structure provided by the invention.
Fig. 2 be the chip-packaging structure shown in Fig. 1 schematic top plan view.
Fig. 3 is the flow chart of chip packaging method of the present invention.
The main element symbol description
| Chip- |
100 |
| |
10 |
| Loading |
101 |
| The |
102 |
| |
20 |
| |
201 |
| |
202 |
| |
203 |
| The |
204 |
| The |
205 |
| |
30 |
| |
301 |
| |
3011 |
| |
3012 |
| |
302 |
| |
303 |
| Through |
304 |
| |
305 |
| |
306 |
| Lead-in |
40 |
| |
50 |
| Adhesive- |
60 |
| |
70 |
| |
80 |
Following embodiment further illustrates the present invention in connection with above-mentioned accompanying drawing.
Embodiment
Refer to Fig. 1 Fig. 2, chip-packaging structure 100 provided by the invention comprises a circuit board 10, chip 20 and a bearer bar 30.Described chip 20 is electrically connected to described circuit board 10 by many lead-in wires 40, and described lead-in wire 40 is gold thread or aluminum steel.Described bearer bar 30 comprises that is located in the outer sidewall 301 of described chip 20, and described sidewall 301 offers a plurality of outer surface 302 of described sidewall and through holes 304 of inner surface 303 of running through.In described bearer bar 30, be filled with cover described chip 20 and described lead-in wire 40 and with the packing colloid 50 of inner surface 303 combinations of sidewall 301.Apply one deck covering layer 80 on the outer surface 302 of described sidewall 301, described covering layer 80 is for the described through hole 304 of shutoff.
Concrete, described circuit board 10 comprises a loading end 101.Be provided with a plurality of the first weld pads 102 on described loading end 101.
Described chip 20 is digital micro-mirror chip (digital micromirror device, DMD), the semiconductor element that described digital micro-mirror chip comprises into micro mirror (micromirro) of array distribution and drives micro mirror to rotate.Described chip 20 is roughly rectangle and comprises the opposing end face in a bottom surface 201, and described bottom surface 201 202, first end 203 and second end 204.Described bottom surface 201 is fixed on described loading end 101 by one deck adhesive-layer 60.Be coated with a glass plate 70 on described end face 202.In present embodiment, described glass plate 70 is the clear glass for the protection of described chip 20, and the area of described glass plate 70 is less than the area of described end face 202.Described first end 203 is near described the first weld pad 102.Described end face 202 is provided with a plurality of the second weld pads 205 corresponding to described the first weld pad 102 near the position of described first end 203.Each second weld pad 205 is soldered to corresponding first weld pad 102 by a lead-in wire 40, so makes reaching between described chip 20 and described circuit board 10 be electrically connected to.
Described bearer bar 30 is made by metal material, and in present embodiment, described bearer bar 30 is made by copper or aluminium.Described bearer bar 30 is roughly rectangle, and it comprises a pair of long sidewall 3011 and a pair of and described long sidewall 3011 short sidewall 3012 connected vertically.Described a pair of long sidewall 3011 and the described sidewall 301 of described a pair of short sidewall 3012 common composition.Described a pair of short sidewall 3012 extends to form a pair of inner edge portion 305 in opposite directions, and described a pair of inner edge portion 305 surrounds a window 306 jointly with a pair of long sidewall 3011, and described window 306 is for passing through for example light signal of external signal.One of them short sidewall 3012 is near described the first weld pad 102, and this offers a plurality of outer surface 302 of described sidewall 301 and through holes 304 of inner surface 303 of running through near on the short sidewall 3012 of described the first weld pad 102.
Be filled with the described packing colloid 50 that covers described glass plate 70, described chip 20 and described lead-in wire 40 in described bearer bar 30, described packing colloid 50 contacts with the inner surface 303 of described sidewall 301 and the loading end 101 of circuit board 10.Can produce heat during described chip-packaging structure 100 work, making described packing colloid 50 be heated expands, because this offers a plurality of through holes 304 near on the short sidewall 3012 of described the first weld pad 102, the packing colloid 50 of described expansion is partially filled in described through hole 304, so, can discharge the internal stress of packing colloid 50 because of the described inner surface 303 of extruding of the generation of expanding, thereby avoid the described packing colloid 50 described lead-in wires 40 of extruding and damage described lead-in wire 40.Further, described a pair of long sidewall 3011 offers a plurality of described through holes 304 equally in the position near offering the short sidewall 3012 of through hole 304.So, the through hole 304 on described long sidewall 3011 can be filled the described packing colloid 50 after expansion further.In other embodiments, also can only near on the short sidewall 3012 of described the first weld pad 102, offer described through hole 304.
In present embodiment, described packing colloid 50 is that ultraviolet light (ultraviolet, UV) solidifies glue, because UV solidifies glue, need under UV-irradiation, heat and be cured.UV solidifies be heated rear expansion produce the inner surface 303 that internal stress is pushed described sidewall 301 of glue.Owing on this close short sidewall 3012 of described the first weld pad 102, reaching on described a pair of long sidewall 3011 and offering described through hole 304, the UV of described expansion solidifies glue and is partially filled in described through hole 304, so, can discharge the internal stress that UV solidifies the described inner surface 303 of extruding of glue expansion generation, avoid described UV to solidify glue and push described lead-in wire 40, thereby prevent from damaging described lead-in wire 40 when the described UV that is heating and curing solidifies glue.
Be coated with one deck covering layer 80 on the outer surface 302 of described sidewall 301; described covering layer 80 is coated on the short sidewall 3012 and a pair of long sidewall 3011 of offering through hole 304 to some extent; described covering layer 80 is for the described through hole 304 of shutoff; prevent that outside steam from entering described bearer bar 30 from described through hole 304; wherein said covering layer 80 is formed on outer surface 302 and is not contained in described through hole 304, and described covering layer 80 is outside described through hole 304.In other execution modes, described covering layer 80 also can partly be contained in described through hole 304, but the thickness that is contained in the described covering layer 80 in described through hole 304 should be less than the degree of depth of described through hole 304.In present embodiment, described covering layer 80 also solidifies glue for UV.
Refer to Fig. 3, the flow chart of chip packaging method of the present invention comprises the following steps:
S1: described circuit board 10 and described chip 20 are provided, and described chip 20 is arranged on described circuit board 10 and by described many lead-in wires 40 and is electrically connected to described circuit board 10;
S2: a bearer bar 30 is provided, describedly comprises that one comprises that is located in the outer sidewall 301 of described chip 20, described sidewall 301 offers a plurality of outer surface of described sidewall 301 and through holes 304 of inner surface of running through;
S3: at the described packing colloid 50 of the interior filling of described bearer bar 30, described packing colloid 50 cover described chips 20 and described lead-in wire 40 and with inner surface 303 combinations of sidewall 301;
S4: apply one deck covering layer 80 on the outer surface 302 of described sidewall 301, described covering layer 80 is coated on the short sidewall 3012 and a pair of long sidewall 3011 of offering through hole 304 to some extent, and described covering layer 80 is for the described through hole 304 of shutoff.
Further, between step S2 and S3, further comprise: settle described glass plate 70 on described chip 20.The packing colloid 50 of filling in described step S3 further covers described glass plate 70.
In other embodiments, described chip 20 is an image sensor, and described glass plate 70 is a cutoff filter (infrared cut filter), and described cutoff filter sees through visible ray for absorbing infrared light.
In addition, those skilled in the art also can do other variation in spirit of the present invention, and certainly, the variation that these are done according to spirit of the present invention, within all should being included in the present invention's scope required for protection.
Claims (10)
1. a chip-packaging structure, comprise a circuit board, chip and a bearer bar be arranged on circuit board be arranged on described circuit board; Described chip is electrically connected and described circuit board by many lead-in wires; Described bearer bar comprises that is located in the outer sidewall of described chip, and described sidewall offers a plurality of inner surface of described sidewall and through holes of outer surface of running through; Be filled with in described bearer bar and cover described chip and packing colloid described lead-in wire and that be combined with the inner surface of sidewall; Be coated with the covering layer for shutoff described through hole of one deck outside described through hole on the outer surface of described sidewall.
2. chip-packaging structure as claimed in claim 1 is characterized in that: described chip comprises end face and the first end that a bottom surface, and described bottom surface are opposing; Described underrun one deck adhesive-layer is fixed on described circuit board; Be coated with a glass plate on described end face, described packing colloid also covers described glass plate.
3. chip-packaging structure as claimed in claim 2, is characterized in that: be provided with a plurality of the first weld pads on described circuit board, close described the first weld pad of described first end; Described end face is provided with a plurality of the second weld pads corresponding to described the first weld pad near the position of described first end, and each second weld pad is connected to corresponding first weld pad by a described lead-in wire.
4. chip-packaging structure as claimed in claim 3, it is characterized in that: described bearer bar is rectangle, described sidewall is comprised of a pair of long sidewall and a pair of and described long sidewall short sidewall connected vertically; One of them short sidewall is near described the first weld pad, and described through hole is opened in this near on the short sidewall of described the first weld pad.
5. chip-packaging structure as claimed in claim 4, it is characterized in that: described a pair of short sidewall extends to form a pair of inner edge portion in opposite directions, and described a pair of inner edge portion and described a pair of long sidewall surround a window jointly.
6. chip-packaging structure as claimed in claim 4 is characterized in that: described a pair of long sidewall also offers described through hole in the position near offering the short sidewall of through hole.
7. a chip packaging method, comprise the steps:
S1: a circuit board and a chip are provided, and described chip is arranged on described circuit board and by many lead-in wires and is electrically connected to described circuit board;
S2: a bearer bar is provided, and described bearer bar comprises that is located in the outer sidewall of described chip, and described sidewall offers a plurality of inner surface of described sidewall and through holes of outer surface of running through;
S3: fill packing colloid in described bearer bar, described packing colloid covers described chip and described lead-in wire and is combined with the inner surface of sidewall;
S4: apply the covering layer for shutoff described through hole of one deck outside described through hole on the outer surface of described sidewall.
8. chip packaging method as claimed in claim 7 is characterized in that: between step S2 and S3, further comprise:
Settle a glass plate on described chip, the packing colloid of filling in described step S3 further covers described glass plate.
9. chip packaging method as claimed in claim 8, is characterized in that: be provided with a plurality of the first weld pads on described circuit board, close described the first weld pad of described first end; Described end face is provided with a plurality of the second weld pads corresponding to described the first weld pad near the position of described first end, and each second weld pad is connected to corresponding first weld pad by a described lead-in wire.
10. chip packaging method as claimed in claim 9, it is characterized in that: described bearer bar is rectangle, described sidewall is comprised of a pair of long sidewall and a pair of and described long sidewall short sidewall connected vertically; One of them short sidewall is near described the first weld pad, and described through hole is opened in this near on the short sidewall of described the first weld pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012101762111A CN103456698A (en) | 2012-05-31 | 2012-05-31 | Chip package structure and chip packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012101762111A CN103456698A (en) | 2012-05-31 | 2012-05-31 | Chip package structure and chip packaging method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103456698A true CN103456698A (en) | 2013-12-18 |
Family
ID=49738916
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012101762111A Pending CN103456698A (en) | 2012-05-31 | 2012-05-31 | Chip package structure and chip packaging method |
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| CN (1) | CN103456698A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116360159A (en) * | 2023-06-02 | 2023-06-30 | 惠科股份有限公司 | Light-emitting module and display device |
-
2012
- 2012-05-31 CN CN2012101762111A patent/CN103456698A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116360159A (en) * | 2023-06-02 | 2023-06-30 | 惠科股份有限公司 | Light-emitting module and display device |
| CN116360159B (en) * | 2023-06-02 | 2023-09-05 | 惠科股份有限公司 | Light-emitting module and display device |
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Application publication date: 20131218 |