CN103456655B - The detection method of semiconductor blind hole - Google Patents
The detection method of semiconductor blind hole Download PDFInfo
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- CN103456655B CN103456655B CN201210174235.3A CN201210174235A CN103456655B CN 103456655 B CN103456655 B CN 103456655B CN 201210174235 A CN201210174235 A CN 201210174235A CN 103456655 B CN103456655 B CN 103456655B
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- blind hole
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- barrier
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Abstract
The invention discloses a kind of detection method of semiconductor blind hole, comprise the semiconductor base providing to comprise conduction region; Form multiple blind hole exposing conduction region; The sidewall of at least one described multiple blind hole forms one deck barrier, and wherein the resistivity of barrier is greater than the resistivity of conduction region; One deck contact layer is formed in the bottom of each blind hole; And after each contact layer of formation, utilize the multiple blind hole of charged radiation exposure.
Description
Technical field
The present invention relates to a kind of detection method, particularly relate to a kind of detection method of semiconductor blind hole.
Background technology
Along with chip and the continuous micro of packaging and the lifting gradually of element integrated level, encapsulation technology encapsulates (BallGridArray, BGA) from the encapsulation of initial stitch plug-in type, ball grid array terminals type and develops into up-to-date three-dimensional packaging technology (3DPackage).Because three-dimension packaging can improve density, reduction package dimension (formfactor) of interconnection line, therefore there is good application prospect.In general, in wafer scale (wafer-level) three-dimensional packaging technology, be utilize the interior access path worn silicon through hole (TSV, Through-Silicon-Via) and be used as chip chamber.Because each silicon through hole is perpendicular to chip, so each chip can the highest interconnection of the shortest and integrated level of realizing route. and chip area can be reduced, alleviate interconnect delay problem and the performance of logical circuit is improved greatly.
For the silicon through hole manufacture craft of front through hole (viafirst), technique generally includes the formation (viaformation) of blind hole, filling (viafilling), wafer joint (waferbonding) etc. the step of blind hole.For example, blind hole can first be formed in chip, and is filled electric conducting material, and then through Silicon Wafer thinning (polishing) technique, makes another section of blind hole be exposed out and become a through hole.This through hole can be connected with another chip in technique afterwards.In order to judge the degree of depth and the yield of blind hole, the checkout equipments such as the voltage contrast mode of light microscope or electron beam tester equipment (electronbeamvoltagecontrastmode) generally can be utilized to judge.But when the depth-to-width ratio of blind hole improves constantly, when making its degree of depth more than 80 microns (μm), light microscope just has no idea clear view to blind via bottom.And all can be electrically connected the silicon materials with conductivity due to the bottom of each blind hole, the voltage contrast mode of electron beam tester equipment therefore also cannot be utilized accurately to differentiate the degree of depth of blind hole and whether blind via bottom has residue to exist.
Summary of the invention
The invention provides a kind of detection method of semiconductor blind hole, to solve the detection defect of prior art.
For solving the problem, the invention provides a kind of detection method of semiconductor blind hole, comprising the semiconductor base providing to comprise conduction region; Form multiple blind hole exposing conduction region; On the sidewall of each blind hole, form one deck barrier, wherein the resistivity of barrier is greater than the resistivity of conduction region; One deck contact layer is formed in the bottom of each blind hole; And after each contact layer of formation, utilize the multiple blind hole of charged radiation exposure.
Accompanying drawing explanation
Fig. 1 is the upper schematic diagram in Semiconductor substrate of the present invention with multiple blind hole.
Fig. 2 is the Semiconductor substrate generalized section of tangent line 2-2 ' in Fig. 1.
Fig. 3 is the upper schematic diagram filling up conductive materials in multiple blind hole.
Fig. 4 is the Semiconductor substrate generalized section of tangent line 3-3 ' in Fig. 3.
Fig. 5 is the generalized section that multiple blind hole includes barrier and contact layer.
Wherein, description of reference numerals is as follows:
1 semiconductor base 10 blind hole
10a first blind hole 10b second blind hole
10c the 3rd blind hole 10d the 4th blind hole
12 insulating barrier 16 conduction regions
30 electric conducting material 31 electron beams
40a junction 40c junction
50 barrier 53 contact layers
Embodiment
Although the present invention is openly as follows with preferred embodiment; but it is not used for limiting the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when doing a little change and retouching; therefore protection scope of the present invention with claims define for standard, in order to not make spirit of the present invention hard to understand, the details of part known features and processing step will not disclose at this.
Similarly, accompanying drawing is represented is device schematic diagram in preferred embodiment, but is not used for the size of device for limiting, and particularly, for making the present invention more clearly present, the size of subelement may be amplified and presented in the drawings.And disclosed identical element will indicate same or analogous symbol in multiple preferred embodiment, to make explanation easier and clear.
Please refer to Fig. 1 and Fig. 2, wherein Fig. 2 is the generalized section of tangent line 2-2 ' in Fig. 1.First, as Fig. 1, in a semiconductor base 1, such as silicon base or silicon-on-insulator (silicon-on-insulator, SOI) substrate form multiple blind hole 10.Wherein, the generation type of described blind hole 10 can utilize laser drill (LaserDrilling), plasma etching or various wet etching (isotropism or anisotropic etching) technology, make each blind hole 10a, 10b, 10c, 10d all have vertical sidewall substantially, but are not limited thereto.And semiconductor base 1 is except being silicon base, also can comprise the semi-conducting material that other has conductivity, such as, comprise II-VI group, iii-v and IV race element.Here it is noted that the present invention can be applied in silicon through hole manufacture craft before through hole (viafirst) or rear through hole (vialast) manufacture craft.For front through hole manufacture craft, semiconductor base 1 can have a layer insulating 12, such as etching stopping layer or protective layer, be used for protecting semiconductor base 1; On the other hand, for rear through hole (vialast) manufacture craft, insulating barrier 12 can be interlayer dielectric layer (interlayerdielectric, ILD) or dielectric layer between metal layers (intermetaldielectric, but be not limited thereto IMD).
The better meeting of the degree of depth due to each blind hole 10a, 10b, 10c, 10d, more than 80 microns (μm), is therefore usually understood in the conduction region 16 of position in semiconductor base 1 bottom it, described conduction region 16 is exposed out.Wherein, described conduction region 16 has the conductivity of N-type or P type, and it can account for the some of semiconductor base 1 or all, better, conduction region 16 accounts for the whole of semiconductor base 1.In this case, because position equal bottom blind hole 10 is in conduction region 16, if so when conduction region 16 has specific potential, such as 0 current potential, the bottom of each blind hole 10a, 10b, 10c, 10d also can have described current potential.
Still as shown in Figure 2.Due to the technical limitations of manufacture craft, blind hole 10 degree of depth can change along with existing region, and that is, the degree of depth bottom each blind hole 10a, 10b, 10c, 10d is not identical.For example, the first blind hole 10a and the second blind hole 10b has same depth; 3rd blind hole 10c occupies secondary; The degree of depth of the 4th blind hole 10d is then be shallower than above-mentioned all blind hole 10a, 10b, 10c.
In order to detect the degree of depth in semiconductor base 1 of each blind hole 10, the mode that the present invention adopts electron beam to scan, electron beam (primarybeam) is utilized to bombard each blind hole 10 and its adjacent domain, and detect secondary electron quantity or the intensity of the generation of each blind hole 10, or detect the current potential of each blind hole 10.In order to the secondary electron quantity allowing each blind hole 10 produce has obvious difference, feature of the present invention is before detecting, and first in each blind hole 10, inserts barrier, such as, and insulating barrier.Hereinafter, two kinds of preferred embodiments can be described respectively: in blind hole, insert barrier and electric conducting material; And only insert barrier in blind hole.
first preferred embodiment
After formation above-mentioned each blind hole 10a, 10b, 10c, 10d, then can form one deck barrier 50 at the sidewall of each blind hole 10, and insert electric conducting material 30 in each blind hole 10.As shown in Figure 3 and Figure 4, wherein Fig. 3 is the upper schematic diagram filling up conductive materials in multiple blind hole to structure after completing; Fig. 4 is the Semiconductor substrate generalized section of tangent line 3-3 ' in Fig. 3.Better, the resistivity of electric conducting material 30 can be less than the resistivity of conduction region 16, wherein, electric conducting material 30 can comprise tungsten (W), aluminium (Al), copper (Cu), titanium (Ti), tantalum (Ta), niobium (Nb), erbium (Er), molybdenum (Mo), cobalt (Co), nickel (Ni), platinum (Pt) or its alloy, but is not limited thereto.And be not ohmic contact between barrier 50 and conduction region 16.If here it should be noted that do not carry out suitable process, now normally Schottky contacts between electric conducting material 30 and conduction region 16.Contrast strength difference during in order to detect after increasing between each blind hole, the feature of this preferred embodiment is after inserting electric conducting material 30, then carries out a technique, such as Technology for Heating Processing, makes the junction between electric conducting material 30 and conduction region 16 with ohmic contact.As shown in Figure 4, after heat-treating technique 21, the junction 40a between electric conducting material 30 and conduction region 16 can have ohmic contact character.
In detection afterwards, when detection board, such as electron beam chip defect detects board, when the electron beam 31 utilizing energy to be less than 2 kilovolts (kV) irradiates and fills up multiple blind hole 10 of electric conducting material 30, because the resistivity of barrier 50 can be greater than the resistivity of conduction region 16, so electronics has no idea to enter electric conducting material 30 from conduction region 16 by insulation junction 40c, and only have contiguous each blind hole 10a, 10b, 10c, conduction region 16 bottom 10d just likely directly contacts with electric conducting material 30, and has ohmic contact character.Therefore, if each blind hole 10a, 10b, 10c, 10d are filled with electric conducting material 30 when detecting, then secondary electron intensity during detection can be improved.
But, under these circumstances, secondary electron intensity usually can be caused too high, the degree of depth of each blind hole 10a, 10b, 10c, 10d is still had no idea fine-resolution.Therefore, the present invention proposes second preferred embodiment in addition, with solving this defect.
second preferred embodiment
Please refer to Fig. 5, Fig. 5 is the generalized section that the sidewall of multiple blind hole comprises barrier.The structure of Fig. 5 and the generation type major part similar structure as Fig. 4 and generation type, that is, have barrier 50 in each blind hole 10a, 10b, 10c, 10d equally.But, the place different with the first preferred embodiment is, each blind hole 10a in Fig. 5,10b, 10c, do not insert electric conducting material 30 (or first insert electric conducting material 30, be removed again after suitable technique) in 10d, and the contact layer 53 with ohmic contact character can be comprised in conduction region 16 bottom contiguous each blind hole 10.For example, the mode forming contact layer 53 can one of comprise the following steps: (1) utilizes epitaxy technique, forms one deck epitaxial loayer in the bottom of each blind hole 10; (2) carry out metal deposition process, form layer of metal layer in the bottom of each blind hole 10; And (3) carry out a deposition and diffusion technology, form layer of metal silicide layer in the bottom of each blind hole 10.In other words, contact layer 53 can comprise epitaxial loayer, metal level or metal silicide layer, but is not limited to this.
Therefore under these circumstances, similar first preferred embodiment, when detection board, such as electron beam chip defect detects board, when the electron beam 31 utilizing energy to be less than 2 kilovolts (kV) irradiates and has multiple blind hole 10 of barrier 50 and contact layer 53, because the first blind hole 10a and the second blind hole 10b is the darkest, so from blind hole 10a, the secondary electron produced bottom 10b is least easily received by the checkout gear above blind mouth 10, so have the most weak secondary electron signal intensity; And the degree of depth of the 3rd blind hole 10c is inferior to the first blind hole 10a and the second blind hole 10b, so the secondary electron signal intensity of the 3rd blind hole 10c can higher than the secondary electron signal intensity of the first blind hole 10a and the second blind hole 10b; 4th blind hole 10d is the most shallow, so the secondary electron produced bottom it is the most easily received by the checkout gear above blind mouth 10, therefore there is the strongest secondary electron signal intensity (can the secondary electron number that produces of each blind hole is slightly different as seen from Figure 5).
More existing technology, because existing detection technique can not form the contact layer 53 with ohmic contact character between electric conducting material 30 and conduction region 16, also can not form one deck barrier 50 at the sidewall of each blind hole 10a, 10b, 10c, 10d.So cause each blind hole 10 can produce the secondary electron of close intensity or quantity, make to detect board and clearly cannot differentiate normal blind hole 10a, 10b and abnormal blind hole 10c, 10d.Contrast down, detection technique of the present invention clearly and easily can tell normal blind hole 10a, 10b and abnormal difference between blind hole 10c, 10d.In addition, detection technique of the present invention perhaps also can be used for distinguishing the residual degree of resistive formation 20 in abnormal blind hole 10c, 10d.
The plan shape of each above-mentioned blind hole 10 is except being circular hole, and in other preferred embodiment, it also can be oval or strip.In addition, above-mentioned detection method adopts passive (passive) voltage contrast mode (semiconductor base 1 ground connection).But according to other preferred embodiment, detection method also can adopt the detection method of active (active) voltage contrast mode, and that is, semiconductor base 1 can be applied in voltage, makes conduction region 16 have positive potential or negative potential.Further, it is that electron beam chip defect detects board that above-mentioned detection board does not limit, and also can be replaced focused ion beam (focusedionbeam, FIB) chip defect and detect board.That is, not necessarily will utilize beam bombardment semiconductor base 1 when detecting, electron beam also can be replaced positive charge bundle, such as gallium ion beam or other ion beam, but is not limited thereto.Therefore without prejudice under spirit of the present invention, the defect in focused ion beam chip defect detection board detection blind hole can also be utilized.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1. a detection method for semiconductor blind hole, is characterized in that, comprising:
The semiconductor base that one comprises conduction region is provided;
Form multiple blind hole exposing described conduction region in described semiconductor base;
In described semiconductor base at least one described multiple blind hole sidewall on form one deck barrier, the resistivity of described barrier is greater than the resistivity of described conduction region;
Form one deck contact layer in the bottom of each blind hole described, the generation type of described contact layer is by carrying out a metal deposition process, thus forms layer of metal layer in the bottom of each blind hole described; And
After formation each contact layer described, utilize multiple blind hole described in charged radiation exposure.
2. the detection method of semiconductor blind hole according to claim 1, it is characterized in that, described barrier is an insulating barrier.
3. the detection method of semiconductor blind hole according to claim 1, it is characterized in that, be not ohmic contact between described barrier and described semiconductor base.
4. the detection method of semiconductor blind hole according to claim 1, it is characterized in that, described contact layer has ohmic contact.
5. the detection method of semiconductor blind hole according to claim 1, is characterized in that, after utilizing described charged radiation exposure to fill up described multiple blind hole, also one of comprise the following steps:
Detect the secondary electron intensity that each blind hole described produces; And
Detect the current potential of each blind hole described.
6. the detection method of semiconductor blind hole according to claim 1, it is characterized in that, each blind hole described has different depth.
7. the detection method of semiconductor blind hole according to claim 1, it is characterized in that, the degree of depth of described multiple blind hole is all greater than 80 microns.
8. the detection method of semiconductor blind hole according to claim 1, it is characterized in that, described charged ray comprises electron beam or ion beam.
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| CN201210174235.3A CN103456655B (en) | 2012-05-30 | 2012-05-30 | The detection method of semiconductor blind hole |
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| CN109935527B (en) * | 2017-12-15 | 2022-11-04 | 长鑫存储技术有限公司 | Contact hole detection method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1355558A (en) * | 2000-11-23 | 2002-06-26 | 三星电子株式会社 | Device for testing defect in semiconductor device and method for using said device |
| US6525318B1 (en) * | 1999-04-23 | 2003-02-25 | Samsung Electronics Co., Ltd. | Methods of inspecting integrated circuit substrates using electron beams |
| TW556301B (en) * | 2001-12-19 | 2003-10-01 | Mitsubishi Electric Corp | Method of manufacturing semiconductor device for evaluation capable of evaluating crystal defect using in-line test by avoiding using preferential etching process |
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| KR20070105201A (en) * | 2006-04-25 | 2007-10-30 | 주식회사 하이닉스반도체 | Method for detecting bottom defects of semiconductor substrate |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6525318B1 (en) * | 1999-04-23 | 2003-02-25 | Samsung Electronics Co., Ltd. | Methods of inspecting integrated circuit substrates using electron beams |
| CN1355558A (en) * | 2000-11-23 | 2002-06-26 | 三星电子株式会社 | Device for testing defect in semiconductor device and method for using said device |
| TW556301B (en) * | 2001-12-19 | 2003-10-01 | Mitsubishi Electric Corp | Method of manufacturing semiconductor device for evaluation capable of evaluating crystal defect using in-line test by avoiding using preferential etching process |
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