CN103456632B - Metal-oxide-semiconductor and forming method thereof - Google Patents
Metal-oxide-semiconductor and forming method thereof Download PDFInfo
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Abstract
A kind of metal-oxide-semiconductor and forming method thereof, wherein the formation method of metal-oxide-semiconductor comprises: provide Semiconductor substrate, described semiconductor substrate surface is coated with voltage control layer, described voltage control layer surface coverage has the first extension intrinsic layer, described first extension intrinsic layer surface coverage has insulating barrier, has the first grid structure running through its thickness in described insulating barrier; With described first grid structure for mask, in described first extension intrinsic layer, doping forms source/drain region; Remove described first grid structure, form the opening exposing described first extension intrinsic layer surface; Form the second extension intrinsic layer covering described open bottom; The second grid structure covering described second extension intrinsic layer is formed in described opening.The threshold voltage of the metal-oxide-semiconductor formed is low, stable performance.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of metal-oxide-semiconductor and forming method thereof.
Background technology
The formation method of the metal-oxide-semiconductor of prior art, comprising:
Please refer to Fig. 1, provide Semiconductor substrate 100, described Semiconductor substrate 100 surface coverage has insulation film 101, and described insulation film 101 surface coverage has polysilicon membrane 103, and described polysilicon membrane 103 surface has photoresist layer 105;
Please refer to Fig. 2, with described photoresist layer 105 for polysilicon membrane described in mask etching and insulation film, until expose Semiconductor substrate 100, form polysilicon layer 103a and insulating barrier 101a, described polysilicon layer 103a and be positioned at described insulating barrier 101a surface;
Please refer to Fig. 3, after insulating barrier 101a to be formed and polysilicon layer 103a, with described photoresist layer 105 be mask to Doped ions in described Semiconductor substrate 100, formed source/drain region 107.
Along with the development of semiconductor process techniques, the reduction gradually of process node, the continuous reduction of gate CDs (CD), rear grid technique is widely used, and adopt high-K gate dielectric material to replace generic media as gate dielectric layer, metal material is adopted to replace polysilicon as gate electrode layer, to improve the performance of MOS device.
But the threshold voltage of the metal-oxide-semiconductor that prior art is formed is higher, and the performance of metal-oxide-semiconductor still has much room for improvement.Specifically please refer to the United States Patent (USP) that publication number is " US20100084719A1 ".
Summary of the invention
The problem that the present invention solves is to provide a kind of superior performance, metal-oxide-semiconductor that threshold voltage is low and forming method thereof.
For solving the problem, embodiments of the invention form the formation method of metal-oxide-semiconductor, comprising:
Semiconductor substrate is provided, described semiconductor substrate surface is coated with voltage control layer, described voltage control layer surface coverage has the first extension intrinsic layer, described first extension intrinsic layer surface coverage has insulating barrier, there is in described insulating barrier the first grid structure running through its thickness, wherein, the ion of described first extension intrinsic layer and the interior doping of voltage control layer has concentration gradient, and the ion concentration of described first extension intrinsic layer is less than the ion concentration of described voltage control layer;
With described first grid structure for mask, in described first extension intrinsic layer, doping forms source/drain region;
Remove described first grid structure, form the opening exposing described first extension intrinsic layer surface;
Form the second extension intrinsic layer covering described open bottom;
The second grid structure covering described second extension intrinsic layer is formed in described opening.
Alternatively, have Doped ions in described voltage control layer, the concentration of described Doped ions is greater than 5E17atoms/cm
3, be less than 5E18atoms/cm
3.
Alternatively, when forming NMOS tube, the Doped ions in described voltage control layer is p-type ion, and also doped with carbon ion in described voltage control layer, and the volume ratio that the carbon ion of doping accounts for total Doped ions of voltage control layer is less than 1%; When forming PMOS, the Doped ions in described voltage control layer is N-shaped ion, and also doped with germanium ion in described voltage control layer, and the volume ratio that the germanium ion of doping accounts for total Doped ions of voltage control layer is less than 3%.
Alternatively, the volume ratio that the carbon ion of described doping accounts for total Doped ions of voltage control layer is less than 0.1%.
Alternatively, not there is Doped ions in described first extension intrinsic layer; Or the ion concentration of doping in described first extension intrinsic layer is less than 1E16atoms/cm
3.
Alternatively, not there is Doped ions in described second extension intrinsic layer; Or the ion concentration of doping in described second extension intrinsic layer is less than 1E16atoms/cm
3.
Alternatively, the thickness of described second epitaxial loayer is 3nm-10nm.
Alternatively, the formation process of described second extension intrinsic layer is selective epitaxial depositing operation.
Alternatively, also comprise: before forming the second extension intrinsic layer, annealing in process is carried out to the first extension intrinsic layer surface of described open bottom.
Alternatively, the gas that described annealing in process adopts is hydrogen or argon gas.
Alternatively, the forming step of described first grid structure comprises: formed and run through described insulating barrier and the pseudo-gate electrode layer being positioned at described first extension intrinsic layer surface; Form the pseudo-side wall being positioned at described pseudo-gate electrode layer both sides.
Alternatively, also comprise: after the pseudo-gate electrode layer of formation, before forming pseudo-side wall, with described pseudo-gate electrode layer for mask, light dope in described first extension intrinsic layer, forms light doping section; After the pseudo-side wall of formation, formed before insulating barrier, with described pseudo-side wall and pseudo-gate electrode layer for mask, heavy doping in described first extension intrinsic layer, forms source/drain region.
Alternatively, the forming step of described second grid structure comprises: form the side wall being positioned at described opening both sides; Form the high-K gate dielectric layer covering described second extension intrinsic layer and side wall; Formed and cover described high-K gate dielectric layer and the metal gate electrode layer flushed with described surface of insulating layer.
Alternatively, also comprise: before formation first grid structure, form the etching barrier layer covering described first extension intrinsic layer surface.
Corresponding volume, additionally provides a kind of metal-oxide-semiconductor, comprising:
Semiconductor substrate;
Cover the voltage control layer of described semiconductor substrate surface;
Cover the first extension intrinsic layer on described voltage control layer surface, the ion of described first extension intrinsic layer and the interior doping of voltage control layer has concentration gradient, and the ion concentration of described first extension intrinsic layer is less than the ion concentration of described voltage control layer;
Cover the insulating barrier on described first extension intrinsic layer surface;
Run through the opening of described thickness of insulating layer;
Be positioned at the second extension intrinsic layer of described open bottom, described second extension intrinsic layer is positioned at described first extension intrinsic layer surface, and do not have Doped ions in described second extension intrinsic layer, or the ion concentration of its doping is less than the ion concentration of doping in described first extension intrinsic layer;
Be positioned at the grid structure on the described second extension intrinsic layer surface of described opening, described grid structure flushes with described surface of insulating layer.
Alternatively, in described second extension intrinsic layer, not there is Doped ions, or the ion concentration of doping in described second extension intrinsic layer is less than 1E16atoms/cm
3.
Alternatively, the thickness of described second extension intrinsic layer is 3nm-10nm.
Alternatively, in described voltage control layer, the concentration of Doped ions is greater than 5E17atoms/cm
3, be less than 5E18atoms/cm
3.
Alternatively, when for NMOS tube, the Doped ions in described voltage control layer is p-type ion, and also doped with carbon ion in described voltage control layer, and the volume ratio that the carbon ion of doping accounts for total Doped ions of voltage control layer is less than 1%; When for PMOS, the Doped ions in described voltage control layer is N-shaped ion, and also doped with germanium ion in described voltage control layer, and the volume ratio that the germanium ion of doping accounts for total Doped ions of voltage control layer is less than 3%.
Alternatively, the volume ratio that the carbon ion of described doping accounts for total Doped ions of voltage control layer is less than 0.1%.
Alternatively, described grid structure comprises the side wall being positioned at described opening sidewalls; Cover the high-K gate dielectric layer of described second extension intrinsic layer and sidewall; Cover described high-K gate dielectric layer and the metal gate electrode layer flushed with described surface of insulating layer.
Alternatively, also comprise: the light doping section being positioned at the first extension intrinsic layer of described metal gate electrode layer both sides; Be positioned at the source/drain region of the first extension intrinsic layer of described metal gate electrode layer and side wall both sides.
Alternatively, described semiconductor substrate surface place has Doped ions, and the concentration of described Doped ions is greater than 1E18atoms/cm
3, be less than 1E19atoms/cm
3.
Alternatively, when for NMOS tube, the Doped ions in described Semiconductor substrate is p-type, also comprises carbon ion in described Semiconductor substrate, and the volume ratio that described carbon ion accounts for total Doped ions in Semiconductor substrate is less than 1%; When for PMOS, the Doped ions in described Semiconductor substrate is N-shaped, also comprises germanium ion in described Semiconductor substrate, and the volume ratio that described germanium ion accounts for total Doped ions in Semiconductor substrate is less than 1%.
Alternatively, the volume ratio that the carbon ion adulterated in described Semiconductor substrate accounts for total Doped ions in Semiconductor substrate is less than 0.4%.
Compared with prior art, embodiments of the invention have the following advantages:
The technique forming metal-oxide-semiconductor is simple, with first grid structure for mask, form source/drain region in the first extension intrinsic layer after, remove described first grid structure and form the opening exposing described first extension intrinsic layer surface, and form the second extension intrinsic layer in described open bottom, then form the second grid structure covering described second extension intrinsic layer.The the second extension intrinsic layer formed is more near second grid structure, due to the existence of the second extension intrinsic layer, even if the ion concentration behind formation source/drain region in the first extension intrinsic layer increases, also negative effect can not be caused to the threshold voltage of the metal-oxide-semiconductor formed, the threshold voltage of the metal-oxide-semiconductor that the embodiment of the present invention is formed is low, the stable performance of the metal-oxide-semiconductor of formation.
Further, also comprise: form light doping section, described light doping section effectively can stop that heavily doped source/drain region intermediate ion is through high-K gate dielectric layer, impacts metal gate electrode layer, namely effectively suppress hot carrier's effect, the performance of the metal-oxide-semiconductor of formation is more stable.
Metal-oxide-semiconductor has the second extension intrinsic layer of close grid structure (second grid structure), does not possess Doped ions or Doped ions concentration lower than 1E16atoms/cm in described second extension intrinsic layer
3, metal-oxide-semiconductor can obtain lower threshold voltage.
Accompanying drawing explanation
Fig. 1-Fig. 3 is the cross-sectional view of the forming process of the metal-oxide-semiconductor of prior art;
Fig. 4 is the schematic flow sheet of the embodiment of the formation method of metal-oxide-semiconductor of the present invention;
Fig. 5-Figure 15 is the cross-sectional view of the embodiment of the forming process of metal-oxide-semiconductor of the present invention;
Figure 16 is the distribution schematic diagram of ion concentration in any point in the embodiment of the present invention the second extension intrinsic layer of metal-oxide-semiconductor, the first extension intrinsic layer, voltage control layer and the Semiconductor substrate that are formed.
Embodiment
As described in background, the threshold voltage of the metal-oxide-semiconductor of prior art is higher, and the performance of metal-oxide-semiconductor still has much room for improvement.
Through research, inventor finds, can at semiconductor substrate surface coating-forming voltage key-course and the extension intrinsic layer covering described voltage control layer, the ion concentration of described voltage control layer is greater than the ion concentration of described extension intrinsic layer, and both are when having concentration gradient, the metal-oxide-semiconductor of formation can obtain lower threshold voltage.
After further research, inventor finds, during owing to forming metal-oxide-semiconductor, doping in described extension intrinsic layer is needed to form source/drain region, even annealing in process is carried out to activate the ion of source/drain region to described source/drain region, the ion of described source/drain region can spread further in described extension intrinsic layer, and the extension intrinsic layer ion concentration being positioned at described grid structure base plate is increased.When the extension intrinsic layer ion concentration being positioned at described grid structure base plate increases, the threshold voltage of the metal-oxide-semiconductor formed can be affected and increase to some extent, for reducing the threshold voltage of the metal-oxide-semiconductor formed and improving the stability of metal-oxide-semiconductor performance, The embodiment provides a kind of metal-oxide-semiconductor and forming method thereof.
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Please refer to Fig. 4, the formation method of the metal-oxide-semiconductor of the embodiment of the present invention, comprising:
Step S201, Semiconductor substrate is provided, described semiconductor substrate surface is coated with voltage control layer, described voltage control layer surface coverage has the first extension intrinsic layer, described first extension intrinsic layer surface coverage has insulating barrier, has the first grid structure running through its thickness, wherein in described insulating barrier, the ion of described first extension intrinsic layer and the interior doping of voltage control layer has concentration gradient, and the ion concentration of described first extension intrinsic layer is less than the ion concentration of described voltage control layer;
Step S203, with described first grid structure for mask, in described first extension intrinsic layer, doping forms source/drain region;
Step S205, removes described first grid structure, forms the opening exposing described first extension intrinsic layer surface;
Step S207, forms the second extension intrinsic layer covering described open bottom;
Step S209, forms the second grid structure covering described second extension intrinsic layer in described opening.
Concrete, please refer to Fig. 5-Figure 16, Fig. 5-Figure 15 shows the cross-sectional view of the forming process of the metal-oxide-semiconductor of the embodiment of the present invention, and Figure 16 shows the distribution schematic diagram of ion concentration in any point in the second extension intrinsic layer of metal-oxide-semiconductor, the first extension intrinsic layer, voltage control layer and Semiconductor substrate that the embodiment of the present invention formed.
Please refer to Fig. 5, Semiconductor substrate 300 is provided.
Described Semiconductor substrate 300 is for providing workbench for subsequent technique.Described Semiconductor substrate 300 is silicon substrate (Si) or silicon-on-insulator (SOI).In an embodiment of the present invention, described Semiconductor substrate 300 is silicon substrate, and its material is monocrystalline silicon, and its indices of crystallographic plane are (100).
It should be noted that, the interior anti-break-through layer (not shown) that can also have well region (not shown), sub-channel (sub-channel) (not shown) or prevent break-through in metal-oxide-semiconductor (punch-through) of described Semiconductor substrate 300, for making the ion distribution in described well region even, annealing process can also be carried out to described Semiconductor substrate 300, because annealing process is well known to those skilled in the art, do not repeat them here.
In an embodiment of the present invention, also comprise: adopt spike doping (spikechannel) technique, adulterate in described Semiconductor substrate 300, make the ion concentration near Semiconductor substrate 300 surface be greater than 1E18atoms/cm
3, be less than 1E19atoms/cm
3.Owing to forming NMOS tube in the embodiment of the present invention, Doped ions in described Semiconductor substrate 300 is p-type, for the follow-up carrier mobility improving the NMOS channel region formed, also doped with carbon ion in described Semiconductor substrate 300, and the volume ratio that the carbon ion of its doping accounts for total Doped ions in Semiconductor substrate is less than 1%, is especially less than 0.4%.
It should be noted that, in other embodiments of the invention, when forming PMOS, Doped ions in described Semiconductor substrate is N-shaped, for the follow-up carrier mobility improving the PMOS channel region formed, also doped with germanium ion in described Semiconductor substrate 300, and the volume ratio that the germanium ion of its doping accounts for total Doped ions in Semiconductor substrate is less than 1%.
Please refer to Fig. 6, form the voltage control layer 301 covering described Semiconductor substrate 300 and the first extension intrinsic layer 303 covering described voltage control layer 301, the ion of described first extension intrinsic layer 303 and the interior doping of voltage control layer 301 has concentration gradient, and the ion concentration of described first extension intrinsic layer 303 is less than the ion concentration of described voltage control layer 301.
In described voltage control layer (epitaxialVtcontrollayer) 301, there is Doped ions, the follow-up threshold voltage for controlling metal-oxide-semiconductor.Through research, inventor finds, when in voltage control layer 301, the concentration of Doped ions is greater than 5E17atoms/cm
3, be less than 5E18atoms/cm
3time, the threshold voltage of the metal-oxide-semiconductor of formation is minimum.In embodiments of the invention, when forming NMOS tube, the Doped ions in described voltage control layer 301 is p-type ion.
For increasing the stress of NMOS tube channel region; improve the carrier mobility of NMOS tube channel region; usually also can in voltage control layer 301 doping carbon ion; when the volume ratio that the carbon ion adulterated accounts for total Doped ions of voltage control layer 301 is less than 1%, the carrier mobility of NMOS tube channel region is higher.In an embodiment of the present invention, the volume ratio that the carbon ion adulterated in described voltage control layer 301 accounts for total Doped ions of voltage control layer 301 is less than 0.1%, and the carrier mobility of the NMOS tube channel region of formation is high, and the threshold voltage of NMOS tube is low.
It should be noted that, in other embodiments of the invention, when forming PMOS, Doped ions in described voltage control layer 301 is N-shaped ion, and also have requirement for the ratio improving the germanium ion that the channel region stress of PMOS and carrier mobility are adulterated, when the volume ratio that the germanium ion adulterated accounts for total Doped ions of voltage control layer 301 is less than 3%, the channel region stress of PMOS and carrier mobility is high and the threshold voltage of PMOS is low.
The material of described voltage control layer 301 is monocrystalline silicon or other semi-conducting materials, and the formation method of described voltage control layer 301 is epitaxial growth technology or ion doping technique.In an embodiment of the present invention, the formation process of described voltage control layer 301 is: epitaxial growth technology, and its concrete steps comprise: adopt the silicon source gas comprising p-type ion and carbon ion, at described Semiconductor substrate 300 surperficial extension coating-forming voltage key-course 301.
It should be noted that, in other embodiments of the invention, also can directly to doped p type in described Semiconductor substrate 300 or N-shaped ion coating-forming voltage key-course 301.
Described first extension intrinsic layer 303 is for together adjusting the threshold voltage of metal-oxide-semiconductor with voltage control layer 301 and barrier layer.Find through research, when the ion concentration of doping in described first extension intrinsic layer 303 is less than 1E16atoms/cm
3time, metal-oxide-semiconductor more easily obtains lower threshold voltage, and especially when not having Doped ions in described first extension intrinsic layer 303, the final metal-oxide-semiconductor formed can obtain minimum threshold voltage.In an embodiment of the present invention, owing to forming NMOS tube, in described first extension intrinsic layer 303, the ion of doping is p-type.
It should be noted that, in other embodiments of the invention, when formation PMOS, in described first extension intrinsic layer 303, the ion of doping is N-shaped.
Please refer to Fig. 7, form the etching barrier layer 305 covering described first extension intrinsic layer 303, form the pseudo-gate electrode layer 307 being positioned at described etching barrier layer 305 surface.
During described etching barrier layer 305 side wall pseudo-in follow-up removal, protection extension intrinsic layer 303 is not damaged.The formation process of described etching barrier layer 305 is depositing operation, such as physics or chemical vapor deposition method.The material of described etching barrier layer 305 is compared with pseudo-side wall, the material that etching selection ratio is little, such as silica, silicon nitride, silicon oxynitride etc.In an embodiment of the present invention, the material of described etching barrier layer 305 is silicon oxynitride.
Described pseudo-gate electrode layer 307 as mask, forms light doping section and source/drain region for follow-up.The material of described pseudo-gate electrode layer 307 is polysilicon, and rear extended meeting is removed.The forming step of described pseudo-gate electrode layer 307 comprises: form the pseudo-gate electrode film (not shown) covering described etching barrier layer 305 surface; Form the photoresist layer (not shown) covering described pseudo-gate electrode film surface; With described photoresist layer for mask, etch described pseudo-gate electrode film and form pseudo-gate electrode layer 307.Because the formation process of described pseudo-gate electrode layer 307 is well known to those skilled in the art, do not repeat them here.
Please refer to Fig. 8, with described pseudo-gate electrode layer 307 for mask, light dope in described first extension intrinsic layer 303, forms light doping section 308.
Described light doping section 308 is follow-up for stopping that heavily doped source/drain region intermediate ion is through high-K gate dielectric layer, impacts metal gate electrode layer, namely produces hot carrier's effect.The formation process of described light doping section 308 is ion doping technique, during doping, when ion implantation the first epitaxial semiconductor layer 303 and described first epitaxial semiconductor layer 303 surface in 30-60 ° of angle (implantangle), the light doping section 308 of formation is ideal.Because the technique forming light doping section 308 is well known to those skilled in the art, do not repeat them here.
Please refer to Fig. 9, after forming light doping section 308, form the pseudo-side wall 309 being positioned at described pseudo-gate electrode layer 307 both sides.
Described pseudo-side wall 309 is for mask as follow-up formation source/drain region common with described pseudo-gate electrode layer 307.The material of described pseudo-side wall 309 is silicon nitride.The formation process of described pseudo-side wall 309 is depositing operation, and its concrete forming step comprises: the pseudo-side wall film forming roof, sidewall and the etching barrier layer 305 covering described pseudo-gate electrode layer 307; Etch described pseudo-side wall film, expose top and etching barrier layer 305 surface of pseudo-gate electrode layer 307, form pseudo-side wall 309.Because the technique forming pseudo-side wall 309 is well known to those skilled in the art, do not repeat them here.
Please refer to Figure 10, with described pseudo-gate electrode layer 307 and pseudo-side wall 309 for mask, heavy doping in described first extension intrinsic layer 303, forms source/drain region 311.
The formation process of described source/drain region 311 is doping process, and the technique forming source/drain region 311 due to doping is well known to those skilled in the art, does not repeat them here.
It should be noted that, after in described first extension intrinsic layer 303, doping forms source/drain region 311, also comprise: annealed in described source/drain region 311, activate the ion in described source/drain region 311, and repair first extension intrinsic layer 303 surface impaired when forming source/drain region 311.
Please refer to Figure 11, after forming source/drain region 311, form the insulating barrier 313 covering described pseudo-gate electrode layer 307, pseudo-side wall 309 and etching barrier layer 305, described insulating barrier 313 surface flushes with described pseudo-gate electrode layer 307 top.
Described insulating barrier 313 is for the second grid structure of follow-up isolation adjacent mos pipe.The material oxidation silicon of described insulating barrier 313, silicon oxynitride or silicon nitride etc., and the removal of conveniently pseudo-side wall 309, the material of described insulating barrier 313 is different from the material of described pseudo-side wall 309, and both have larger etching selection ratio.In an embodiment of the present invention, the material of described insulating barrier 313 is silica.
The formation process of described insulating barrier 313 is depositing operation, such as physics or chemical vapor deposition method.The forming step of described insulating barrier 313 comprises: form the insulation film (not shown) covering described pseudo-gate electrode layer 307, pseudo-side wall 309 and etching barrier layer 305; Chemico-mechanical polishing or time described insulation film of etching, form the insulating barrier 313 flushed with described pseudo-gate electrode layer 307 and pseudo-side wall 309 surface.
Please refer to Figure 12, after forming insulating barrier 313, remove described pseudo-gate electrode layer and pseudo-side wall, form the opening 315 exposing described first extension intrinsic layer 303 surface.
Described opening 315 is for the follow-up window as forming the second extension intrinsic layer.The formation process of described opening 315 is etching technics, such as dry etch process.Because the technique adopting dry etch process to form opening 315 is well known to those skilled in the art, do not repeat them here.
It should be noted that, by the protection of described etching barrier layer 305, described first extension intrinsic layer 303 surface when etching described opening 315, can not be destroyed.
Please refer to Figure 13, form the second extension intrinsic layer 317 covered bottom described opening 315.
Inventor finds, because in described first extension intrinsic layer 303, doping forms light doping section 308 and source/drain region 311, and behind formation source/drain region 311, also carried out annealing in process, described light dope goes 308, ion in source/drain region 311 diffuses to the part first extension intrinsic layer 303 be positioned at bottom described opening 315 further, causes ion concentration in the first extension intrinsic layer 303 to increase.If the first extension intrinsic layer 303 surface increased in described ion concentration forms second grid structure, then the threshold voltage of the metal-oxide-semiconductor formed is higher, the unstable properties of metal-oxide-semiconductor.
After further research, inventor finds, can in formation light doping section 308, behind source/drain region 311, more described first extension intrinsic layer 303 surface bottom described opening 315 forms the second extension intrinsic layer 317.Not there is Doped ions in described second extension intrinsic layer 317, or there is Doped ions, but in described second extension intrinsic layer 317, the ion concentration of doping is less than 1E16atoms/cm
3, described second extension intrinsic layer 317, closer to second grid structure, is beneficial to the metal-oxide-semiconductor that follow-up formation threshold voltage is low.
The formation process of described second extension intrinsic layer 317 is depositing operation, such as physics or chemical vapor deposition method.In an embodiment of the present invention, the formation process of described second extension intrinsic layer 317 is selective epitaxial depositing operation, and the thickness of the described second extension intrinsic layer 317 of formation is 3nm-10nm, is beneficial to the metal-oxide-semiconductor forming high integration.
It should be noted that, when removing described pseudo-gate electrode layer and pseudo-side wall owing to adopting etching technics, the first extension intrinsic layer 303 surface bottom described opening 315 may exist uneven, therefore, the stability of the metal-oxide-semiconductor formed for making embodiments of the invention is better, also comprise: before forming the second extension intrinsic layer 317, carry out annealing in process to the first extension intrinsic layer 303 surface bottom described opening 315, the gas that described annealing in process adopts is hydrogen or argon gas.
Please refer to Figure 14, form the side wall 319 being positioned at described opening 315 both sides.
Described side wall 319 is not damaged for protecting metal gate electrode layer and high-K gate dielectric layer in subsequent technique.The formation process of described side wall 319 is depositing operation, such as chemical vapor deposition method.The forming step of described side wall 319 comprises: formed cover bottom described opening 315, the side wall film (not shown) on sidewall and insulating barrier 313 surface; Return etching described side wall film until expose bottom described opening 315 first extension intrinsic layer 303 surface and insulating barrier 313 surface, formation side wall 319.
The material of described side wall 319 is silica, silicon nitride or silicon oxynitride.In an embodiment of the present invention, the material of described side wall 319 is identical with the material of described pseudo-side wall, is silicon nitride.
Please refer to Figure 15, form the high-K gate dielectric layer 321 covering described second extension intrinsic layer 317 and side wall 319; Formed and cover described high-K gate dielectric layer 321 and the metal gate electrode layer 323 flushed with described insulating barrier 313 surface.
Described side wall 319, high-K gate dielectric layer 321 and metal gate electrode layer 323 form second grid structure jointly.The concrete forming step of described high-K gate dielectric layer 321 and metal gate electrode layer 323 comprises: form the high-K gate dielectric film (not shown) covering described second extension intrinsic layer 217, side wall 319 and insulating barrier 313 surface; Form the metal electrode film (not shown) covering described high-K gate dielectric film; Metal electrode film described in chemico-mechanical polishing and high-K gate dielectric film, form the high-K gate dielectric layer 323 and metal electrode layer 325 that flush with described insulating barrier 313 surface.
After above-mentioned steps completes, completing of the MOS device of the embodiment of the present invention.
Incorporated by reference to the ion concentration distribution schematic diagram being any point in the second extension intrinsic layer 317, first extension intrinsic layer 303, voltage control layer 301 and Semiconductor substrate 300 in the metal-oxide-semiconductor shown in Figure 15 with reference to Figure 15 and Figure 16, Figure 16.Wherein, X-axis is that in the second extension intrinsic layer 317, first extension intrinsic layer 303 of metal-oxide-semiconductor, voltage control layer 301 and Semiconductor substrate 300, any point is to the distance on extension intrinsic layer 303 surface, and Y-axis is the ion concentration of any point in the second extension intrinsic layer 317, first extension intrinsic layer 303 of described metal-oxide-semiconductor, voltage control layer 301 and Semiconductor substrate 300.
In described first extension intrinsic layer 303, the concentration of ion is as shown in first area I in Figure 16; In described voltage control layer 301, the concentration of ion is as shown in second area II in Figure 16, is greater than 5E17atoms/cm
3, be less than 5E18atoms/cm
3; In described Semiconductor substrate 300, the concentration of ion is as shown in the 3rd region III in Figure 16, and the concentration near Semiconductor substrate 300 surface is the highest, and in described second extension intrinsic layer 317, the concentration of ion is as shown in the 4th region IV in Figure 16, is less than 1E16atoms/cm
3.The ion concentration of the voltage control layer 301 of the metal-oxide-semiconductor formed is greater than the ion concentration of described extension intrinsic layer 303, is conducive to obtaining lower threshold voltage.
Accordingly, please continue to refer to Figure 15, embodiments of the invention additionally provide a kind of metal-oxide-semiconductor adopting said method to be formed, and comprising:
Semiconductor substrate 300;
Cover the voltage control layer 301 on described Semiconductor substrate 300 surface;
Cover the first extension intrinsic layer 303 on described voltage control layer 301 surface, the ion of described first extension intrinsic layer 303 and the interior doping of voltage control layer 301 has concentration gradient, and the ion concentration of described first extension intrinsic layer 303 is less than the ion concentration of described voltage control layer 301;
Cover the insulating barrier 313 on described first extension intrinsic layer 303 surface;
Run through the opening (sign) of described insulating barrier 313 thickness;
Be positioned at the second extension intrinsic layer 317 of described open bottom, described second extension intrinsic layer 317 is positioned at described first extension intrinsic layer 303 surface, and not there is Doped ions in described second extension intrinsic layer 317, or the ion concentration of its doping is less than the ion concentration of doping in described first extension intrinsic layer 303;
Be positioned at the grid structure (second grid structure) on described second extension intrinsic layer 317 surface of described opening, described grid structure flushes with described insulating barrier 313 surface.
Wherein, described Semiconductor substrate 300 is silicon substrate (Si) or silicon-on-insulator (SOI).In embodiments of the invention, described Semiconductor substrate 300 is silicon substrate, and its material is monocrystalline silicon, and its indices of crystallographic plane are (100).The ion concentration of described Semiconductor substrate 300 surface is greater than 1E18atoms/cm
3, be less than 1E19atoms/cm
3.Owing to forming NMOS tube in the embodiment of the present invention, Doped ions in described Semiconductor substrate 300 is p-type, for improving the carrier mobility of the NMOS tube channel region of follow-up formation, also carbon ion is comprised in described Semiconductor substrate 300, and the volume ratio that the carbon ion of its doping accounts for total Doped ions in Semiconductor substrate 300 is less than 1%, is especially less than 0.4%.
It should be noted that, in other embodiments of the invention, when forming PMOS, Doped ions in described Semiconductor substrate 300 is N-shaped, for improving the carrier mobility of the PMOS channel region of follow-up formation, also comprise germanium ion in described Semiconductor substrate 300, and the volume ratio that the germanium ion of its doping accounts for total Doped ions in Semiconductor substrate 300 is less than 1%.
Have Doped ions in described voltage control layer 301, the concentration of described Doped ions is greater than 5E17atoms/cm
3, be less than 5E18atoms/cm
3, to obtain the threshold voltage of little metal-oxide-semiconductor.In an embodiment of the present invention, described metal-oxide-semiconductor is NMOS tube, and the Doped ions in described voltage control layer 301 is p-type ion.For increasing the stress of NMOS tube channel region, improve the carrier mobility of NMOS tube channel region, doping carbon ion is gone back in described voltage control layer 301, the volume ratio that the carbon ion of described doping accounts for total Doped ions of voltage control layer 301 is less than 1%, especially when the volume ratio that the carbon ion adulterated in voltage control layer 301 accounts for total Doped ions of voltage control layer 301 is less than 0.1%, the carrier mobility of the NMOS tube channel region formed is high, and the threshold voltage of NMOS tube is low.
It should be noted that, in other embodiments of the invention, when described metal-oxide-semiconductor is PMOS, the Doped ions in described voltage control layer 301 is N-shaped ion, doped germanium ion is gone back, to improve channel region stress and the carrier mobility of PMOS in described voltage control layer 301.Usually, when the volume ratio that the germanium ion adulterated accounts for total Doped ions of voltage control layer 301 is less than 3%, the channel region stress of PMOS and carrier mobility is high and the threshold voltage of PMOS is low.
Described first extension intrinsic layer 303 is for together adjusting the threshold voltage of metal-oxide-semiconductor with voltage control layer 301 and the second extension intrinsic layer 317.The ion concentration of described first epitaxial loayer 303 is less than ion concentration in described voltage control layer 301.In an embodiment of the present invention, owing to being NMOS tube, in described extension intrinsic layer 303, the ion of doping is p-type.
It should be noted that, in other embodiments of the invention, when being PMOS, in described extension intrinsic layer 303, the ion of doping is N-shaped.
Described insulating barrier 313 is for isolating the grid structure of adjacent mos pipe.The material oxidation silicon of described insulating barrier 313, silicon oxynitride or silicon nitride.In an embodiment of the present invention, the material of described insulating barrier 313 is silica.
Not there is Doped ions in second extension intrinsic layer 317, or the ion concentration of doping in the second extension intrinsic layer 317 is less than the ion concentration of doping in described first extension intrinsic layer 303, for reducing the threshold voltage of metal-oxide-semiconductor further.Not there is Doped ions in described second epitaxial loayer 317, or there is Doped ions, but in described second extension intrinsic layer 317, the ion concentration of doping is less than 1E16atoms/cm
3.The thickness of described second extension intrinsic layer 317 is 3nm-10nm.
Described grid structure (i.e. second grid structure) comprising: the side wall 319 being positioned at described opening both sides; Cover the high-K gate dielectric layer 321 of described second extension intrinsic layer 317 and side wall 319; Cover described high-K gate dielectric layer 321 and the metal gate electrode layer 323 flushed with described insulating barrier 313 surface.
It should be noted that, the MOS of the embodiment of the present invention also comprises: the light doping section 308 being positioned at the first extension intrinsic layer 303 of described metal gate electrode 323 both sides; Be positioned at the source/drain region 311 of the first extension intrinsic layer 303 of described metal gate electrode layer 323 and side wall 319 both sides.Wherein, described light doping section 308 is for suppressing hot carrier's effect, and described source/drain region 311 is for the source/drain of follow-up formation metal-oxide-semiconductor.
The metal-oxide-semiconductor of the embodiment of the present invention, has the first extension intrinsic layer and the second extension intrinsic layer, and the concentration not possessing Doped ions or Doped ions in the second extension intrinsic layer of second grid structure is less than 1E16atoms/cm
3, metal-oxide-semiconductor can obtain lower threshold voltage.
In sum, the technique forming metal-oxide-semiconductor is simple, with first grid structure for mask, form source/drain region in the first extension intrinsic layer after, remove described first grid structure and form the opening exposing described first extension intrinsic layer surface, and form the second extension intrinsic layer in described open bottom, then form the second grid structure covering described second extension intrinsic layer.The the second extension intrinsic layer formed is more near second grid structure, due to the existence of the second extension intrinsic layer, even if the ion concentration behind formation source/drain region in the first extension intrinsic layer increases, also negative effect can not be caused to the threshold voltage of the metal-oxide-semiconductor formed, the threshold voltage of the metal-oxide-semiconductor that the embodiment of the present invention is formed is low, the stable performance of the metal-oxide-semiconductor of formation.
Further, also comprise: form light doping section, described light doping section effectively can stop that heavily doped source/drain region intermediate ion is through high-K gate dielectric layer, impacts metal gate electrode layer, namely effectively suppress hot carrier's effect, the performance of the metal-oxide-semiconductor of formation is more stable.
Metal-oxide-semiconductor has the second extension intrinsic layer of close grid structure (second grid structure), does not possess Doped ions or Doped ions concentration lower than 1E16atoms/cm in described second extension intrinsic layer
3, metal-oxide-semiconductor can obtain lower threshold voltage.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (14)
1. a formation method for metal-oxide-semiconductor, is characterized in that, comprising:
Semiconductor substrate is provided, described semiconductor substrate surface is coated with voltage control layer, described voltage control layer surface coverage has the first extension intrinsic layer, described first extension intrinsic layer surface coverage has insulating barrier, there is in described insulating barrier the first grid structure running through its thickness, wherein, the ion of described first extension intrinsic layer and the interior doping of voltage control layer has concentration gradient, and the ion concentration of described first extension intrinsic layer is less than the ion concentration of described voltage control layer;
With described first grid structure for mask, in described first extension intrinsic layer, doping forms source/drain region;
Remove described first grid structure, form the opening exposing described first extension intrinsic layer surface;
Form the second extension intrinsic layer covering described open bottom;
The second grid structure covering described second extension intrinsic layer is formed in described opening.
2. the formation method of metal-oxide-semiconductor as claimed in claim 1, it is characterized in that having Doped ions in described voltage control layer, the concentration of described Doped ions is greater than 5E17atoms/cm
3, be less than 5E18atoms/cm
3.
3. the formation method of metal-oxide-semiconductor as claimed in claim 2, it is characterized in that, when forming NMOS tube, Doped ions in described voltage control layer is p-type ion, also doped with carbon ion in described voltage control layer, and the volume ratio that the carbon ion of doping accounts for total Doped ions of voltage control layer is less than 1%; When forming PMOS, the Doped ions in described voltage control layer is N-shaped ion, and also doped with germanium ion in described voltage control layer, and the volume ratio that the germanium ion of doping accounts for total Doped ions of voltage control layer is less than 3%.
4. the formation method of metal-oxide-semiconductor as claimed in claim 3, is characterized in that, the volume ratio that the carbon ion of described doping accounts for total Doped ions of voltage control layer is less than 0.1%.
5. the formation method of metal-oxide-semiconductor as claimed in claim 1, is characterized in that not having Doped ions in described first extension intrinsic layer; Or the ion concentration of doping in described first extension intrinsic layer is less than 1E16atoms/cm
3.
6. the formation method of metal-oxide-semiconductor as claimed in claim 1, is characterized in that not having Doped ions in described second extension intrinsic layer; Or the ion concentration of doping in described second extension intrinsic layer is less than 1E16atoms/cm
3.
7. the formation method of metal-oxide-semiconductor as claimed in claim 1, it is characterized in that, the thickness of described second epitaxial loayer is 3nm-10nm.
8. the formation method of metal-oxide-semiconductor as claimed in claim 1, it is characterized in that, the formation process of described second extension intrinsic layer is selective epitaxial depositing operation.
9. the formation method of metal-oxide-semiconductor as claimed in claim 1, is characterized in that, also comprise: before forming the second extension intrinsic layer, carry out annealing in process to the first extension intrinsic layer surface of described open bottom.
10. the formation method of metal-oxide-semiconductor as claimed in claim 9, is characterized in that, the gas that described annealing in process adopts is hydrogen or argon gas.
The formation method of 11. metal-oxide-semiconductors as claimed in claim 1, it is characterized in that, the forming step of described first grid structure comprises: formed and run through described insulating barrier and the pseudo-gate electrode layer being positioned at described first extension intrinsic layer surface; Form the pseudo-side wall being positioned at described pseudo-gate electrode layer both sides.
12. the formation method of metal-oxide-semiconductor as claimed in claim 11, is characterized in that, also comprise: after the pseudo-gate electrode layer of formation, before forming pseudo-side wall, with described pseudo-gate electrode layer for mask, light dope in described first extension intrinsic layer, forms light doping section; After the pseudo-side wall of formation, formed before insulating barrier, with described pseudo-side wall and pseudo-gate electrode layer for mask, heavy doping in described first extension intrinsic layer, forms source/drain region.
The formation method of 13. metal-oxide-semiconductors as claimed in claim 1, it is characterized in that, the forming step of described second grid structure comprises: form the side wall being positioned at described opening both sides; Form the high-K gate dielectric layer covering described second extension intrinsic layer and side wall; Formed and cover described high-K gate dielectric layer and the metal gate electrode layer flushed with described surface of insulating layer.
The formation method of 14. metal-oxide-semiconductors as claimed in claim 1, is characterized in that, also comprise: before formation first grid structure, form the etching barrier layer covering described first extension intrinsic layer surface.
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