CN103455281A - Two-port storage realized by single-port storage blocks - Google Patents
Two-port storage realized by single-port storage blocks Download PDFInfo
- Publication number
- CN103455281A CN103455281A CN2012102788301A CN201210278830A CN103455281A CN 103455281 A CN103455281 A CN 103455281A CN 2012102788301 A CN2012102788301 A CN 2012102788301A CN 201210278830 A CN201210278830 A CN 201210278830A CN 103455281 A CN103455281 A CN 103455281A
- Authority
- CN
- China
- Prior art keywords
- group
- write
- read
- address
- entry
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
A two-port storage comprises a read port, a write port and a plurality of identical single-port RAM (random access memory) sets. The capacity of one single-port RAM set is used to solve the conflict of simultaneous read and write access of the same single-port RAM set. A read mapping storage stores read instance information mapping a plurality of logic groups and one idle group to the single-port RAM sets for read access. Similarly, a write mapping storage stores write instance information mapping a plurality of logic groups and one idle group to the single-port RAM sets for write access. If simultaneous read and write access does not map to the same single-port RAM set, read and write are performed simultaneously. If conflict exists, the write access is remapped to the idle group appointed by the write instance information to allow simultaneous read and write. The read and write mapping storages are updated to reflect any remapping.
Description
Related application
The application requires on Dec 6th, 2010 application, the right of priority of the U.S. Provisional Patent Application that title is " two-port eDRAM " number 61/420,176.Above-mentioned application is incorporated herein by reference.
Invention field
Reservoir (RAM) is asked in the two-port random access that the present invention relates to utilize a plurality of one-port memory groups (memory bank) to realize.
Correlation technique
In network exchange ASIC, require high memory throughput to keep an acceptable bag processing speed.In addition, require large storage space to keep a large amount of bags that high-quality service is provided.
In order to obtain high memory throughput, typically use two-port static RAM (SRAM).As definition herein, two-port memory (2-port memory) comprises a read port and a write port, wherein from read port, carries out read operation, and carries out write operation from write port simultaneously.Note at the read port of two-port memory, only having read operation to be allowed to, and to only have write operation to be allowed at the write port of two-port memory.Two-port memory is different from dual-ported memory (dual-port memory), and on two ports of dual-ported memory, read and write operation all is allowed to.
The design district of two-port SRAM (layout area) compares relatively large with a port SRAM design district of same capability.More specifically, the design district of two-port SRAM is typically the twice in a port SRAM design district of same capability.In addition, the design district of two-port SRAM may be 3 to 4 times of design district of the dynamic RAM (DRAM) of the enhancing of same capability.Two-port SRAM has the ability of a large amount of bags of storage of more asking as network exchange ASIC, therefore will consume unwelcomely large design district on this ASIC.As a result of, the ASIC tube core may need the manufactured two-port SRAM that holds more greatly.Optionally, unlikely the two-port SRAM of desired volume is installed on the ASIC tube core of specific dimensions.
Therefore, want to have a kind of improved two-port memory, it does not show the relatively large design district demand of two-port SRAM.
Summary of the invention
Therefore, the present invention uses a plurality of identical single port random access memory (RAM) group to realize two-port memory, and wherein, a free storage group is appointed as in an initialization in these single port RAM group.This two-port memory comprises a read port and a write port.When write access (on write port) specifies first and simultaneously read access (on read port) in a plurality of single port RAM groups to specify second (different) in a plurality of single port RAM groups, there do not is conflict between write access and read access.In this case, write access and read access are performed simultaneously, and wherein this write access is to first execution in single port RAM group, and this read access is to second execution in single port RAM group.
For example, when write access and read access (have been specified identical single port RAM group simultaneously, " first " single port RAM group), (" first " single port RAM group to appointment carries out read access, read access has higher priority than write access), the entry place definite at the write address by write access carries out write access to the free storage group of appointment.In addition, for the write access to same item subsequently, should " first " single port RAM group be the free storage group by heavily specifying (mapping).In addition, for the read access to same item subsequently, initial appointed free storage group is " first " single port RAM group by heavily specifying (mapping).The mapping of single port RAM group is by two relatively little two-port memory realizations, and these two relatively little two-port memory and read port and write port interrelate.
Control in this way read access and write access, read access and write access indefinite ground are carried out at the read and write port simultaneously.Realize that by two-port memory of the present invention save in zone fully, because the single port RAM storer of optimization of region is used as primary memory.In a particular embodiment, single port RAM group is the DRAM group.
The present invention is understood the explanation based on following and accompanying drawing more fully.
The accompanying drawing explanation
Fig. 1 is the block diagram of the two-port memory of a plurality of single port RAM group of use according to an embodiment of the invention realization.
Fig. 2 is according to one embodiment of present invention, describes the block diagram that the logic of using in the two-port memory in Fig. 1 arrives the entry of physics (L2P) memory mapped SRAM.
Fig. 3 is according to one embodiment of present invention, and the L2P memory mapped SRAM and the single port RAM that describe the two-port memory in Fig. 1 organize the and then block diagram of the content after initialization.
Fig. 4 has described the L2P memory mapped SRAM of the two-port memory in Fig. 1 and the block diagram of the content of single port RAM group after a period of time, data value DATA1 and DATA2 were written to single port RAM group.
Fig. 5 has described the L2P memory mapped SRAM of the two-port memory in Fig. 1 and the block diagram of the content of single port RAM group after non-conflict read and write access is performed.
Fig. 6 A, 6B and 6C have described the L2P memory mapped SRAM of the two-port memory in Fig. 1 and single port RAM group at the block diagram to the content during being processed to the first read and write access conflict.
Fig. 7 A, 7B and 7C have described the L2P memory mapped SRAM of the two-port memory in Fig. 1 and single port RAM group at the block diagram to the content during being processed to the second read and write access conflict.
Fig. 8 A, 8B and 8C have described the L2P memory mapped SRAM of the two-port memory in Fig. 1 and single port RAM group at the block diagram to the content during being processed to the conflict of third reading write access.
Fig. 9 A, 9B and 9C have described the L2P memory mapped SRAM of the two-port memory in Fig. 1 and single port RAM group at the block diagram to the content during being processed to the 4th read and write access conflict.
Embodiment
Fig. 1 is the block diagram of two-port memory system 100 according to an embodiment of the invention.Accumulator system 100 comprises read port 101, write port 102, and read access logical one 11, write access logical one 12, the two-port logic is to physics (L2P) memory mapped SRAM121-122, Compare Logic 130 and primary memory 140.Primary memory 140 comprises single port RAM group P0-P4.In one embodiment, single port RAM group P0-P4 is the DRAM group that realizes the DRAM storage unit.In an optional embodiment, single port RAM group P0-P4 is realized by high density SRAM storage unit.Note using the DRAM unit to realize that single port RAM group P0-P4 advantageously provides high density to primary memory 140.The read access of primary memory 140 is started at read port 101, the write access of primary memory 140 is started at write port 102.According to an embodiment, two-port memory system 100 is in response to clock signal (CLK) work, and wherein the write access of while started during the identical clock period on port one 01 and 102.Each read access is read enable signal RD by activation and is started, and provides logic to read address RA[15:0 at read port 101].Similar, each write access is write enable signal WR by activation and is started, and provides logic write address WA[15:0 at write port 102] and write accordingly data value W_DATA.
Logic is two-port memory to physics (L2P) memory mapped SRAM121-122, and each two-port memory comprises N entry (N equals 16K in illustrated example).As described in detail below, write access logical one 12 maintains identical entry in L2P memory mapped SRAM121 and 122.L2P memory mapped SRAM121 and each entry sign logical group address of 122 and the corresponding relation between the physical set address.In illustrated example, four logical group address are arranged, it reads address bit RA[15:14 by two] or two write address bit WA[15:14] specify.Four logical storage groups that are associated with four logical group address are called as logical storage group L0-L3 after this.In the example of describing herein, logical storage group L0, L1, L2 and L3 have been assigned with respectively logical group address " 00 ", " 01 ", " 10 " and " 11 ".
Each in five single port RAM group P0-P4 has been assigned with the physical set address.Described above, each physical set address is meaned by three bit values.In the example than locating to describe, single port RAM organizes P0, P1, and P2, P3 and P4 have been assigned with respectively physical set address " 000 ", " 001 ", " 010 ", " 011 " and " 100 ".
Fig. 2 is 16K the entry E that has described L2P memory mapped SRAM121-122 according to an embodiment of the invention
0to E
16K-1block diagram.Each entry comprises 5 byte B
0, B
1, B
2, B
3and B
4, the first byte B wherein
0storage Mapping is to the physical set address of the single port RAM group of the first logical storage group L0; The second byte B
1storage Mapping is to the physical set address of the single port RAM group of the second logical storage group L1; The 3rd byte B
2the physical set address of the single port RAM group of Storage Mapping to the three logical storage group L2; Nybble B
3the physical set address of the single port RAM group of Storage Mapping to the four logical storage group L3; The 5th byte B
4store the physical set address of the single port RAM group of the free storage group (SP) of being appointed as particular items.
As shown in Figure 2, L2P memory mapped SRAM121-122 is initialised to programme and makes each for N entry, logical storage group L0, and L1, L2 and L3 are initialized to and are mapped to respectively single port RAM group P0, P1, P2 and P3.In addition, for each of N entry, single port RAM group P4 initially is appointed as the free storage group.The content of each entry of L2P memory mapped SRAM121-122 is called as " example information " hereinafter, points out that due to each entry which example of single port RAM group P0-P4 is mapped to logical storage group L0-L3.
According to one embodiment of present invention, accumulator system 100 operates as follows.In response to receive a read access request at read port 101, read access logical one 11 is fetched example information (R_INST) from L2P memory mapped SRAM121.More specifically, read access logical one 11 activates and reads enable signal RE1 (in response to the RD signal activated) transmission logic and read the read port (R_PORT) of the entry address portion of address (that is, RA[13:0]) to L2P memory mapped SRAM121.As response, L2P memory mapped SRAM121 provides by reading entry address RA[13:0] entry of appointment is as reading example information (R_INST).
Which in identification form port ram group P0-P4 be the example information of reading (R_INST) that read access logical one 11 decoding is fetched be mapped to by logic to read address RA[15:14] the logical storage group of appointment.For example,, if logic is read address bit RA[15:14] specify logical storage group L0 (that is, RA[15:14]=" 00 "), then read access logical one 11 will be from the first byte B of the example information of fetching
0fetch the physical set address.Therefore, in initialization (Fig. 2) afterwards, read access logical one 11 will be fetched the physical set address (for example, " 000 ") of distributing to single port RAM group P0 immediately.
Read access logical one 11 use are read address RA[15:0 from the physical set address of reading example information R_INST and fetching by logic] be translated as physical read address PRA[16:0].This physical read address PRA[16:0] comprise from reading the thin address of physics that example information R_INST fetches as bit PRA[16:14], and read address bit RA[13:0] as bit PRA[13:0].
Read access logical one 11 provides physical read group address bit PRA[16:14] to Compare Logic 130.As described in detail below, Compare Logic 130 is physical read group address PRA[16:14 relatively] and physical write group address (described below) determine between read access and the write access of while whether have conflict.
Read access logical one 11 provides physical read address PRA[16:0 equally] give primary memory 140, and activate and read enable signal RE3.In this case, by physical read group address PRA[16:14] in the single port RAM group of appointment, from by reading entry address PRA[13:0] entry of appointment carries out read access.Corresponding read data value R_DATA is routed to read access logical one 11 from the single port RAM group of access.Read access logical one 11 sends read data value R_DATA to read port 101, completes thus read access.
In the example of describing, read access has the priority higher than write access, makes read access always to by physical read group address PRA[16:14] the single port RAM group of appointment carries out, do not postpone or remap.As hereinafter described in detail, the conflict between write access when specifying identical single port RAM group is by solving remapping of write access.
Write access to accumulator system 100 is carried out as follows.In response to receive a write access request at write port 102, write access logical one 12 is fetched example information (W_INST) from L2P memory mapped SRAM122.More specifically, write access logical one 12 activates the entry address portion of reading enable signal RE2 (in response to the WR signal activated) transmission logic write address (that is, the WA[13:0]) read port (R_PORT) to L2P memory mapped SRAM122.As response, L2P memory mapped SRAM122 provides by write address WA[13:0] entry of appointment is as writing example information (W_INST).
Which in identification form port ram group P0-P4 be the example information of writing (W_INST) that write access logical one 12 decoding is fetched be mapped to by logic write address WA[15:14] the logical storage group of appointment.For example,, if logic write address bit WA[15:14] specify logical storage group L2 (that is, WA[15:14]=" 10 "), then write access logical one 12 will be from the 3rd byte B of the example information of writing of fetching
2fetch the physical set address.Therefore, in initialization (Fig. 2) afterwards, write access logical one 12 will be fetched the physical set address (for example, " 010 ") of distributing to single port RAM group P2 immediately.The physical write group address that this is fetched is designated PWA[16:14 in Fig. 1], be provided for Compare Logic 130.
During each access cycle, the physical write group address PWA[16:14 that Compare Logic 130 relatively receives from write access logical one 12] and the physical read group address PRA[16:14 that receives from the read access logic].If the coupling of detecting, show that read access and write access attempt to access physical storage group identical in primary memory 140, then Compare Logic 130 activates a coupling (MATCH) control signals.If coupling do not detected, Compare Logic 130 makes this match control invalidating signal.
This match control signal is provided for write access logical one 12.If this match control signal has disarmed state (show not conflict), the physical set address PWA[16:14 that write access logical one 12 is fetched from writing example information W_INST before using] carry out the write access to primary memory 140.More specifically, write access logical one 12 provides the TWA[16:0 of the physical write address after translation] give primary memory 140, wherein TWA[16:14] the physical set address PWA[16:14 that fetches before equaling], TWA[13:0] equal to write entry address bit WA[13:0].Enable signal WE1 is write in one of the same activation of write access logical one 12, and it is provided for primary memory 140, provides equally and writes data value W_DATA to primary memory 140.In this case, primary memory 140 will be write data value W_DATA and be written to by physical write address PWA[16:14] for example,, in the single port RAM group of appointment (, group P2), write on by writing entry address WA[13:0] the entry place of appointment.Note this write access can with the read access executed in parallel be associated because these access occur in single port RAM group P0-P4 not on the same group in.
If this match control signal is activated (showing the conflict between write access and read access) by conflict logic 130 simultaneously, the example information of the writing W_INST fetched before write access logical one 12 use comes for the physical write address TWA[16:0 after translation of write access generation], thus conflict removal.More specifically, the 5th byte B of the example information of the writing W_INST that the write access logical access is fetched
4, determine which in single port RAM group P0-P4 is designated as the free storage group of the entry for being written at present.For example, immediately in initialization (Fig. 2) afterwards, the example information of the writing W_INST of each entry shows that single port RAM group P4 is designated as free storage group (that is, byte B
4=" 100 ").Write access logical one 12 generates the physical write address TWA[16:0 after translation], make TWA[16:14] equal the address of free storage group, TWA[13:0] equal to write entry address WA[13:0].Write access logical one 12 provides the TWA[16:0 of the physical write address after translation], and write data value W_DATA and be activated write enable signal WE1 to primary memory 140.As response, primary memory 140 will be write data value W_DATA and be written to by the physical write address bit TWA[16:14 after translation] in the free storage group of appointment (for example, group P4), write on by the physical write address bit TWA[13:0 after translation] in the entry of appointment.This write access can with the read access executed in parallel be associated because single port RAM group P0-P4 not on the same group in these access of execution.
If this match control signal is activated (showing conflict) by conflict logic 130, the same read and write example information of upgrading by the entry of the write access appointment entry of appointment (that is, by the write address bit WA[13:0]) of write access logical one 12.Namely, read and write example information is updated to reflect new idle group by the entry of write access appointment.More specifically, the following modification of write access logical one 12 write example information W_INST.That writes example information W_INST writes group address WA[15:14 with logic] byte be associated and the byte B be associated with the free storage group that writes example information W_INST
4exchange, create amended example information MOD_INST thus.For example, suppose read access and write access conflict, write access specifies logical group address L0 (that is, to write the byte B of example information simultaneously
0).Further suppose byte B
0identification form port store group P0 (that is, B
0=" 000 ").As described above, write the byte B of example information W_INST
4specify the free storage group.Suppose byte B
4identification form port store group P4 (that is, B
4=" 100 ").In this case, the byte B of example information W_INST is write in 12 exchanges of write access logical one
0and B
4create amended example information MOD_INST.Result is, the byte B of amended example information MOD_INST
4equal " 000 ", show that thus single port RAM group P0 has become the free storage group of the entry be associated.Similarly, the byte B of amended example information MOD_INST
0equal " 100 ", show that thus single port RAM group P4 has become the logical storage group L0 of this entry.
Write access logical one 12 is written to L2P memory mapped SRAM121 and 122 by amended example information MOD_INST, writes on by writing entry address WA[13:0] in the entry of appointment.More specifically, write access logical one 12 provides amended example information MOD_INST and writes entry address WA[13:0] give the write port (W_PORT) of L2P memory mapped SRAM121-122, and activate the corresponding enable signal WE2 that writes and start these write operations.In the example of describing, write access logical one 12 is written to L2P memory mapped SRAM121_122 by amended example information MOD_INST, writes data value W_DATA simultaneously and is written to primary memory 140, and read data value R_DATA reads from primary memory 140.Because the same item of L2P memory mapped SRAM121 and 122 is used identical amended example information MOD_INST and is upgraded, these SRAM121 and 122 content accumulator system 100 normal work period are phase orders with.
To describe now an exemplary write access sequence in detail, carry out thus further to illustrate the operation of accumulator system 100.Fig. 3,4,5,6A-6C, 7A-7C, 8A-8C and 9A-9C are exemplified with the concrete write and read sequence of operation, and it is carried out according to one embodiment of present invention.
Fig. 3 is the block diagram exemplified with the content of the single port RAM group P0-P4 of the content of the immediately L2P memory mapped SRAM121-122 after initialization according to an embodiment of the invention and primary memory 140.As shown in Figure 3, the identical value as described above that L2P memory mapped SRAM121-122 storage interrelates with Fig. 2.Note, the 3 bit-binary physical set address values of Fig. 2 substitute (for clear) by corresponding integer in Fig. 3.Therefore, logical storage group L0-L3 is mapped to respectively single port RAM group P0-P3, and the free storage group is mapped to single port RAM group P4.All entries of single port RAM group P0-P4 are initially sky (or invalid).
Fig. 4 has described at data value DATA1 to be written to the entry E in single port RAM group P0
0, data value DATA2 is written to the entry E in single port RAM group P2
0afterwards, the block diagram of the content of L2P memory mapped SRAM121-122 and single port RAM group P0-P4.These write accesss in the situation that be performed without any conflicting with read access, make content and Fig. 3 of L2P memory mapped SRAM121-122 remain unchanged.Note, if do not have conflict between the write access of read access and correspondence, the example information of being preserved by L2P memory mapped SRAM121-122 can not be modified.
Fig. 5 has described after the read access of logic being read to address 0x0000 and the write access to logic write address 0x4000, the block diagram of the content of L2P memory mapped SRAM121-122 and single port RAM group P0-P4 simultaneously.Read access logical one 11, according to above-described mode, is read entry address RA[13:0 in response to logic], from the entry E of L2P memory mapped SRAM121
0fetch the example information of reading.Read access logical one 11 these entry E that fetch of decoding
0determine read access specify single port RAM group P0 (that is, logic is read address RA[15:14]=" 00 "=logical storage group L0=byte B
0=physical set P0).
Similarly, write access logical one 12, according to above-described mode, is write entry address WA[13:0 in response to logic], from the entry E of L2P memory mapped SRAM122
0fetch the example information of writing.Write access logical one 12 these entry E that fetch of decoding
0determine write access specify single port RAM group P1 (that is, logic write address WA[15:14]=" 01 "=logical storage group L2=byte B
1=physical set P1).Conflict logic 130 is determined do not have conflict between read access and write access.Result is that to single port RAM group, P0 carries out read access, single port RAM group P1 is carried out to write access simultaneously.More specifically, read access logical one 11 is from the entry E of single port RAM group P0
0reading out data value DATA1, write access logical one 12 is to the entry E of single port RAM group P1 simultaneously
0data writing value DATA3.Owing to not conflicting, measured, the content of L2P memory mapped SRAM121-122 is not modified.
Fig. 6 A-6C is during exemplified with the read access of logic being read to address 0x0000 and the write access to logic write address 0x0001 simultaneously, the block diagram of L2P memory mapped SRAM121-122 and single port RAM group P0-P4.As shown in Figure 6A, read access logical one 11, according to above-described mode, is read entry address RA[13:0 in response to logic], from the entry E of L2P memory mapped SRAM121
0fetch the example information of reading.Read access logical one 11 these entry E that fetch of decoding
0determine this read access specify single port RAM group P0 (that is, logic is read address RA[15:14]=" 00 "=logical storage group L0=byte B
0=physical set P0).
Similarly, write access logical one 12, according to above-described mode, is write entry address WA[13:0 in response to logic], from the entry E of L2P memory mapped SRAM122
1fetch the example information of writing.Write access logical one 12 these entry E that fetch of decoding
1determine write access specify single port RAM group P0 (that is, logic write address WA[15:14]=" 00 "=logical storage group L0=byte B
0=physical set P0).Conflict logic 130 is determined existence conflict between read access and write access.
As shown in Figure 6B, when having conflict, read access has higher priority, so read access logical one 11 is allowed to from the entry E of single port RAM group P0
0reading out data value DATA1.Write access logical one 12 determines that from writing example information of fetching single port RAM group P4 is as free storage group (that is, byte B
4=physical set P4).Then write access logical one 12 is written to the data value DATA4 of write access the entry E of this " free time " single port RAM group P4
1in.From the read access of single port RAM group P0 can with the write access executed in parallel to single port RAM group P4 because do not have conflict between these access.
As shown in Figure 6 C, the content of L2P memory mapped SRAM121-122 is updated the solution that correctly reflects conflict.More specifically, L2P memory mapped SRAM121 and 122 entry E
1be updated the byte B made in these entries
0storing value " 4 ", the byte B in these entries
4storing value " 0 ".This renewal has correctly reflected the following fact: the follow-up entry E to logical storage group L0
1read access should be mapped to single port RAM group P4 and (notice that data value DATA4 is stored in the entry E of group P4
1in).This renewal has equally correctly reflected that the following fact: single port RAM group P0 has become entry E now
1the free storage group.Note, although single-port SRAM group P4 starts as entry E
1the free storage group, be understandable that any one in RAM group P0-P4 can at any time become entry E
1the free storage group of (or any entry).
Fig. 7 A-7C is during exemplified with the read access of logic being read to address 0x4000 and the write access to logic write address 0x4000 simultaneously, the block diagram of L2P memory mapped SRAM121-122 and single port RAM group P0-P4.As shown in Figure 7 A, read access logical one 11 is read entry address RA[13:0 in response to logic], from the entry E of L2P memory mapped SRAM121
0fetch the example information of reading.Read access logical one 11 these entry E that fetch of decoding
0determine this read access specify single port RAM group P1 (that is, logic is read address RA[15:14]=" 01 " and logical storage group L1=byte B
1=physical set P1).
Similarly, write access logical one 12 is write entry address WA[13:0 in response to logic], from the entry E of L2P memory mapped SRAM122
0fetch the example information of writing.Write access logical one 12 these entry E that fetch of decoding
0determine write access specify single port RAM group P1 (that is, logic write address WA[15:14]=" 01 "=logical storage group L1=byte B
1=physical set P1).Conflict logic 130 is determined existence conflict between read access and write access.
As shown in Figure 7 B, when having conflict, read access has higher priority, so read access logical one 11 is allowed to from the entry E of single port RAM group P1
0reading out data value DATA3.Write access logical one 12 is write example information identification form port ram group P4 as free storage group (that is, byte B from what fetch
4sign physical set P4).Then write access logical one 12 is written to the data value DATA5 of write access the entry E of this " free time " single port RAM group P4
0in.From the read access of single port RAM group P1 can with the write access executed in parallel to single port RAM group P4 because do not have conflict between these access.
As shown in Fig. 7 C, the content of L2P memory mapped SRAM121-122 is updated the solution that correctly reflects conflict.More specifically, L2P memory mapped SRAM121 and 122 entry E
0be updated the byte B made in these entries
1storing value " 4 ", the byte B in these entries
4storing value " 1 ".This renewal has correctly reflected the following fact: the follow-up entry E to logical storage group L1
0read access should be mapped to single port RAM group P4 and (notice that data value DATA5 is stored in the entry E of group P4
0in).This renewal has equally correctly reflected that the following fact: single port RAM group P1 has become entry E now
0the free storage group.Note, the different group in single-port SRAM group P0-P4 can be the free storage group of different entries simultaneously.In the example of Fig. 7 C, single-port SRAM group P1 is entry E
0idle group, simultaneously single-port SRAM group P0 is entry E
1the free storage group.
Fig. 8 A-8C is during exemplified with the read access of logic being read to address 0x8000 and the write access to logic write address 0x8001 simultaneously, the block diagram of L2P memory mapped SRAM121-122 and single port RAM group P0-P4.As shown in Figure 8 A, read access logical one 11 is read entry address RA[13:0 in response to logic], from the entry E of L2P memory mapped SRAM121
0fetch the example information of reading.Read access logical one 11 these entry E that fetch of decoding
0determine this read access specify single port RAM group P2 (that is, logic is read address RA[15:14]=" 10 "=logical storage group L2=byte B
2=physical set P2).
Similarly, write access logical one 12 is write entry address WA[13:0 in response to logic], from the entry E of L2P memory mapped SRAM122
1fetch the example information of writing.Write access logical one 12 these entry E that fetch of decoding
1determine write access specify single port RAM group P2 (that is, logic write address WA[15:14]=" 10 "=logical storage group L2=byte B
2=physical set P2).Conflict logic 130 is determined existence conflict between read access and write access.
As shown in Figure 8 B, when having conflict, read access has higher priority, so read access logical one 11 is allowed to from the entry E of single port RAM group P2
0reading out data value DATA2.Write access logical one 12 is write example information identification form port ram group P0 as free storage group (that is, byte B from what fetch
4sign physical set P0).Note, due to the conflict that top contact Fig. 6 A-6C describes, single port RAM group P4 is no longer entry E
1the free storage group.Write access logical one 12 is written to the data value DATA6 of write access the entry E of identified idle single port RAM group P0
1in.From the read access of single port RAM group P2 can with the write access executed in parallel to single port RAM group P0 because do not have conflict between these access.
As shown in Figure 8 C, the content of L2P memory mapped SRAM121-122 is updated the solution that correctly reflects conflict.More specifically, L2P memory mapped SRAM121 and 122 entry E
1be updated the byte B made in these entries
2storing value " 0 ", the byte B in these entries
4storing value " 2 ".This renewal has correctly reflected the following fact: the follow-up entry E to logical storage group L2
1read access should be mapped to single port RAM group P0 and (notice that data value DATA6 is stored in the entry E of group P0
1in).This renewal has equally correctly reflected that the following fact: single port RAM group P2 has become entry E now
1the free storage group.
Fig. 9 A-9C is during exemplified with the read access of logic being read to address 0x4000 and the write access to logic write address 0x0001 simultaneously, the block diagram of L2P memory mapped SRAM121-122 and single port RAM group P0-P4.As shown in Figure 9 A, read access logical one 11 is read entry address RA[13:0 in response to logic], from the entry E of L2P memory mapped SRAM121
0fetch the example information of reading.Read access logical one 11 these entry E that fetch of decoding
0determine this read access specify single port RAM group P4 (that is, logic is read address RA[15:14]=" 01 "=logical storage group L1=byte B
1=physical set P4).
Similarly, write access logical one 12 is write entry address WA[13:0 in response to logic], from the entry E of L2P memory mapped SRAM122
1fetch the example information of writing.Write access logical one 12 these entry E that fetch of decoding
1determine write access specify single port RAM group P4 (that is, logic write address WA[15:14]=" 00 "=logical storage group L0=byte B
0=physical set P4).Conflict logic 130 is determined existence conflict between read access and write access.Note, this specific read access for the moment and write access do not lead to a conflict immediately after accumulator system 100 is initialised.Yet dynamically remapping of free storage group caused current conflict.
As shown in Fig. 9 B, when having conflict, read access has higher priority, so read access logical one 11 is allowed to from the entry E of single port RAM group P4
0reading out data value DATA5.Write access logical one 12 is write example information identification form port ram group P2 as free storage group (that is, byte B from what fetch
4indication physical set P2).Then write access logical one 12 is written to the data value DATA7 of write access the entry E of this idle single port RAM group P2
1in.From the read access of single port RAM group P4 can with the write access executed in parallel to single port RAM group P2 because do not have conflict between these access.
As shown in Fig. 9 C, the content of L2P memory mapped SRAM121-122 is updated the solution that correctly reflects conflict.More specifically, L2P memory mapped SRAM121 and 122 entry E
1be updated the byte B made in these entries
0storing value " 2 ", the byte B in these entries
4storing value " 4 ".This renewal has correctly reflected the following fact: the follow-up entry E to logical storage group L0
1read access should be mapped to single port RAM group P2 and (notice that data value DATA7 is stored in the entry E of group P2
1in).This renewal has equally correctly reflected that the following fact: single port RAM group P4 has become entry E now
1the free storage group.
According to above-described method, any on port one 01 and 102 read access in appointment and write access sequence can be realized by two-port memory system 100.
Two-port memory system 100 is the design district reduced with respect to an advantage of the two-port memory system realized by two-port memory fully.Yet two-port L2P memory mapped SRAM121-122 requires to design significantly district in accumulator system 100.In the distortion of the embodiment described, encode to reduce the width of this example information by the example information to storage in L2P memory mapped SRAM121 and 122 in the above.As described above, 5 physical memory address of each entry storage of storing in SRAM121-122, its scope is from " 0 " to " 4 ".Arbitrary logical storage group L0-L3 can be mapped to physical storage group P0-P4 arbitrarily.(that is, each logical storage group is mapped to unique physical storage group) that this mapping is normally unique.Therefore, the sum of the combination of five physical storage groups equals 5 * 4 * 3 * 2 * 1, or 120.These 120 kinds of combinations can only be used the example information of 7 bits to be meaned (that is, 7 bits can mean up to 128 kinds of combinations).In one embodiment, provide logic this 7 bit example information of decoding in read access logical one 11 and write access logical one 12.The width that reduces by this way two-port L2P memory mapped SRAM121 and 122 can advantageously further reduce the design district of the accumulator system 100 needed.
According to another distortion of the present invention, each entry of L2P memory mapped SRAM121-122 is used corresponding error correcting code (ECC) to be protected.For example, the ECC scheme provides the ability of correcting single-bit error and detecting the dibit mistake.In one embodiment, a plurality of entries of SRAM121-122 are combined, and are the entry generation ECC bit of combination, reduce thus the quantity of the ECC bit that need to be stored by SRAM121-122.For example, four entries (4 entry * 7 bits/entry=28 bits) are combined, and these four entries are by the ECC protection of 7 bits.The shared ECC bit of a plurality of entries has further reduced the capacity of needed two-port L2P memory mapped SRAM121 and 122, advantageously further reduces thus the design district of the accumulator system 100 needed.
With the two-port SRAM accumulator system of same capability, compare, the area savings realized by accumulator system 100 can be summarized as under mouth.The area of supposing each port ram group P0-P4 (having separately capacity 16K * 256) equals Y, and the area of two two-port L2P memory mapped SRAM121 and 122 (it realizes that example information coding and ECC are shared as described above separately) is Y.In this case, the area of accumulator system 100 is approximately 6Y (that is, 5Y+Y).The area that further hypothesis has the two-port SRAM of capacity 16K * 256 is 4Y.The area of the two-port 64K that in this case, only uses two-port SRAM to realize * 256 accumulator systems is approximately 16Y (that is, 4 * 4Y).Therefore, the area savings realized by accumulator system 100 be approximately 10Y (that is, 16Y-6Y), or about 62.5% (that is, 10Y/16Y=62.5%).Therefore with traditional two-port memory system, compare, accumulator system 100 has realized significant area savings.
Described the present invention although contacted a plurality of embodiment, be understandable that the distortion of these embodiment apparent to those skilled in the art.Therefore, the present invention only limits by following claim.
Claims (35)
1. a two-port memory comprises:
N one-port memory group, each one-port memory group has M entry, and wherein N is more than or equal to 2 integer;
What with the read port of this two-port memory, be associated reads mapping memory, wherein this is read mapping memory and comprises M entry, and each entry has been stored the example information of reading that N-1 logical storage group and free storage group is mapped to N one-port memory group; And
What with the write port of this two-port memory, be associated writes mapping memory, wherein this is write mapping memory and comprises M entry, and each entry has been stored the example information of writing that N-1 logical storage group and described free storage group is mapped to N one-port memory group.
2. two-port memory as claimed in claim 1, each that wherein read in M entry of mapping memory is associated with the corresponding entry in each M entry in N one-port memory group.
3. two-port memory as claimed in claim 2, each of M entry of wherein writing mapping memory is associated with the corresponding entry in M entry in each in N one-port memory group.
4. two-port memory as claimed in claim 1, wherein be stored in the example information of reading read in mapping memory be stored in write in mapping memory to write example information identical.
5. two-port memory as claimed in claim 1, wherein reading mapping memory is the two-port memory with read port and write port, and wherein to write mapping memory be the two-port memory that tool is economized read port and write port.
6. two-port memory as claimed in claim 5, further comprise the write access logic, described write access logic be coupled to two-port memory write port, write the read port of mapping memory, the read port of writing the write port of mapping memory and writing mapping memory.
7. two-port memory as claimed in claim 6, further comprise the read access logic, the read port that described read access logic is coupled to the read port of two-port memory and reads mapping memory.
8. two-port memory as claimed in claim 1, wherein said N one-port memory group is identical.
9. two-port memory as claimed in claim 1, wherein said N one-port memory group is dynamic RAM (DRAM) group.
10. two-port memory as claimed in claim 1 further comprises:
The read access logic, described read access logic receives read access request, described read access request comprise the logic of sign one of N-1 logical groups read group address and sign read mapping memory one of a plurality of entries read the entry address, wherein said read access logic fetches from the entry by reading the entry address designation of reading mapping memory the example information of reading, and, as response, logic is read to group address and be mapped to the physical read group address of specifying one of N one-port memory group; And
The write access logic, described write access logic receives write access request, this write access request comprise the logic of sign one of N-1 logical groups write group address and sign write mapping memory one of a plurality of entries write the entry address, wherein this write access logic fetches from the entry by writing the entry address designation of writing mapping memory the example information of writing, and, as response, logic is write to group address and be mapped to the physical write group address of specifying one of N one-port memory group.
11. two-port memory as claimed in claim 10, further comprise Compare Logic, described Compare Logic comparison physical read group address and physical write group address are to determine whether to exist coupling.
12. two-port memory as claimed in claim 11, wherein said write access logic is coupled to described Compare Logic, if wherein described Compare Logic is determined the existence coupling, described write access logic uses the fetched example information of writing that the physical write group address is translated as to idle group address.
13. two-port memory as claimed in claim 12, wherein said write access logic is coupled to described mapping memory and the described mapping memory of writing read, if wherein determine there is coupling in described Compare Logic, described write access logical renewal is in the described example information of writing in writing mapping memory and in the described example information of reading in reading mapping memory.
14. a two-port memory comprises:
N one-port memory group, each one-port memory group has a plurality of entries, and wherein N is more than or equal to 2 integer, and wherein said N one-port memory group realizes N-1 logical storage group and a free storage group;
Read mapping memory, the described mapping memory of reading has a plurality of entries, each entry has been stored the example information of reading, and the described example information pointer of reading is mapped to described N one-port memory group to N respective entries in described N one-port memory group by described N-1 logical storage group and described free storage group; And
Write mapping memory, the described mapping memory of writing has a plurality of entries, each entry has been stored the example information of writing, and the described example information pointer of writing is mapped to described N one-port memory group to N respective entries in described N one-port memory group by described N-1 logical storage group and described free storage group.
15. two-port memory as claimed in claim 14, wherein be stored in described read the example information of reading in mapping memory be stored in described write in mapping memory to write example information identical.
16. two-port memory as claimed in claim 14 further comprises:
The read access logic, described read access logic receives read access request, described read access request comprise the logic of sign one of N-1 logical groups read group address and sign read mapping memory one of a plurality of entries read the entry address, wherein said read access logic fetches from the entry by reading the entry address designation of reading mapping memory the example information of reading, and, as response, logic is read to group address and be mapped to the physical read group address of specifying one of N one-port memory group; And
The write access logic, described write access logic receives write access request, described write access request comprise the logic of sign one of N-1 logical groups write group address and sign write mapping memory one of a plurality of entries write the entry address, wherein said write access logic fetches from the entry by writing the entry address designation of writing mapping memory the example information of writing, and, as response, logic is write to group address and be mapped to the physical write group address of specifying one of N one-port memory group.
17. two-port memory as claimed in claim 16, further comprise Compare Logic, described Compare Logic compares to determine whether to exist coupling to physical read group address and physical write group address.
18. two-port memory as claimed in claim 17, wherein said write access logic is coupled to described Compare Logic, if wherein described Compare Logic is determined the existence coupling, described write access logic uses the fetched example information of writing that the physical write group address is translated as to idle group address.
19. two-port memory as claimed in claim 18, wherein said write access logic is coupled to described mapping memory and the described mapping memory of writing read, if wherein described Compare Logic is determined coupling, the described example information of writing and the described example information of reading of reading in mapping memory of writing in mapping memory of described write access logical renewal of existing.
20. a method that realizes two-port memory comprises:
Use N one-port memory group to realize the physical storage of two-port memory, each one-port memory group has M entry, and wherein N is more than or equal to 2 integer;
Maintain the mapping memory of reading be associated with the read port of described two-port memory, the wherein said mapping memory of reading comprises M entry, and each entry has been stored the example information of reading that N-1 logical storage group and free storage group is mapped to described N one-port memory group; And
Maintain the mapping memory of writing be associated with the write port of described two-port memory, the wherein said mapping memory of writing comprises M entry, and each entry has been stored the example information of writing that N-1 logical storage group and free storage group is mapped to N one-port memory group.
21. method as claimed in claim 20 further comprises:
Receive read access request at read port, described read access request comprises that logic reads group address and read the entry address;
Use the described described mapping memory of reading of entry addressing of address of reading, from reading mapping memory, fetch the example information of reading; And
By the example information of reading of fetching, logic is read to group address and be mapped as the physical read group address of specifying one of N one-port memory group.
22. method as claimed in claim 21 further comprises:
Receive write access request at write port, described write access request comprises that logic writes group address and write the entry address;
Use the described described mapping memory of writing of entry addressing of address of writing, from writing mapping memory, fetch the example information of writing; And
By the example information of writing of fetching, logic is write to group address and be mapped as the physical write group address of specifying one of N one-port memory group.
23. method as claimed in claim 22, further comprise and determine whether described physical read group address is complementary with described physical write group address.
24. method as claimed in claim 23 further comprises if described physical read group address and described physical write group address are complementary carry out following step:
By the fetched example information of writing, come described physical write group address is remapped to the idle group address of specifying one of described N one-port memory group; And
To one of described N one-port memory group by described idle group address appointment, carry out write access at the entry place by writing the appointment of entry address, and concurrently, to one of described N one-port memory group by the appointment of described physical read group address, at the entry place by reading the appointment of entry address, carry out read access.
25. method as claimed in claim 23 further comprises if described physical read group address and described physical write group address are complementary carry out following step:
Revise the example information of writing of fetching, create thus amended example information;
Amended example information is written to described writing in mapping memory by the place, address of writing the appointment of entry address; And
This amended example information is written to described reading in mapping memory by the place, address of writing the appointment of entry address.
26. method as claimed in claim 23 further comprises if described physical read group address and described physical write group address are not complementary carry out following step:
To one of described N one-port memory group by the appointment of described physical write group address, at the entry place by writing the appointment of entry address, carry out write access; And concurrently,
To one of described N one-port memory group by the appointment of described physical read group address, at the entry place by reading the appointment of entry address, carry out read access.
27. a method that realizes two-port memory comprises:
Receive read access request at read port, this read access request comprises that logic reads group address and read the entry address;
In response to the described entry address of reading, described logic is read to group address and be mapped to the physical read group address;
Receive write access request at write port, described write access request comprises that logic writes group address and write the entry address;
In response to the described entry address of writing, described logic is write to group address and be mapped to the physical write group address;
More described physical read group address and the thin address of described physical write determine whether to exist coupling; And
If the coupling of existence,
In response to the described entry address of writing, described physical write group address is translated as to idle group address; And
To by the described entry of reading the first one-port memory group of entry address and the appointment of described physical read group address, carrying out read access, and concurrently, to by the described entry of writing the second one-port memory group of entry address and described idle group address appointment, carrying out write access.
28. method as claimed in claim 27, wherein if there is no mate, to by the described entry of reading the first one-port memory group of entry address and the appointment of described physical read group address, carrying out read access, and concurrently, to by the described entry of writing the 3rd one-port memory group of entry address and the appointment of described physical write group address, carrying out write access.
29. method as claimed in claim 27, if wherein there is coupling, upgrades with described and write the map information that the entry address is associated.
30. method as claimed in claim 27, wherein saidly described logic is read to step that group address is mapped to the physical read group address comprise from reading mapping memory and fetch the example information of reading, the wherein said entry of reading mapping memory is specified by the described entry address of reading, and the wherein said example information of reading is read group address by described logic and is mapped to described physical read group address.
31. method as claimed in claim 30, wherein saidly described logic is write to step that group address is mapped to the physical write group address comprise from writing mapping memory and fetch the example information of writing, the wherein said entry of writing mapping memory is specified by the described entry address of writing, and the wherein said example information of writing is write group address by described logic and is mapped to described physical write group address.
32. method as claimed in claim 31, further be included in and describedly read mapping memory and write in mapping memory the example information that remains identical.
33. method as claimed in claim 31, wherein saidly read the example information definition and read the mapping to a plurality of physical read group addresss of group address and idle group address from a plurality of logics.
34. method as claimed in claim 33, wherein saidly write the example information definition and write the mapping to a plurality of physical write group addresss of group address and idle group address from a plurality of logics.
35. method as claimed in claim 34, further comprise by the described example information of writing described physical write group address be translated as to idle group address.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210278830.1A CN103455281B (en) | 2012-05-30 | 2012-05-30 | The two-port memory realized by one-port memory block |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210278830.1A CN103455281B (en) | 2012-05-30 | 2012-05-30 | The two-port memory realized by one-port memory block |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103455281A true CN103455281A (en) | 2013-12-18 |
| CN103455281B CN103455281B (en) | 2018-01-09 |
Family
ID=49737706
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210278830.1A Active CN103455281B (en) | 2012-05-30 | 2012-05-30 | The two-port memory realized by one-port memory block |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103455281B (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104333674A (en) * | 2014-11-24 | 2015-02-04 | 广东中星电子有限公司 | Video stabilization method and video stabilization device |
| CN106095328A (en) * | 2015-04-29 | 2016-11-09 | 马维尔以色列(M.I.S.L.)有限公司 | Each cycle has a read port and the multi-bank memory of one or more write port |
| CN106126112A (en) * | 2015-05-07 | 2016-11-16 | 马维尔以色列(M.I.S.L.)有限公司 | Each cycle has multiple read port and a plurality of memorizer of multiple write port |
| CN107526534A (en) * | 2016-06-21 | 2017-12-29 | 伊姆西公司 | The method and apparatus for managing the input and output (I/O) of storage device |
| CN107545914A (en) * | 2016-06-27 | 2018-01-05 | 阿尔特拉公司 | Method and apparatus for smart memory interface |
| WO2018148918A1 (en) * | 2017-02-17 | 2018-08-23 | 深圳市大疆创新科技有限公司 | Storage apparatus, chip, and control method for storage apparatus |
| CN108984148A (en) * | 2018-06-13 | 2018-12-11 | 浙江大华技术股份有限公司 | A kind of method and memory of the data storage based on synchronization fifo memory |
| CN110704369A (en) * | 2019-10-09 | 2020-01-17 | 盛科网络（苏州）有限公司 | Memory and control method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1504890A (en) * | 2002-12-03 | 2004-06-16 | 中国科学院计算技术研究所 | Address mapping method and system for FFT processor with completely parallel data |
| CN1555063A (en) * | 2003-12-19 | 2004-12-15 | 北京中星微电子有限公司 | Synchronous single nort SRAM capable of realizng synchronous double port SRAM effect and its realizing method |
| US20090089532A1 (en) * | 2007-09-27 | 2009-04-02 | Integrated Device Technology, Inc. | Serial Buffer Supporting Virtual Queue To Physical Memory Mapping |
| US20110145777A1 (en) * | 2009-12-15 | 2011-06-16 | Sundar Iyer | Intelligent memory system compiler |
| US20110302376A1 (en) * | 2010-06-04 | 2011-12-08 | Lsi Corporation | Two-port memory capable of simultaneous read and write |
| CN102436427A (en) * | 2011-11-07 | 2012-05-02 | 华为技术有限公司 | Data read-write method and storage device |
-
2012
- 2012-05-30 CN CN201210278830.1A patent/CN103455281B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1504890A (en) * | 2002-12-03 | 2004-06-16 | 中国科学院计算技术研究所 | Address mapping method and system for FFT processor with completely parallel data |
| CN1555063A (en) * | 2003-12-19 | 2004-12-15 | 北京中星微电子有限公司 | Synchronous single nort SRAM capable of realizng synchronous double port SRAM effect and its realizing method |
| US20090089532A1 (en) * | 2007-09-27 | 2009-04-02 | Integrated Device Technology, Inc. | Serial Buffer Supporting Virtual Queue To Physical Memory Mapping |
| US20110145777A1 (en) * | 2009-12-15 | 2011-06-16 | Sundar Iyer | Intelligent memory system compiler |
| US20110302376A1 (en) * | 2010-06-04 | 2011-12-08 | Lsi Corporation | Two-port memory capable of simultaneous read and write |
| CN102436427A (en) * | 2011-11-07 | 2012-05-02 | 华为技术有限公司 | Data read-write method and storage device |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104333674B (en) * | 2014-11-24 | 2019-01-22 | 广东中星电子有限公司 | A kind of video image stabilization method and device |
| CN104333674A (en) * | 2014-11-24 | 2015-02-04 | 广东中星电子有限公司 | Video stabilization method and video stabilization device |
| CN106095328A (en) * | 2015-04-29 | 2016-11-09 | 马维尔以色列(M.I.S.L.)有限公司 | Each cycle has a read port and the multi-bank memory of one or more write port |
| US11099746B2 (en) | 2015-04-29 | 2021-08-24 | Marvell Israel (M.I.S.L) Ltd. | Multi-bank memory with one read port and one or more write ports per cycle |
| CN106095328B (en) * | 2015-04-29 | 2021-02-26 | 马维尔以色列(M.I.S.L.)有限公司 | Multi-bank memory having one read port and one or more write ports per cycle |
| CN106126112A (en) * | 2015-05-07 | 2016-11-16 | 马维尔以色列(M.I.S.L.)有限公司 | Each cycle has multiple read port and a plurality of memorizer of multiple write port |
| CN106126112B (en) * | 2015-05-07 | 2020-08-18 | 马维尔以色列(M.I.S.L.)有限公司 | Multiple stripe memory with multiple read ports and multiple write ports per cycle |
| CN107526534A (en) * | 2016-06-21 | 2017-12-29 | 伊姆西公司 | The method and apparatus for managing the input and output (I/O) of storage device |
| CN107545914A (en) * | 2016-06-27 | 2018-01-05 | 阿尔特拉公司 | Method and apparatus for smart memory interface |
| CN107545914B (en) * | 2016-06-27 | 2023-07-25 | 太浩研究有限公司 | Method and apparatus for intelligent memory interface |
| WO2018148918A1 (en) * | 2017-02-17 | 2018-08-23 | 深圳市大疆创新科技有限公司 | Storage apparatus, chip, and control method for storage apparatus |
| CN108984148A (en) * | 2018-06-13 | 2018-12-11 | 浙江大华技术股份有限公司 | A kind of method and memory of the data storage based on synchronization fifo memory |
| CN108984148B (en) * | 2018-06-13 | 2020-11-06 | 浙江芯昇电子技术有限公司 | Data storage method based on synchronous FIFO memory and memory |
| CN110704369A (en) * | 2019-10-09 | 2020-01-17 | 盛科网络（苏州）有限公司 | Memory and control method thereof |
| CN110704369B (en) * | 2019-10-09 | 2023-06-06 | 苏州盛科通信股份有限公司 | Memory and control method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103455281B (en) | 2018-01-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103455281A (en) | Two-port storage realized by single-port storage blocks | |
| US11061663B2 (en) | Memory devices, systems, and methods for updating firmware with single memory device | |
| US7447870B2 (en) | Device for identifying data characteristics for flash memory | |
| US9158683B2 (en) | Multiport memory emulation using single-port memory devices | |
| CN100545940C (en) | The access of control store and the system and method that refreshes | |
| CN109582214B (en) | Data access method and computer system | |
| US20140297921A1 (en) | Method of Partitioning Physical Block and Memory System Thereof | |
| US9594675B2 (en) | Virtualization of chip enables | |
| CN109952565B (en) | Memory access techniques | |
| CN110647475B (en) | Storage device and storage system including the same | |
| CN102024490B (en) | Pseudo-static memory, and reading operation and refreshing operation control method thereof | |
| US11537389B2 (en) | Memory devices, systems, and methods for updating firmware with single memory device | |
| CN116149554B (en) | RISC-V and extended instruction based data storage processing system and method thereof | |
| CN102024492A (en) | Pseudo-static memory and method for controlling write operation and refresh operation of pseudo-static memory | |
| CN102156676B (en) | Cache system | |
| CN109710547B (en) | Buffer memory management design and implementation method in industrial Internet of things | |
| CN102023845A (en) | Cache concurrent access management method based on state machine | |
| CN105404591B (en) | Processor system and its memory control methods | |
| CN108763106B (en) | Cache implementation method based on cross storage | |
| US8671262B2 (en) | Single-port memory with addresses having a first portion identifying a first memory block and a second portion identifying a same rank in first, second, third, and fourth memory blocks | |
| EP2767980B1 (en) | Two-port memory implemented with single-port memory blocks | |
| CN103514953B (en) | There is address RAM simulation electrically -erasable memory to the data stored in a flash memory | |
| CN103678159B (en) | Data storage device and data write-in method thereof | |
| CN106469020B (en) | Cache element and control method and its application system | |
| CN110362509A (en) | Unified address conversion and unified address space |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20181031 Address after: Singapore Singapore Patentee after: Annwa high tech Limited by Share Ltd Address before: American California Patentee before: Brocade Communications Systems, Inc. |