CN103427973B - Based on outer loop feedback formula symbol synchronization method - Google Patents

Abstract

The present invention is based on outer loop feedback formula symbol synchronization method, belongs to digital communication technology field.It is characterized by: first judged whether that signal arrives, when having signal to arrive, carry out Timing error estimate; Carry out the symbol decision of error amount according to matched filter output signal, determine to adjust step value simultaneously.False sync probability can be reduced like this, and can direct alignment error value in the seizure stage, so capture velocity is fast.Finally, dagital clock signal is transformed into square and feeds back to sampling clock control module by the present invention, can control sampling instant more accurately.Structure of the present invention is simple, and method implementation complexity is low, and synchronization catch is fast and follow the tracks of the features such as stable.

Description

Based on outer loop feedback formula symbol synchronization method

Technical field the present invention relates to a kind of digital demodulation Timing Synchronization implementation method, belongs to digital communication technology field.

Background technology digital communication system has some analogue systems a little incomparable.Such as: transmission capacity is large; Antijamming capability is strong; Be beneficial to information encryption; The equipment of being easy to realizes the integrated etc. of micro-, miniaturized and module.So the digitlization of communication system is the target that people pursue always.Meanwhile, digital communication system has again oneself special technical requirement.Digital receiver, when receiving digital signals, in order to adjudicate receiving symbol adjudicating the moment accurately, and to the correct integration of reception chip energies, must must know the accurate start/stop time of receiving symbol.When with matched filter or correlator receiving symbol, if be sampled state generation saltus step between adjacent code element, integrating range is shorter than element duration, then the chip energies E of integration _bobviously less than actual value, and the noise power spectral density of white Gaussian noise is unaffected.So whether accurate symbol synchronization is directly affect snr of received signal E _b/ N ₀size, a good symbol synchronization method just seems most important for a digital communication system.

The development of large scale integrated circuit, make in the engineer applied of reality, increasing system using DSP (DigitalSignalProcessing), FPGA (Field-ProgrammableGateArray) and CPU (CentralProcessingUnit) chip as realizing hardware platform.Functional realiey complexity becomes one of key restriction factors of high performance method realization, and the computational resource provided due to chip is limited, so the work of high-performance symbol synchronization method just seems particularly important under finding low complex degree.

Summary of the invention is for the defect described in background technology and deficiency; the present invention proposes a kind of based on outer loop feedback formula symbol synchronization method; the method is a kind of numerical model analysis structure, has that implementation complexity is low, synchronization catch is fast, synchronization accuracy advantages of higher, decreases the error rate.

The invention is characterized in that the method comprises three signal transacting steps, input and Timing error estimate, error transfer factor module and synchronizing signal digital-to-analogue conversion.Described process has following steps successively:

A: whether receiver detection signal has signal to arrive, calculates the time error between current interpolation valuation point and optimal sample point;

Steps A l: transmitting terminal signal, after receiving terminal matched filter, outputs signal as X _sk () (now signal is the complex signal with real part and imaginary part), obtains signal X after carrying out delivery square operation to output signal _m(k), that is: X _m(k)=| X _s(k) | ².

Steps A 2: carry out periodicity accumulating operation to steps A 1 output signal, preset accumulation period length is that L, sample rate N get 4,8 or 16 etc., that is: adder output signal is

Steps A 3: according to preset decision threshold γ (γ is preset signals range value), exports instruction control signal.E _lsignal is had, control signal set during >=γ; E _lno signal during < γ, control signal resets; Accumulation period length L value and choosing of decision threshold γ value are keys, and the long meeting of L makes data delay excessive, and L is too short, returns increase False Rate.

Steps A 4: if steps A 3 exports set control signal, then steps A 1 is outputed signal X _mk () carries out low-pass digital filter, getting number of sampling points is 4, and namely filter function is this step outputs signal $X\left(m\right)=X_M\left(k\right){\mathrm{\&Sigma;}}_{4\mathrm{mL}}^{4(m+1)L-1}{X}_M\left(k\right)e^{-\mathrm{j\&pi;k}/2};$

If steps A 3 exports reseting controling signal, then turn back to steps A 3;

Steps A 5: data X (m) is exported to steps A 4 and gets argument computing, obtain sequence of symhols phase information.That is: this phase information is taken as Timing error estimate value ê (m);

B: input data X according in steps A 1 _sk () and error estimate ê (m) calculate digital controlled oscillator (NCO:numericalcontrolledoscillator, hereinafter referred to as NCO) control signal;

Step B1: input signal X in receiving step A1 _sk (), preset signal amplitude thresholding β, works as X _sk () amplitude is greater than β, definition respective symbol value q (m)=1; Work as X _sk () amplitude is less than β, definition respective symbol value q (m)=-1;

Step B2: according to step B1 symbol decision result q (m) value, determines error transfer factor direction.According to steps A 4 Output rusults X (m) signal, determine to adjust step-length with comparing of error amount ê (m).Concrete: according to sample rate

When ê (m) < X (m) error transfer factor minimum step, then adjusted value is decided to be minimum adjustment step-length;

When ê (m) > X (m) error transfer factor minimum step, then adjusted value is decided to be ê (m);

Step B3: by step B2 medial error adjusted value sequence, through smothing filtering, generates control signal c (m);

Step B4: export control signal according to step B3, adjustment NCO exports digital dock information clk;

C: by NCO output digit signals clk, finally convert square wave to, more precisely controls Received signal strength sampling instant;

Step C1: NCO output digit signals in step B4 is generated sinusoidal wave through digital to analog converter (DAC:digital-to-analogconverter, hereinafter referred to as DAC);

Step C2: converted through comparator by the sine wave generated in step C1 is that sine wave is transformed into square wave;

Step C3: square-wave signal in step C2 is fed back to sampling control module;

The present invention propose based on outer loop feedback formula symbol synchronization method, there are following several advantages:

1, Parameter adjustable, under different environmental requirements, can change sample rate etc. easily;

2, structure is simple, and amount of calculation is less, is easy to use the chips such as FPGA to realize;

3, owing to directly revising error according to estimate of error, synchronously catch rapidly, synchronized tracking stablizes;

4, synchronization accuracy is high, reduces reception error rates of data;

5, better effects can be obtained under continuous mode and burst mode;

Accompanying drawing explanation

Fig. 1 is symbol synchronization Method And Principle figure

Fig. 2 is Data Detection schematic diagram

Fig. 3 is Timing error estimate schematic diagram

Fig. 4 is-symbol judges control signal transfer principle figure

Fig. 5 is digital-to-analogue conversion schematic diagram

Fig. 6 is that symbol synchronization method realizes schematic diagram

Embodiment

The quick symbol synchronization that can realize Received signal strength in digital receiver based on outer loop feedback formula symbol synchronization method that the present invention proposes.It realizes schematic diagram as shown in Figure 1, when a signal has been detected, first carries out Timing error estimate to signal, then judges adjusted value symbol according to Received signal strength waveforms amplitude situation.Relatively evaluated error value and minimum adjustment step size, choose adjusted value.Finally, export dagital clock signal through NCO and convert analog square wave signal to, feedback signal acquisition control module.Owing to being directly adjust synchronizing information according to error estimate, catching synchronizing information in this way fast, particularly under burst communication pattern, there is better performance.The theory diagram of its function specific implementation as indicated with 6.

As shown in Figure 2, transmitting terminal signal, after receiving terminal matched filter, outputs signal as X input principle of the present invention _sk () (now signal is the complex signal with real part and imaginary part), obtains signal X after carrying out delivery square operation to output signal _m(k), that is: X _m(k)=| X _s(k) | ².Preset accumulation period length is that L, sample rate N get 4,8 or 16 etc., uses adder output signal to be according to preset decision threshold γ, export instruction control signal.E _lsignal is had, control signal set during >=γ; E _lno signal during < γ, control signal resets;

Estimation error principle of the present invention as shown in Figure 3, after carrying out delivery square operation, obtains signal X to signal _m(k).Low-pass filtering computing is carried out to signal, then phase bit arithmetic is asked to number sequence sequence, can error estimate ê (m) be obtained.The concrete grammar of filtering can pass through realize.

Symbol decision control signal transfer principle of the present invention as shown in Figure 4, according to input signal X _sk (), preset signal amplitude thresholding β, works as X _sk () amplitude is greater than β, definition respective symbol value q (m)=1; Work as X _sk () amplitude is less than β, definition respective symbol value q (m)=-1; Design a symbol mechanism here, just effectively can reduce the probability of the locking that makes a mistake.Accurately can determine adjustment direction according to its sign, according to X (m) signal, determine to adjust step-length with comparing of error amount ê (m).Concrete: according to sample rate

When ê (m) < X (m) error transfer factor minimum step, then adjusted value is decided to be minimum adjustment step-length;

When ê (m) > X (m) error transfer factor minimum step, then adjusted value is decided to be ê (m);

Determine adjustment direction and adjustment amount, just can determine control signal c (m), control NCO exports respective digital clock signal.

As shown in Figure 5, the dagital clock signal clk that NCO exports mainly is transformed into controlling party waveshape and feeds back to sampling clock control module digital-to-analogue conversion principle of the present invention by this part.By rising edge or the trailing edge of square wave, sampling point position can be regulated more accurately.Main implementation procedure divides two steps, and first is by DAC sine wave output; Second is, by a comparator, sine wave is transformed into square wave.

Claims (1)

1., based on a symbol synchronization method for external feedback, it is characterized in that the method comprises input and estimation error module, error transfer factor module and D/A converter module, there are following steps:

A: whether receiver detection signal has signal to arrive, calculates the time error between current interpolation valuation point and optimal sample point;

Steps A 1: transmitting terminal signal, after receiving terminal matched filter, outputs signal as X _sk (), now signal is the complex signal with real part and imaginary part, obtains signal X after carrying out delivery square operation to output signal _m(k), that is: X _m(k)=| X _s(k) | ²;

Steps A 2: carry out periodicity accumulating operation to steps A 1 output signal, preset accumulation period length is that L, sample rate N get 4,8 or 16, that is: adder output signal is

Steps A 3: according to preset decision threshold γ, exports instruction control signal, E _lsignal is had, control signal set during >=γ; E _lno signal during < γ, control signal resets; Accumulation period length L value and choosing of decision threshold γ value are keys, and the long meeting of L makes data delay excessive, and L is too short, can increase False Rate;

Steps A 4: if steps A 3 exports set control signal, then steps A 1 is outputed signal X _mk () carries out low-pass digital filter, getting number of sampling points is 4, and namely filter function is this step outputs signal $X\left(m\right)=X_M\left(k\right){\&Sigma;}_{4mL}^{4(m+1)L-1}{X}_M\left(k\right)e^{-j\mathrm{\&pi;}k/2};$

If steps A 3 exports reseting controling signal, then turn back to steps A 3;

Steps A 5: data X (m) is exported to steps A 4 and gets argument computing, obtain sequence of symhols phase information, that is: this phase information is taken as Timing error estimate value

B: input data X according in steps A 1 _s(k) and error estimate calculate NCO control signal;

Step B1: input signal X in receiving step A1 _sk (), preset signal amplitude thresholding β, works as X _sk () amplitude is greater than β, definition respective symbol value q (m)=1; Work as X _sk () amplitude is less than β, definition respective symbol value q (m)=-1;

Step B2: according to step B1 symbol decision result q (m) value, determines error transfer factor direction, according to steps A 4 Output rusults X (m) signal, with error amount relatively determine adjust step-length, concrete: according to sample rate

When error transfer factor minimum step, then adjusted value is decided to be minimum adjustment step-length;

When error transfer factor minimum step, then adjusted value is decided to be

Step B3: by step B2 medial error adjusted value sequence, through smothing filtering, generates control signal c (m);

Step B4: export control signal according to step B3, adjustment NCO exports digital dock information clk;

C: by NCO output digit signals, finally convert square wave to, more precisely controls Received signal strength sampling instant;

Step C1: by NCO output digit signals in step B4 through DAC, generates sinusoidal wave;

Step C2: converted through comparator by the sine wave generated in step C1, makes sine wave be transformed into square wave;

Step C3: square-wave signal in step C2 is fed back to sampling control module.