Summary of the invention
The embodiment of the present invention provides a kind of multimode Veterbi decoding device and coding/decoding method thereof, with the simple stack-up issue of the decoding algorithm that solves the different systems encoder.
The embodiment of the present invention provides a kind of multimode Veterbi decoding device, and this device comprises:
The input data memory module, store the data to be decoded of outside input, and read data to be decoded according to the decoding instruction received for the mode that adopts the table tennis storage;
The branch path metric module, for to described input data memory module, sending described decoding instruction, and receive described data to be decoded; And, according to different code check indications, the State-output value of described data to be decoded and encoder is carried out to related operation, obtain the branch path metric value;
Mode selection module, for according to different systems, the State-output value of different constraint degrees and different coding device, select the branch path metric of various combination to send into parallel adding than modeling piece;
Described parallel adding than modeling piece, be used for according to state transition diagram, by the metric of corresponding states and the parallel accumulation calculating of branch path metric value, obtain accumulated value, and the new metric using maximum accumulated value as NextState, send the survivor path selection result to the survivor path memory module, until described ED to be decoded;
Described survivor path memory module, for preserving all survivor path selection results;
Recall module, for the recall mode different according to different coding mode selection, the described survivor path selection result of preserving according to described survivor path memory module, start to recall from free position or the maximum corresponding state of accumulated value, obtains decoded result;
Time-sequence control module, for to described branch path metric module, described mode selection module, describedly parallelly add than modeling piece, described survivor path memory module and describedly recall module control signal is provided, so that each module operates in the mode of streamline, described control signal comprises enable signal, inhibit signal and count signal.
Preferably, described device also comprises:
Anti-spilled module, for described parallel add obtain described accumulated value than modeling piece after, when the highest order of accumulated value significance bit corresponding to 0 state is 1, according to the enable signal from described time-sequence control module, the inferior high position of the accumulated value significance bit of all acquisitions is subtracted to 1, obtain new accumulated value and as the result of this accumulation calculating.
Preferably, described different coded system comprises and stings tail convolutional encoding and the non-tail convolutional encoding of stinging; Described sting the tail convolutional encoding corresponding recall mode for once recalling, the code length that traceback depth is twice; The described non-mode of recalling corresponding to tail convolutional encoding of stinging recalled for sliding window, and the overlap length (overlap) that described sliding window is recalled, window length and effective number of bits are arranged according to performance requirement.
Preferably, described different systems comprises Long Term Evolution (LTE), TD SDMA (TD-SCDMA), Wideband Code Division Multiple Access (WCDMA) (WCDMA) and code division multiple access (CDMA) 2000 standards.
Preferably, when described different systems comprises TD-SCDMA, WCDMA and CDMA2000 standard, describedly recall the difference of module according to code block length, selectedly recall mode and recall for once recalling with sliding window the mode combined.
Preferably, described parallel adding than modeling piece, comprise:
The accumulation calculating unit, for according to state transition diagram, the metric of multidiameter delay accumulation calculating corresponding states and branch path metric value, obtain accumulated value;
Selected cell, for according to adding than selecting rule, select the new metric of maximum accumulated value as NextState, and send selection result to described survivor path memory module, until ED to be decoded;
Judging unit, for when accumulative frequency, being less than preset accumulative frequency, return to the accumulation calculating next time of carrying out described accumulation calculating unit; When described accumulative frequency is more than or equal to preset accumulative frequency, finish accumulation calculating.
The embodiment of the present invention also provides a kind of coding/decoding method of multimode Veterbi decoding device, and the method comprises:
The mode that adopts table tennis to store is stored the data to be decoded of input;
According to different code check indications, the State-output value of described data to be decoded and encoder is carried out to related operation, obtain the branch path metric value;
According to different systems, the State-output value of different constraint degrees and different coding device, the branch path metric of selection various combination;
According to state transition diagram, by the metric of corresponding states and the parallel accumulation calculating of branch path metric value, obtain accumulated value, and the new metric using maximum accumulated value as NextState, record all survivor path selection results, until described ED to be decoded;
Differently according to different coding mode selection recall mode, according to the described survivor path selection result of record, start to recall from free position or the maximum corresponding state of accumulated value, obtain decoded result.
Preferably, after described acquisition accumulated value, described method also comprises:
When the highest order of accumulated value significance bit corresponding to 0 state is 1, the inferior high position of the accumulated value significance bit of all acquisitions is subtracted to 1, obtain new accumulated value and as the result of this accumulation calculating.
Preferably, described different coded system comprises and stings tail convolutional encoding and the non-tail convolutional encoding of stinging; Described sting the tail convolutional encoding corresponding recall mode for once recalling, the code length that traceback depth is twice; The described non-mode of recalling corresponding to tail convolutional encoding of stinging recalled for sliding window, and the overlap length (overlap) that described sliding window is recalled, window length and effective number of bits are arranged according to the performance simulation of algorithm.
Preferably, described different systems comprises Long Term Evolution (LTE), TD SDMA (TD-SCDMA), Wideband Code Division Multiple Access (WCDMA) (WCDMA) and code division multiple access (CDMA) 2000 standards.
Preferably, described the recall mode different according to different coding mode selection comprises:
When described different systems comprises TD-SCDMA, WCDMA and CDMA2000 standard, according to the difference of code block length, select once to recall with sliding window and recall the mode combined.
The present invention is under TD-SCDMA/WCDMA and CDMA 2000 patterns, maximally utilised the parallel computation acs unit way under the LTE pattern, share ample resources, optimal design, improved the decoding throughput, the throughput of LTE pattern reaches 50Mbps, and the throughput of TD-SCDMA/WCDMA pattern reaches 10Mbps, decoding latency is also only the us level, applicable to the high-speed coding system.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, hereinafter in connection with accompanying drawing, embodiments of the invention are elaborated.It should be noted that, in the situation that do not conflict, the embodiment in the application and the feature in embodiment be combination in any mutually.
As shown in Figure 1a, it is the structural representation of multimode Veterbi decoding device of the present invention, it comprises input data memory module (input_buffer) 11, branch path metric module (dis_gen_v2) 12, mode selection module (mode_dis_select) 13, parallelly adds than modeling piece (parallel_add_com_sel) 14, survivor path memory module (route_ram) 15, recalls module (trace_back) 16 and time-sequence control module (viterbi_state_contrl) 17, wherein:
The input data memory module, store the data to be decoded of outside input, and read data to be decoded according to the decoding instruction received for the mode that adopts the table tennis storage;
The branch path metric module, for to described input data memory module, sending described decoding instruction, and receive described data to be decoded; And, according to different code check indications, the State-output value of described data to be decoded and encoder is carried out to related operation, obtain the branch path metric value;
Mode selection module, for according to different systems, the State-output value of different constraint degrees and different coding device, select the branch path metric of various combination to send into parallel adding than modeling piece;
Described parallel adding than modeling piece, be used for according to state transition diagram, by the metric of corresponding states and the parallel accumulation calculating of branch path metric value, obtain accumulated value, and the new metric using maximum accumulated value as NextState, send the survivor path selection result to the survivor path memory module, until described ED to be decoded;
Described survivor path memory module, for preserving all survivor path selection results;
Recall module, for the recall mode different according to different coding mode selection, the described survivor path selection result of preserving according to described survivor path memory module, start to recall from free position or the maximum corresponding state of accumulated value, obtains decoded result; Wherein, to the LTE standard, from any device, start to recall, start to recall from the corresponding state of maximum accumulated value for other patterns;
Time-sequence control module, for to described branch path metric module, described mode selection module, describedly parallelly add than modeling piece, described survivor path memory module and describedly recall module control signal is provided, so that each module operates in the mode of streamline, described control signal comprises enable signal, inhibit signal and count signal.
Wherein, this time-sequence control module provides enable signal for each module, and enable signal is effective, each module work, otherwise do not work.Corresponding certain module also needs to provide inhibit signal and count signal to coordinate on function, completes corresponding function.Time-sequence control module is that various control signals are gathered and have been placed on together.
In addition, this device can also comprise: anti-spilled module 18, for described parallel add obtain described accumulated value than modeling piece after, when the highest order of accumulated value significance bit corresponding to 0 state is 1, according to the enable signal from described time-sequence control module, the inferior high position of the accumulated value significance bit of all acquisitions is subtracted to 1, obtain new accumulated value and as the result of this accumulation calculating.
Wherein, described different coded system comprises and stings tail convolutional encoding and the non-tail convolutional encoding of stinging; Described sting the tail convolutional encoding corresponding recall mode for once recalling, the code length that traceback depth is twice; The described non-mode of recalling corresponding to tail convolutional encoding of stinging recalled for sliding window, and the overlap that described sliding window is recalled, window length and effective number of bits are determined by algorithm simulating.Described different systems comprises Long Term Evolution (LTE), TD SDMA (TD-SCDMA), Wideband Code Division Multiple Access (WCDMA) (WCDMA) and code division multiple access (CDMA) 2000 standards.
When described different systems comprises TD-SCDMA, WCDMA and CDMA2000 standard, describedly recall the difference of module according to code block length, selectedly recall mode and recall for once recalling with sliding window the mode combined.
Further, described parallel adding than modeling piece, comprise accumulation calculating unit 141, selected cell 142 and judging unit 143, as shown in Figure 1 b, and wherein:
The accumulation calculating unit, for according to state transition diagram, the metric of multidiameter delay accumulation calculating corresponding states and branch path metric value, obtain accumulated value;
Selected cell, for according to adding than selecting rule, select the new metric of maximum accumulated value as NextState, and send selection result to described survivor path memory module, until ED to be decoded;
Judging unit, for when accumulative frequency, being less than preset accumulative frequency, return to the accumulation calculating next time of carrying out described accumulation calculating unit; When described accumulative frequency is more than or equal to preset accumulative frequency, finish accumulation calculating.
As shown in Figure 2, be the flow chart of the coding/decoding method embodiment of multimode Veterbi decoding device of the present invention, the present embodiment Veterbi decoding flow process comprises the following steps:
Step S201, the mode that adopts table tennis to store are stored the data to be decoded of outside input;
At first judging that whether two table tennis memories are in idle condition, is to allow new data to be decoded to write the table tennis memory; Otherwise forbid that new data to be decoded write.When data to be decoded write a memory, allow to read data to be decoded from another memory.For example, for the first time, by the input data buffer storage to memory SA, while having for the second time data, by signal, switch, by the input data flow cache to memory SB, if the while receive outside decoding instruction, can be by the data reading of memory SA.For the third time when input store is idle, again by new input traffic buffer memory to memory SA, simultaneously again can be by the data reading of memory SB.So circulation, can realize the seamless buffering of data greatly having improved the parallel processing speed in later stage, while effectively having reduced decoding because etc. data to be stored and the processing delay brought.The maximum length code block length decision of the data to be encoded of memory depth herein in various standard agreement regulations, width is determined by sampling precision;
Step S202, calculate to receive code word and branch path metric value with reference to code word;
Receiving code word is data to be decoded, the State-output value that is encoder with reference to code word; The State-output value of encoder and data to be decoded are carried out to correlation computations, obtain the branch path metric value;
The present embodiment is mainly used in the decoding of error correcting code in the data mobile communication system, for example 3G (3rd-Generation, 3G (Third Generation) Moblie technology) and LTE project etc.Fig. 3 and Fig. 4 are respectively that the LTE standard adopts stings the common convolution coder that tail convolution coder and TD-SCDMA standard adopt, below we only take these two kinds of standard resource-sharings and are described in detail as example, other standard principle of multiplexing are similar;
With reference to Fig. 3, be in the LTE standard, provide sting the tail convolution coder, have 6 shifting memories, before starting coding, the initial value of 6 shift registers of encoder is made as rear 6 bits of data to be encoded.This encoder constraint degree is 7, and code check is 1/3, therefore has 2 in computational process each time
6=64 states.According to the regulation of LTE agreement, the result of code block segmentation, the maximum input data volume of convolution coder first encoding is 80 bits;
With reference to Fig. 4 a and Fig. 4 b, in the TD-SCDMA agreement, convolution coder used is respectively 1/2 and 1/3 encoder by two code checks and forms, and has 8 shifting memories, and constraint length is all 9, therefore has 2 in computational process each time
8=256 states.Before starting coding, the initial value of 8 shift registers of encoder is made as full 0, and adds 8 bits 0 at the end of input bit.According to the regulation of 3G agreement, the result of code block segmentation, the maximum input data volume of convolution coder first encoding is 504 bits;
(be suitable for stinging tail convolutional encoding and conventional coders) simultaneously in the convolutional encoding process, at T constantly, can arrive S
2k, S
2k+1State have two for S
kAnd S
K+32(k=0~31) or S
K+128(k=0~127) these two states, S
2kCorresponding to being input as 0, S
2k+1Corresponding to being input as 1.S
kAnd S
K+32Or S
K+128Highest order correspond to respectively 0 and 1, i.e. encoding and decoding state transition diagram as shown in Figure 5.For example,, according to its encoding and decoding state transition diagram, by the known S of correlation computations
kTo S
2kAnd S
2k+1The branch path metric value be respectively 5 and 3, and S
K+32To S
2kAnd S
2k+1Branched measurement value be respectively 13 and 10;
Different structure according to the convolution coder of Fig. 3, Fig. 4 a, Fig. 4 b, all can change with reference to code word and code check accordingly, and this step is according to the difference of standard, selects different code checks and with reference to code word, thereby calculate corresponding branch path metric value;
Step S203, according to the relation between standard, coding multinomial and encoding state, the branch metric path is selected, send into to add than modeling piece and calculated;
Multimode system of the present invention is wanted maximum multiplexed resource, in order to meet the rate requirement of LTE pattern, improve data throughput, Viterbi decoder to add than modeling piece inside be full concurrent operation under the LTE pattern, it is entirely more parallel than selecting submodule that the shared basis of other patterns is exactly that LTE Xia De 32 tunnels add.Under the LTE pattern, constraint degree is different from TD-SCDMA, CDMA 2000, WCDMA, but it only has 64 different conditions, 32 tunnels entirely walk abreast and just can once calculate under a clk clock, therefore it is with after corresponding coding multinomial carries out necessary calculating and selects, and obtains sending giving walking abreast that to add than the branch path metric of selecting submodule be to immobilize.Also therefore, the branch metric Path selection under the LTE pattern calculates in advance, when fixing, selects to send to give to add than modeling piece, has saved a large amount of computational resources;
Under TD-SCDMA, CDMA 2000, WCDMA pattern, constraint degree is identical, though that coding multinomial and code check etc. exist is different, during calculating, can realize to a certain extent sharing.The index signal of corresponding standard and code check, when carrying out Viterbi decoding, can be sent in outside, and by code rate selection, we can bypass the 3rd group of branches path metric under 1/3 code check when 1/2 code check, or are set to 0, are defaulted as 1/3 code check; Adding while adding up than modeling piece, processing mode is similar, can realize sharing of different code checks; Under TD-SCDMA, CDMA 2000, WCDMA pattern, state has 2
8What=256 Ge, 32 tunnels were parallel adds than selecting submodule can't disposablely complete the calculating of all state measurements and path metric, and also therefore, branch path metric each time need to be carried out the algorithm of different modes and be selected.Coding multinomial and state also need to be selected according to standard and code check, especially calculate the necessary factors of How to choose branch path metric;
Step S204, according to state transition diagram, by the metric of corresponding states and the parallel accumulation calculating of branch path metric value, obtain accumulated value, and the new metric using maximum accumulated value as NextState, record all survivor path selection results, until ED to be decoded;
This step mainly completes in adding than modeling piece; Add and all can share multiplexingly than modeling piece for different systems, different is that its accumulative frequency will be at least 4*n clk (n is encoding block length) under TD-SCDMA, CDMA 2000, WCDMA pattern.According to state transition diagram, entirely parallel by 32 tunnels, accumulation calculating unit 141 is added up the metric of corresponding states and branch path metric value, and obtains accumulated value.For example, the T-1 moment, S
kMetric be 16, S
K+32Metric be 15, and S
kTo S
2kAnd S
2k+1The branch path metric value be respectively 5 and 3, and S
K+32To S
2kAnd S
2k+1Branched measurement value be respectively 13 and 10, known by metric and the branch path metric value of cumulative corresponding states, arrive S
2kThe path accumulated value be respectively 26+5=31 and 15+13=28, arrive S
2k+1The path accumulated value be respectively 26+3=29 and 15+10=25.142 bases of selected cell add than selecting rule, select the new metric of maximum accumulated value as NextState.Select maximum path accumulated value 31 as S
2kNew metric, select maximum path accumulated value 29 as S
2k+1New metric.Simultaneously, the survivor path memory module will be preserved each time the path metric value of selecting, until judging unit 143 judgement accumulative frequencies while being more than or equal to preset accumulative frequency, just finish the accumulation calculating of accumulation calculating unit 141;
Adding than choosing is the process of a continuous iteration, and the iterations under the LTE pattern is determined by outside decoding iterations max_times.When meeting specified conditions, judge whether inner loop counting max_cnt equals max_times, if equate, stops iteration, and by cycle counter max_cnt clear 0; Otherwise again start iteration.Iterations is larger in theory, and the performance of decoder is better, yet finds through emulation, when iterations more than 4 circles, the performance increase of decoder is very little, and the resource consumption simultaneously brought increases greatly, and therefore iterations max_times value of the present invention is preferably between 2~4.Do and once add than selecting iteration can meet performance requirement for the whole encoding block of other standards;
The embodiment of the present invention is under TD-SCDMA/WCDMA and CDMA 2000 patterns, utilized to greatest extent the parallel computation acs unit way under the LTE pattern, share ample resources, optimal design, improved the decoding throughput, the throughput of LTE pattern reaches 50Mbps, and the throughput of TD-SCDMA/WCDMA pattern reaches 10Mbps, decoding latency is also only the us level, applicable to the high-speed coding system.
When calculating cumulative metrology path, the survivor path selection result need to be kept to survivor memory unit, recall module for follow-up; Add than selecting submodule according to 32 tunnels are parallel, under the LTE pattern, once can preserve all survivor path selection results, the single port random asccess memory (ram) that selected depth and width are 256*64bit gets final product; And TD-SCDMA, CDMA 2000, WCDMA pattern are according to the single port ram of width 64bit, complete the survivor path that once calculates 256 states and at least need 4 clk (256=64*4), the degree of depth of survivor memory unit and width are at least (4*n_max) * 64bit (n_max>64bit, the maximum length that n_max is encoding block);
Step S205, after the accumulation calculating path metric value, when the highest order of cumulative metric significance bit corresponding to 0 state is 1, the inferior high position of the accumulated value significance bit of all acquisitions is subtracted to 1, obtain new accumulated value and as the result of this accumulation calculating, this step is carried out in anti-spilled module, is optional step;
At first will judge highest order (if the signed number of the significance bit of the corresponding cumulative path metric value of 0 state, significance bit refers to the data bit except sign bit) whether be 1, be the inferior high position of the accumulated value significance bit of all acquisitions to be subtracted to 1, be about to whole metric and carry out simple normalization to null value.For example, the accumulative total path metric value of 14bit of take is example, as distance0[12] while being zero, normal running, the subtraction enable signal sub_en of generation is low level; As distance0[12] while being 1, the subtraction enable signal sub_en of generation is high level, all survivor paths is deducted to 0x800 (16 system), time high position of distance0 significance bit, just can effectively prevent overflowing of cumulative metrics value.
Traditional anti-spilled step is mainly in the selection of fixed value, need more all path metric values and get its minimum value as fixed value, and the anti-spilled step of the present embodiment can be saved a pile compare selection circuit and subtraction circuit is very simple, because it is only subtracted 1 operation for the Senior Three position of cumulative metrics value.
Step S206, from the survivor path memory module, read the survivor path selection result, and, according to state measurement, recall the output decode results.
Under the LTE pattern, coded system, for stinging the tail convolutional encoding, is recalled and can be regarded the decoded mode of turn-taking as, and the state after recalling is once got back to again initial state.The length of its encoding block is generally also all shorter, is less than 100bit, adopts 32 tunnels parallel according to noted earlier adding than modeling piece, and the survivor path tolerance ram of storage can be very not large, once recalls output and can obtain decoded result.But, the code length that under LTE, its traceback depth is 2 times, i.e. 2*n.Abandon the retrieve data of first times of degree of depth when the output data, only use the retrieve data of second times of degree of depth, second times recall to take first times recall as basis, therefore need the survivor path selection result (this is also that the survivor path memory module degree of depth noted earlier is 256, rather than 128 reason) of storage twice.Adopt the traceback depth of twice code length, while because of the high-speed decoding system, with tail-biting convolutional code, replacing common convolution code, constraint degree has reduced, after emulation, its code length of comparing one times of discovery is recalled, the performance of decoder has improved 0.2db~0.3db, so the present invention's traceback depth under the LTE pattern adopts the code length of twice to guarantee the performance of system.And its control is simpler, realizes more convenient.
Under TD-SCDMA/WCDMA and CDMA 2000 patterns, because the constraint degree of coding is long, therefore need not adopt the code length of twice to improve performance as traceback depth.Under this several modes, we take once to recall with sliding window and recall the mode of combination, once recall in code block (below 256bit) employing more in short-term, when code block length is greater than the bit number (such as 256bit) of setting, the method that adopts sliding window to recall can be set.Once recall performance higher, yet in the situation that code block length is long, if will once recall, just need more memory space, such as code block length is 512bit, under the TD-SCDMA pattern, the survivor memory unit degree of depth and the bit wide that need are at least 2048*64bit, in this case, if adopt the mode of sliding window, can save ample resources, such as code block length is still 512 bits, window length is 120 bits, overlap selects 32bit, store survivor path unit depth and bit wide for ((120+32) * 4) * 64bit, even code block length is long again, the storage survivor path cell size of sliding window mode still can remain unchanged.(annotate: the size here only just for example, does not have the performance reference value).Why the present invention adopts two kinds to recall mode, exactly in order to utilize both advantages under the guaranteed performance prerequisite.Wherein, slide window length, effective number of bits, overlap length (overlap) length that window recalls and can, according to the performance simulation of algorithm, carry out corresponding outer setting under different condition.
One of ordinary skill in the art will appreciate that all or part of step in said method can come the instruction related hardware to complete by program, said procedure can be stored in computer-readable recording medium, as read-only memory, disk or CD etc.Alternatively, all or part of step of above-described embodiment also can realize with one or more integrated circuits.Correspondingly, each the module/unit in above-described embodiment can adopt the form of hardware to realize, also can adopt the form of software function module to realize.The present invention is not restricted to the combination of the hardware and software of any particular form.
Above embodiment is only unrestricted in order to technical scheme of the present invention to be described, only with reference to preferred embodiment, the present invention is had been described in detail.Those of ordinary skill in the art should be appreciated that and can modify or be equal to replacement technical scheme of the present invention, and do not break away from the spirit and scope of technical solution of the present invention, all should be encompassed in the middle of claim scope of the present invention.