CN103426809A - Semiconductor manufacturing method based on self-aligned double-patterning technology - Google Patents
Semiconductor manufacturing method based on self-aligned double-patterning technology Download PDFInfo
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Abstract
The invention relates to a semiconductor manufacturing method based on the self-aligned double-patterning technology. The method comprises the steps that a mask layer containing silicon is formed above a low k material layer or an ultralow k material layer formed above a semiconductor substrate; a nonnitrogenous oxide mask layer is formed above the mask layer containing the silicon; a metal mask layer is formed above the nonnitrogenous oxide mask layer; an oxide mask layer is formed above metal mask layer; patterning is conducted on the oxide mask layer; nitrides are deposited on the patterned oxide mask layer and the metal mask layer, etching is conducted on the nitrides, and therefore, space walls are formed on the side walls of the oxide mask layer; a one-end-cutting step is conducted to remove the nitride space walls at the two ends of the oxide mask layer; monoxides are deposited to fill gaps between the nitride space walls; the nitride space walls are removed. The semiconductor manufacturing method based on the self-aligned double-patterning technology has the advantage that the selectivity of the oxides and the nitrides in the manufacturing process is improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly, the present invention relates to a kind of semiconductor making method based on the self-aligned double patterning case.
Background technology
Increase day by day for the semiconductor storage demand of high power capacity, the integration density of these semiconductor storages receives people's concern, in order to increase the integration density of semiconductor storage, available technology adopting many diverse ways, for example by reducing wafer size and/or change inner structure unit, form a plurality of memory cell on single wafer, for increase the method for integration density by changing cellular construction, attempted ditch and reduced cellar area by floor plan or the change cell layout that changes active area.
Nand flash memory is a kind of than the better storage scheme of hard disk drive, because nand flash memory be take page and is read and write data as unit, thus be suitable for storing continuous data, as picture, audio frequency or alternative document data; Because of the advantage that its cost is low, capacity is large and writing speed is fast, the erasing time is short, in the field of storage of device for mobile communication and portable multimedia device, be widely used simultaneously.At present, in order to improve the capacity of nand flash memory, need in preparation process, improve the integration density of nand flash memory.
In preparing the nand flash memory process, spacer patterns technology (Spacer patterning technology, SPT) and self-aligned double patterning case technology (self aligned double patterning, SaDPT) all can be used for preparing the transistor of nanoscale, while adopting described method to process semi-conductive wafer, usually use known patterning and etch process to form the feature of semiconductor device in wafer, in these photoetching processes, the photoresist deposition of material is on wafer, then be exposed to the light filtered through reticule, after reticule, this light contacts the surface of this photoresist material, thereby this light changes the part that the chemical composition developing machine of this photoresist material can be removed this photoresist material, obtain needed pattern, as shown in Fig. 1 a-1e, adopt at present the process of self-aligned double patterning case legal system manufacturing semiconductor device to be:
At first, form SiN mask layer 104 on Semiconductor substrate 102, form oxide mask layer 106 above SiN mask layer 104, form polycrystalline silicon mask layer 108 on oxide mask layer 106, form second layer SiN mask layer 110 on the mask layer 108 of this polysilicon, the last patterned mask layer 112 that forms above second layer SiN mask layer 110, obtain stacked;
Then this is stackedly carried out to etching, during etching, below second layer SiN mask layer 110, be polycrystalline silicon mask layer 108, therefore may be etched into this polycrystalline silicon mask layer 108 during etching, by the design transfer of patterned mask layer on second layer SiN mask layer 110 and described polycrystalline silicon mask layer 108, perhaps in this step first by design transfer to described SiN mask layer 110, then through SiN mask layer 110 by design transfer to polycrystalline silicon mask layer 108, no matter which kind of method can obtain pattern as shown in Figure 1 b, then remove this patterned mask layer 112, follow deposit spathic silicon mask layer 114 above second layer SiN mask layer 110, above second layer SiN mask layer 110 and on sidewall by described polycrystalline silicon mask layer 114 uniform folds, described polycrystalline silicon mask layer 114 is carried out to etching, form spaced walls on the sidewall of second layer SiN mask layer 110 and polycrystalline silicon mask layer 108, as shown in Fig. 1 c, remove the polycrystalline silicon mask layer 114 above second layer SiN mask layer 110, the sidewall that retains second layer SiN mask layer 110 and polycrystalline silicon mask layer 108, make the height of the height of the polysilicon layer that deposits on the SiN sidewall and SiN consistent, then the inter polysilicon next door that deposition oxide 116 forms with polymer in blank map 1c, obtain the pattern as shown in Fig. 1 d, finally remove the oxide 116 of described second layer SiN mask layer 110 and filling, obtain the pattern of polysilicon, as shown in Fig. 1 e.
But in the preparation method, between oxide mask layer 106 and second layer SiN mask layer 110, select polysilicon as mask layer at present, described polycrystalline silicon mask layer selection rate to oxide mask layer and SiN when etching is low, easily destroy this polycrystalline silicon mask layer during etching, make the pattern the off-design pattern that prepare, make whole semiconductor at rear end processing procedure (The back end ofline, BEOL) in, rate of finished products is low, therefore and when preparing the nand flash memory device of high storage density, in the semiconductor back-end processing procedure pattern lamination arrange very crucial, only have arranging of rational pattern lamination could improve selection rate and solve described problem.
Summary of the invention
For solve in the described rear end at semiconductor device processing procedure (BEOL) due to mask layer arrange reasonable not, to be located thereon or under the selection rate of mask layer low, cause the problem that semiconductor device yield is not high, the invention provides a kind of semiconductor making method based on the self-aligned double patterning case, described method comprises:
A kind of semiconductor making method based on the self-aligned double patterning case, described method comprises:
Form siliceous mask layer above the low-k materials formed above Semiconductor substrate or ultralow k material layer;
Form unazotized oxide mask layer above this siliceous mask layer;
Form the metal mask layer above this unazotized oxide mask layer;
Form the oxide mask layer above this metal mask layer;
The described oxide mask layer of patterning;
At described patterning the oxide mask layer and described metal mask layer on depositing nitride, then this nitride is carried out to etching, form spaced walls with the sidewall at described oxide mask layer;
Carry out an end-grain cutting step, to remove the nitride spacer at described oxide mask layer two ends;
The deposition monoxide, to fill the space between described nitride spacer;
Remove described nitride spacer.
As preferably, described metal mask layer is selected TiN, BN or Cu
3The N material.
As preferably, the described oxide mask layer of patterning comprises by monochromatic light and hindering or three layer pattern methods are carried out etched step.
As preferably, described end-grain cutting step comprises: deposit photoresist layer on described Semiconductor substrate, the described photoresist layer of patterning, to expose the nitride spacer at described oxide mask layer two ends, adopts dry etching to remove the described nitride spacer of exposing.
As preferably, deposit after the step of described oxide and also comprise described oxide is carried out to a cmp to expose the step of described nitride wall.
As preferably, remove described nitride spacer and select wet method or dry etching.
As preferably, described siliceous mask layer is SiC layer or SiN layer.
As preferably, described nitride is SiN.
As preferably, remove after described nitride spacer and also comprise and take described oxide as mask, the step of the described metal mask layer of dry etching.
The invention has the advantages that and select the metal mask layer in manufacture process below the mask layer of metal oxide; the selection rate of this metal mask layer to oxide and nitride while having improved etching; unazotized oxide below this layer is played to the effect of protection, improved the rate of finished products of product in the processing procedure of rear end.
The accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining device of the present invention and principle.In the accompanying drawings,
Fig. 1 a-e is the method for semiconductor device of manufacturing in prior art;
Fig. 2 is the process chart that the present invention is based on self-aligned double patterning case method;
Fig. 3 a-f the present invention is based on the method that the self-aligned double patterning case is manufactured semiconductor device.
Embodiment
Next, in connection with accompanying drawing, the present invention is more intactly described, shown in the drawings of embodiments of the invention.But the present invention can be with multi-form enforcement, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiment to expose thorough and complete, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, for size and the relative size of knowing the ，Ceng He district, may be exaggerated.Same reference numerals means identical element from start to finish.
Understand for convenient, the invention provides a kind of process chart of embodiment, as shown in Figure 2, the process schematic diagram of the manufacture method of the present invention provided in conjunction with Fig. 3 a-f is further explained simultaneously.
As shown in Fig. 2 and 3a, at first can on semi-conductive substrate, form low-K material or ultralow K material 202, form siliceous mask layer 204(step 102 above low-K material or ultralow K material 202), the top of this siliceous mask layer 204 can form unazotized oxide mask layer 206(step 104), then can form metal mask layer 208(step 106 above unazotized oxide mask layer 206), then above this metal mask layer 208, can form oxide skin(coating) 210(step 108), finally above described oxide mask layer 210, can form patterned mask layer 220(step 110), form thus mask stacked.
Wherein, described substrate is low-K material or ultralow K material, and those skilled in the art can be selected according to this instruction, are not limited to a certain material; Described siliceous mask layer 204 can be dielectric substance, as materials such as SiC, SiN, can form the hard mask of conductor when etching, as preferably, selects in the present invention SiC as this hard mask; Described unazotized oxide mask layer 206 is silica, can be also ZnO, CdO, TiO
2, Al
2O
3, SnO, Cu
2O, NiO, CoO, FeO, Cr
2O
3In a kind of; Described metal mask layer 208 is hard mask; this metal mask layer can improve the etching selection rate to top oxide mask layer 210 and following unazotized oxide mask layer 206; particularly; while carrying out design transfer only to 210 etching of oxide mask layer; this metal mask layer 208 can be not etched; to this layer and below each mask layer play a protective role; in addition, at this metal mask layer of etching, design transfer can not impacted following unazotized oxide mask layer 206 during to this metal mask layer 208 yet.Setting due to this metal mask layer, improved the selection rate be located thereon with its lower mask layer, guarantee the accuracy of design transfer, further improved the rate of finished products of product in the processing procedure of rear end, well solved the problem existed in current semiconductor back-end processing procedure.As long as can realize that the metal mask layer of described purpose all can be applied to the present invention, those skilled in the art can be selected metal level according to this minimum requirements, and as preferably, in the present invention, this metal level can be TiN, BN or Cu
3N, while selecting above-mentioned three kinds of materials, its better effects if, to being located thereon, under the selection rate of oxide mask layer higher, during etching, the accuracy of pattern is higher, and the integration density of the semiconductor device prepared is large, memory capacity is larger; Described oxide mask layer 210 is silica, can be also ZnO, CdO, TiO
2, Al
2O
3, SnO, Cu
2O, NiO, CoO, FeO or Cr
2O
3Deng, this oxide skin(coating) can be the same with not siliceous oxide skin(coating), also can be inconsistent, can contain the nitrogen element in this oxide mask layer 210; Described patterned mask layer can be the photoresist material, for example this mask can be 60nm photoresist material, wherein this patterned mask layer can be revised, the size at the interval for example formed between the patterned mask layer in Fig. 3 a can be adjusted as required, can be repaired by controlling the modes such as etching period.
As preferably, in specific embodiment, the lamination of described design transfer is followed successively by low K or ultralow K material, SiC, unazotized oxide, TiN, BN or Cu from lower to upper
3N, oxide, photoresist mask layer.
In a kind of embodiment of the present invention, can be at first by the stacked execution step 112 patterning oxide mask layers 210 of the mask prepared, concrete is: this is stackedly carried out to etching, and control etching condition, make the only described oxide mask layer 210 of etching of this process, by this design transfer to this oxidation mask layer 210, in order to improve the selection rate to this layer, metal level can be selected in the below of oxide layer in the present invention, as preferably, in this step, select monochromatic light resistance pattern or three layer pattern methods to carry out etching, be common method of the present invention at the resistance pattern of the monochromatic light described in this step or three layer pattern methods, those skilled in the art can be selected according to the needs of this step, do not repeat them here.
Then perform step 114, depositing nitride on oxide mask layer 210 and described metal mask layer 208, then this nitride is carried out to etching, form spaced walls with the sidewall at described oxide mask layer: particularly, at first remove patterned mask layer 220, obtain the pattern as shown in Fig. 3 b, described removal method can be selected known method, if for example described patterned mask layer 220 adopts the photoresist material, can select the oxygen ashing method to remove, by controlling described incineration condition to remove this patterned mask layer 220, and do not affect the pattern of described oxide layer, those skilled in the art can this minimum requirements select described method, be not limited only to ashing method.After removing this patterned mask layer 220, then depositing nitride on this oxide mask layer 210 and metal mask layer 208, as preferably, select in the present invention SiN to be deposited, form the mask layer 212 of nitride on this oxide mask layer 210 and metal mask layer 208, then this nitride mask layer 212 is carried out to etching, remove the nitride of oxide and metal level top, and retain the nitride of described oxide pattern two side, thereby form spaced walls as shown in Figure 3 d at the sidewall of described oxide mask layer.Selectable removal patterned mask described in step 114 and the method that is etched with the interval that forms nitride, all can adopt this area method commonly used, and the deposition of described nitride can be selected the CVD(chemical vapour deposition (CVD)) etc. method.
In step 114, on oxide mask layer 210 and metal mask layer 208, both the interval between oxide pattern all can have been filled during depositing nitride, obtain pattern as shown in Figure 3 c, can also on oxide mask layer 210 and metal mask layer 208, deposit uniformly, obtain pattern similar to that of Fig. 1 c, certainly also not only be confined in the present invention above-mentioned two kinds of patterns, as long as can on the oxide mask layer, form sidewall, the spaced walls that forms nitride after etching gets final product.
Then perform step 116 end-grain cutting, to remove the nitride spacer at described oxide mask layer two ends, described end-grain cutting is for to be excised the nitride at the two ends of described oxidation pattern, to expose described oxide, wherein the two ends of oxide pattern refer to two end points in the longitudinal direction, as preferably, can on described Semiconductor substrate, deposit photoresist layer, the described photoresist layer of patterning, to expose the nitride spacer at described oxide mask layer two ends, adopts dry etching to remove described nitride spacer.
Execution step 118, the deposition monoxide, to fill the space between described nitride spacer: deposition oxide 214 in the formed spaced walls of nitride mask layer, wherein, described oxide 214 is silica, also can select 206 oxide layer materials, as ZnO, CdO, TiO
2, Al
2O
3, SnO, Cu
2O, NiO, CoO, FeO or Cr
2O
3, also can select and this layer of different material, obtain pattern as shown in Figure 3 e, then carry out a chemical mechanical milling tech, to expose described nitride spacer.
Execution step 120, remove described nitride spacer, particularly, optionally removes described nitride spacer, obtains pattern of the present invention, as shown in Fig. 3 f, wherein removes described nitride spacer and select dry method or wet etching.
Remove after described nitride spacer and also comprise and take described oxide as mask, the step of the described metal mask layer of dry etching, as described in transferring to oxide pattern as described in will be as shown in Fig. 3 f in metal oxide layer.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the purpose for giving an example and illustrating just, but not is intended to the present invention is limited in described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to above-described embodiment, according to instruction of the present invention, can also make more kinds of variants and modifications, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (9)
1. the semiconductor making method based on the self-aligned double patterning case, described method comprises:
Form siliceous mask layer above the low-k materials formed above Semiconductor substrate or ultralow k material layer;
Form unazotized oxide mask layer above this siliceous mask layer;
Form the metal mask layer above this unazotized oxide mask layer;
Form the oxide mask layer above this metal mask layer;
The described oxide mask layer of patterning;
At described patterning the oxide mask layer and described metal mask layer on depositing nitride, then this nitride is carried out to etching, form spaced walls with the sidewall at described oxide mask layer;
Carry out an end-grain cutting step, to remove the nitride spacer at described oxide mask layer two ends;
The deposition monoxide, to fill the space between described nitride spacer;
Remove described nitride spacer.
2. the semiconductor making method based on the self-aligned double patterning case according to claim 1, is characterized in that, described metal mask layer is selected TiN, BN or Cu
3The N material.
3. the semiconductor making method based on the self-aligned double patterning case according to claim 1, is characterized in that, the described oxide mask layer of patterning comprises by monochromatic light and hindering or three layer pattern methods are carried out etched step.
4. the semiconductor making method based on the self-aligned double patterning case according to claim 1, it is characterized in that, described end-grain cutting step comprises: on described Semiconductor substrate, deposit photoresist layer, the described photoresist layer of patterning, to expose the nitride spacer at described oxide mask layer two ends, adopts dry etching to remove the described nitride spacer of exposing.
5. the semiconductor making method based on the self-aligned double patterning case according to claim 1, is characterized in that, the step that deposits described oxide also comprises afterwards carries out a cmp to expose the step of described nitride spacer to described oxide.
6. the semiconductor making method based on the self-aligned double patterning case according to claim 1, is characterized in that, removes described nitride spacer and select wet method or dry etching.
7. the semiconductor making method based on the self-aligned double patterning case according to claim 1, is characterized in that, described siliceous mask layer is SiC layer or SiN layer.
8. the semiconductor making method based on the self-aligned double patterning case according to claim 1, is characterized in that, described nitride is SiN.
9. the semiconductor making method based on the self-aligned double patterning case according to claim 1, is characterized in that, removes after described nitride spacer also to comprise and take described oxide as mask, the step of the described metal mask layer of dry etching.
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| CN108231770A (en) * | 2016-12-22 | 2018-06-29 | 联华电子股份有限公司 | The method for forming pattern |
| CN108666207A (en) * | 2017-03-29 | 2018-10-16 | 联华电子股份有限公司 | The method for making semiconductor element |
| CN109427686A (en) * | 2017-08-29 | 2019-03-05 | 联华电子股份有限公司 | Isolation structure and forming method thereof |
| CN109904157A (en) * | 2017-12-08 | 2019-06-18 | 长鑫存储技术有限公司 | The miniature method of characteristic size and the structure applied to semiconductor memory |
| CN110660652A (en) * | 2018-06-29 | 2020-01-07 | 台湾积体电路制造股份有限公司 | Patterning method of semiconductor device |
| US11018006B2 (en) | 2018-05-01 | 2021-05-25 | United Microelectronics Corp. | Method for patterning a semiconductor structure |
| WO2022233249A1 (en) * | 2021-05-06 | 2022-11-10 | International Business Machines Corporation | High-density memory devices using oxide gap fill |
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| US11018006B2 (en) | 2018-05-01 | 2021-05-25 | United Microelectronics Corp. | Method for patterning a semiconductor structure |
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