CN103426767B - The formation method of PMOS transistor - Google Patents
The formation method of PMOS transistor Download PDFInfo
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- CN103426767B CN103426767B CN201210165882.8A CN201210165882A CN103426767B CN 103426767 B CN103426767 B CN 103426767B CN 201210165882 A CN201210165882 A CN 201210165882A CN 103426767 B CN103426767 B CN 103426767B
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Abstract
The invention provides a kind of formation method of PMOS transistor, comprising: the substrate being formed with gate dielectric layer is provided; Form the workfunction layers covering described gate dielectric layer, the material of described workfunction layers is metal nitride; NH is passed in the reaction chamber at described substrate place
3gas, and described workfunction layers is heat-treated, to increase the nitrogen content of workfunction layers; After heat-treating, described workfunction layers forms gate electrode.The present invention utilizes NH
3described workfunction layers is heat-treated, improves the nitrogen content of metal nitride in PMOS workfunction layers, cause the increase of PMOS transistor work function, thus reduce the threshold voltage of PMOS transistor, improve device electric property.
Description
Technical field
The present invention relates to field of semiconductor fabrication processes, particularly relate to the formation method of PMOS transistor.
Background technology
Integrated circuit fabrication process follows Moore's Law high speed development always, and the characteristic size of cmos device constantly reduces according to certain ratio all the time, adopts the gate dielectric layer (hereinafter referred to as high-k gate dielectric layer) of high-g value to replace traditional SiO
2the gate dielectric layer of material is the inexorable trend of integrated circuit development.But, still have many problems anxious to be resolved when high-k gate dielectric layer is formed metal gate electrode, one of them is exactly the matching problem of work function, because work function is by the performance of the threshold voltage (Vt) and transistor that directly affect device, therefore work function must be adjusted within the proper operation scope of cmos device.Further, the work function of NMOS is approximately 4.2eV, and the work function of PMOS is approximately 5.2eV, and the work function of PMOS transistor is higher, and research finds that the higher work function of PMOS transistor is difficult to regulate.
Prior art makes all effort, to obtain the suitable work function of PMOS transistor.Such as, the Chinese patent application that date of publication is on May 25th, 2011, application publication number is CN102074469A discloses a kind of control method of the work function for PMOS transistor, the method utilizes physical vapor deposition (PVD) technique, high-k gate dielectric layer deposits layer of metal nitride film or metal film, as metal gate electrode, then ion injection method is adopted to inject the elements such as Al in metal gate electrode, by high-temperature thermal annealing, doped metal ion is diffused on the interface of metal gate electrode and high-k gate dielectric layer, thus can regulatory work function.
But prior art normally adopts PVD technique to form workfunction layers, and the method for regulatory work function normally obtains by optimizing PVD technological parameter.But, traditional deposition technique (such as PVD) has been difficult to the technique needs meeting the semiconductor device that size reduces increasingly, and atom layer deposition process (ALD, atomiclayerdeposition) stability of accurate THICKNESS CONTROL and height is possessed, even and if utilize ALD technique for vertical wide ratio up to 100: 1 structure also can realize good stepcoverage, and comply with semiconductor technology due to ALD technique and there is lower heat budget, utilize ALD technique to form high-k gate dielectric layer and will reduce damage to high-k gate dielectric layer, add the stability of high-k gate dielectric layer.Therefore, ALD technique replaces conventional deposition processes gradually and is used widely in field of semiconductor manufacture.
Therefore, how to regulate the work function of PMOS transistor, particularly adopt ALD technique to be formed into the work function how regulating PMOS transistor in workfunction layers process, become current urgent problem.
Summary of the invention
The technical problem that the present invention solves is that the work function that prior art exists PMOS transistor is difficult to regulate, the problem of how regulatory work function when particularly adopting ALD technique to form workfunction layers.
For solving the problems of the technologies described above, the embodiment of the present invention provides a kind of formation method of PMOS transistor, comprising: provide the substrate being formed with gate dielectric layer; Form the workfunction layers covering described gate dielectric layer, the material of described workfunction layers is metal nitride; NH is passed in the reaction chamber at described substrate place
3gas, and described workfunction layers is heat-treated, to increase the nitrogen content of workfunction layers; After heat-treating, described workfunction layers forms gate electrode.
Alternatively, described reaction chamber pressure between 1torr to 30torr, described heat treated temperature between 500 DEG C to 800 DEG C, the described heat treated time between 1 second to 100 seconds, described NH
3gas flow is between 1sccm to 60slm.
Alternatively, the material of described workfunction layers is TiN or TaN.
Alternatively, atom layer deposition process is utilized to form described workfunction layers.
Alternatively, the material of described gate dielectric layer is high K medium material.
Alternatively, described high K medium material comprises HfO
2, HfSiON, ZrO
2, Al
2o
3in any one or its combination in any.
Alternatively, the substrate being formed with gate dielectric layer is provided to comprise described in: to provide substrate; Form pseudo-grid structure over the substrate, described pseudo-grid structure comprises pseudo-gate electrode, gate dielectric layer between described pseudo-gate electrode and described substrate; Form interlayer dielectric layer over the substrate, the upper surface of described interlayer dielectric layer and the upper surface flush of pseudo-grid structure; Remove described pseudo-gate electrode.
Alternatively, after the pseudo-grid structure of formation, before forming interlayer dielectric layer, in described substrate, source electrode and drain electrode is formed.
Alternatively, described pseudo-grid structure comprises the etching stop layer between gate dielectric layer and pseudo-gate electrode further.
Alternatively, the step of the pseudo-grid structure of described formation comprises: provide substrate; Form dielectric layer and etching stop layer successively over the substrate; Described etching stop layer forms polysilicon layer, and graphical described polysilicon layer, forms pseudo-gate electrode; With described pseudo-gate electrode for mask, etch described dielectric layer and etching stop layer, form pseudo-grid structure, the dielectric layer after described etching forms gate dielectric layer.
Alternatively, the material of described etching stop layer is TiN or TaN.
Alternatively, atom layer deposition process is utilized to form described etching stop layer.
Alternatively, after the described etching stop layer of formation, before forming polysilicon layer, also comprise: in described reaction chamber, pass into NH
3gas, and described etching stop layer is heat-treated, to increase the nitrogen content of described etching stop layer.
Alternatively, in the step that described etching stop layer is heat-treated, described reaction chamber pressure between 1torr to 30torr, described heat treatment temperature between 500 DEG C to 800 DEG C, described heat treatment time between 1 second to 100 seconds, described NH
3gas flow is between 1sccm to 60slm.
Alternatively, the substrate being formed with gate dielectric layer is provided to comprise described in: to provide substrate; Form pseudo-gate electrode over the substrate; Form the interlayer dielectric layer covering described substrate, the upper surface of described interlayer dielectric layer and the upper surface flush of pseudo-gate electrode; Remove described pseudo-gate electrode, form pseudo-grid recess; Gate dielectric layer is formed in described pseudo-grid recess.
Alternatively, after forming pseudo-gate electrode, formed before interlayer dielectric layer, also comprise: in described substrate, pseudo-gate electrode both sides form source electrode and drain electrode.
Alternatively, the material of described gate electrode is metal.
Alternatively, the material of described gate electrode is titanium, aluminium or copper.
Alternatively, the formation method of described gate dielectric layer, workfunction layers and gate electrode comprises: provide substrate; Form dielectric layer, workfunction layers and polysilicon layer successively over the substrate; Graphical described dielectric layer, workfunction layers and polysilicon layer, described graphical after polysilicon layer form gate electrode, described graphical after dielectric layer be gate dielectric layer; Wherein, NH is passed into described in
3gas and heat treated step, after formation workfunction layers, are carried out before forming polysilicon layer.
Alternatively, formed after gate electrode, in described substrate, gate electrode both sides form source electrode and drain electrode.
Compared with prior art, the embodiment of the present invention has the following advantages:
The embodiment of the present invention by passing into NH in the reaction chamber at substrate place
3gas, and described workfunction layers is heat-treated, improve the nitrogen content of workfunction layers, cause the work function of PMOS transistor to increase, thus reduce the threshold voltage of PMOS transistor, improve device electric property.
Further, in the embodiment of the present invention, between workfunction layers and gate electrode, form etching stop layer, and adopt metal nitride such as TiN or TaN as etching stop layer, to utilize NH
3gas is heat-treated this etching stop layer, improve the nitrogen content of metal nitride in etching stop layer, thus this etching stop layer is together with workfunction layers, plays the effect of regulatory work function, reduces the threshold voltage of PMOS transistor.
Further, in the embodiment of the present invention, utilize atom layer deposition process to form workfunction layers, after utilizing ALD technique formation PMOS workfunction layers (such as TiN or TaN), adopt NH
3workfunction layers is heat-treated, thus increases the work function of PMOS transistor, solve prior art cannot regulate PMOS transistor work function technical problem by adjustment ALD technological parameter.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the formation method of the PMOS transistor of one embodiment of the invention;
Fig. 2 to Fig. 9 is the generalized section of the formation method intermediate structure of the PMOS transistor of example one of the present invention;
Figure 10 to Figure 15 is the generalized section of the formation method intermediate structure of the PMOS transistor of example two of the present invention;
Figure 16 to Figure 19 is the generalized section of the formation method intermediate structure of the PMOS transistor of example three of the present invention;
Figure 20 is that the present invention is through NH
3nitrogen element x ray energy spectrum (XPS) figure after heat treatment and before heat treatment;
Figure 21 is that the present invention is through NH
3transistor threshold voltage variation diagram after heat treatment and before heat treatment.
Embodiment
As previously mentioned, more benefit is there is owing to adopting ald (ALD) technique, such as, step coverage is good, heat budget is lower and less to the damage of high-k gate dielectric layer, and current ALD technique replaces traditional deposition process (such as PVD) gradually and is used widely in transistor formation process.In addition, in order to obtain the PMOS transistor compared with low threshold voltage, the metal gate electrode of higher work function (being approximately 5.2eV) is needed.Existing PVD technique can obtain the work function of higher PMOS transistor by optimizing PVD technological parameter, but for ALD technique, is generally difficult to the work function obtaining higher PMOS transistor at the enterprising Row sum-equal matrix of technological parameter.
Inventor finds, in metal nitride, the scale of metal and nitrogen will directly affect the work function of workfunction layers, and specifically, the nitrogen content increased in metal nitride can increase work function.
Therefore, in order to solve the problem, the embodiment of the present invention provides a kind of formation method of PMOS transistor, after the workfunction layers forming PMOS transistor, adopts NH
3described workfunction layers is heat-treated, improve the content of the nitrogen (N) of metal nitride in the workfunction layers of PMOS transistor, and this heat treatment has an impact hardly to the content of metal ingredient in metal nitride, like this, in metal nitride, nitrogen content increases, cause the work function of PMOS transistor to increase, thus reduce the threshold voltage of PMOS transistor, improve device electric property.
Specific embodiment is described in detail, so that fully understand the present invention below in conjunction with figure.But the present invention can be much different from alternate manner described here to implement, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public specific embodiment.
The embodiment of the present invention provides a kind of formation method of PMOS transistor.Specifically please refer to Fig. 1, Fig. 1 is the formation method flow schematic diagram of the PMOS transistor of the embodiment of the present invention, and the method at least comprises the following steps:
Step S1, provides the substrate being formed with gate dielectric layer;
Step S2, form the workfunction layers covering described gate dielectric layer, the material of described workfunction layers is metal nitride;
Step S3, passes into NH in the reaction chamber at described substrate place
3gas, and described workfunction layers is heat-treated, to increase the nitrogen content of workfunction layers;
Step S4, after heat-treating, described workfunction layers forms gate electrode.
Because the formation process of gate electrode can be divided into " front grid (GateFirst) " and " rear grid (GateLast) " technique, " rear grid " technique can be divided into two kinds again further according to the difference of gate dielectric layer formation order, for clearly demonstrating technical scheme of the present invention, below will represent two kinds of different process in " rear grid " technique with example one, example two respectively, represent " front grid " technique to describe the formation method of PMOS transistor of the present invention in detail with example three, but not as limit.
The method of the formation PMOS transistor of example one of the present invention is described in detail below in conjunction with Fig. 2 to Fig. 9.
First, in conjunction with referring to figs. 2 to Fig. 7, perform step S1, provide the substrate being formed with gate dielectric layer, this step S1 comprises again further:
S111, provides substrate; S112, forms dielectric layer over the substrate; S113, described dielectric layer forms etching stop layer; S114, described etching stop layer forms polysilicon layer, and graphical described polysilicon layer, forms pseudo-gate electrode; S115, with described pseudo-gate electrode for mask, etches described dielectric layer and etching stop layer, forms pseudo-grid structure, and the dielectric layer after described etching forms gate dielectric layer; S116, forms interlayer dielectric layer, the upper surface of described interlayer dielectric layer and the upper surface flush of pseudo-grid structure; Remove described pseudo-gate electrode.
First, with reference to figure 2, step S111, provide substrate 10.Described substrate 10 can be different semiconductor material.As one embodiment of the present of invention, described substrate 10 is silicon substrate or silicon-on-insulator (SOI), and described substrate needs can comprise different Doped ions, such as p-type substrate or n-type substrate according to design.Further, described substrate 10 can comprise the isolation structure (not shown) be formed thereon, such as fleet plough groove isolation structure (STI), and the formation method of described fleet plough groove isolation structure can be any method known in the art, does not repeat them here.
After isolation structure is formed, can also comprise substrate surface cleaning and form the step of interface oxide layer (not shown), the formation method of described substrate cleaning method and interface oxide layer is well known to those skilled in the art, and does not repeat them here.
With reference to figure 3, step S112, described substrate 10 forms dielectric layer 120.
The material of described dielectric layer 120 is high K medium material, such as, can comprise HfO
2, HfSiON, ZrO
2, Al
2o
3in any one or its combination in any.As one embodiment of the present of invention, the material of described dielectric layer 120 is HfO
2, and dielectric layer 120 can be formed by PVD or ALD technique.As one embodiment of the present of invention, described ALD technique comprises hafnium source and oxygen source, and described hafnium source and oxygen source ALT pulse arrive substrate surface to form material for HfO
2dielectric layer 120, described hafnium source and oxygen source are such as respectively HfCl
4and H
2o.
With reference to figure 4, step S113, described dielectric layer 120 forms etching stop layer 130.Described etching stop layer 130 is not subject to etching injury for protective dielectric layer in the step of subsequent etching polysilicon layer.If those skilled in the art will be appreciated that the situation that there will not be Damage Medium layer in subsequent technique, then also can omit the step S113 forming etching stop layer 130.
Described etching stop layer 130 can be formed by chemical vapor deposition (CVD) or ALD technique.As an embodiment, ALD technique is adopted to form etching stop layer 130.As an embodiment, the material of described etching stop layer 130 can adopt TiN or TaN, and the thickness of described etching stop layer 130 is approximately 10 to 30 dusts, such as, be 20 dusts.The selection of this etching stopping layer material, on the one hand not by follow-up etching injury, can play the effect of regulatory work function with the workfunction layers of follow-up formation again by protective dielectric layer as previously mentioned on the other hand jointly.
With reference to figure 5, step S114, described etching stop layer 130 forms polysilicon layer, graphical described polysilicon layer, form pseudo-gate electrode 140, this pseudo-gate electrode 140 is corresponding with the pseudo-grid locations of structures of follow-up formation;
Next, in conjunction with reference to figure 5 and Fig. 6, description of step S115, as one embodiment of the present of invention, with described pseudo-gate electrode 140 for mask, etch described etching stop layer 130 and dielectric layer 120, form pseudo-grid structure.Wherein, for ease of illustrating, the etching stop layer after described etching is labeled as etching stop layer 130 ', and the dielectric layer 120 after described etching is labeled as gate dielectric layer 120 '.Described pseudo-grid structure comprises the stacked structure be from bottom to top made up of gate dielectric layer 120 ', etching stop layer 130 ' and pseudo-gate electrode 140.
Those skilled in the art will be appreciated that, if there will not be the situation of damage gate dielectric layer 120 ' in subsequent technique, then can omit the step S113 forming etching stop layer 130, so, pseudo-grid structure only comprises pseudo-gate electrode 140, gate dielectric layer 120 ' between described pseudo-gate electrode 140 and described substrate, and does not have etching stop layer 130 '.
Further, after the pseudo-grid structure of formation, be also included in pseudo-grid structure side wall and form side wall 150, and with described pseudo-grid structure and side wall 150 for mask, carry out source/drain regions (not shown) ion implantation, in substrate, form source electrode and drain electrode.The step of concrete formation side wall and source/drain is well known to those skilled in the art, and does not repeat them here.
With reference to figure 7, step S116, form interlayer dielectric layer 160 over the substrate, the upper surface of described interlayer dielectric layer 160 and the upper surface flush of pseudo-grid structure, then, remove pseudo-gate electrode 140, form pseudo-grid recess 50.
As one embodiment of the present of invention, the method forming interlayer dielectric layer 160 is: form the interlayer dielectric layer 160 covering described pseudo-grid structure, interlayer dielectric layer 160 described in planarization is to exposing described pseudo-grid structure.
In the present invention, pseudo-gate electrode is formed by graphical polysilicon layer, therefore can remove pseudo-gate electrode 140 by wet method or dry etch process.As one embodiment of the present of invention, adopt wet-etching technology to remove pseudo-gate electrode, this wet-etching technology adopts and etches containing hydroxide solution (such as ammonium hydroxide), hydrogen peroxide or other polysilicon of solution to pseudo-gate electrode 140 be applicable to.This wet-etching technology optionally removes polysilicon layer, and stops at etching stop layer 130 ', thus forms pseudo-grid recess 50.
Next, with reference to figure 8, perform step S2, form the workfunction layers of covering gate dielectric layer.As one embodiment of the present of invention, form workfunction layers 170 in pseudo-grid recess, described workfunction layers 170 is formed in the bottom of described pseudo-grid recess and covers described gate dielectric layer 120 ', etching stop layer 130 '.
Described workfunction layers is in order to regulate the work function of PMOS transistor.The material of described workfunction layers 170 is metal nitride, and described workfunction layers 170 can comprise one or more layers, such as can comprise in TiN, TaN, WN, MoN or TaSiN wherein one or more.As one embodiment of the present of invention, described workfunction layers 170 is a Rotating fields, and its material can be TiN or TaN.The thickness of described workfunction layers 170 is approximately 30 to 80 dusts, alternatively, is approximately 40 to 50 dusts.
As previously mentioned, if also comprised the step being formed and comprise the etching stop layer 130 of TiN or TaN before step S2, then, in example one, workfunction layers 170 is formed on etching stop layer 130 '.The etching stop layer 130 ' of the described TiN of comprising or TaN together with the workfunction layers 170 that it is formed in order to regulate the work function of PMOS transistor.
Described workfunction layers 170 can adopt PVD or ALD technique to be formed, and as one embodiment of the present of invention, adopt ALD technique to form workfunction layers 170, such as, described ALD technique comprises titanium source (as TiCl
4) and nitrogenous source (as NH
3), described titanium source and nitrogenous source ALT pulse arrive substrate surface to form the workfunction layers 170 comprising TiN.And this ALD technique can repeat the secondary workfunction layers forming any desired thickness arbitrarily.
After formation workfunction layers 170, perform step S3, in the reaction chamber at described substrate place, pass into NH
3gas, and described workfunction layers 170 is heat-treated, to increase the nitrogen content of workfunction layers.
As previously mentioned, in order to obtain the PMOS transistor compared with low threshold voltage, need higher work function, and owing to being difficult to obtain higher PMOS transistor work function by adjustment ALD technological parameter.The embodiment of the present invention passes into NH in the reaction chamber at described substrate place
3gas, and described workfunction layers is heat-treated, improve the content of the nitrogen (N) of metal nitride in the workfunction layers of PMOS transistor, in metal nitride, nitrogen content increases, cause the increase of PMOS transistor work function, thus reduce the threshold voltage of PMOS transistor, improve device electric property.
As one embodiment of the present of invention, described process of thermal treatment parameter comprises: described reaction chamber pressure is between 1torr to 30torr; Described heat treated temperature is between 500 DEG C to 800 DEG C, and the described heat treated time is between 1 second to 100 seconds; Described NH
3gas flow is between 1sccm to 60slm.
It should be noted that, the step S113 being formed and comprise the etching stop layer of TiN or TaN is comprised at example one, this etching stop layer can together with the workfunction layers of follow-up formation, play the effect of regulatory work function, in this case, described heat treatment only can be carried out once after step S2 forms workfunction layers 170, also can heat-treat at twice: carry out a heat treatment after step sl 13 with before step S114, this heat treatment step comprises: in described reaction chamber, pass into NH
3gas, and described etching stop layer is heat-treated, to increase the nitrogen content of described etching stop layer; And carry out a heat treatment again after step S2, increase the nitrogen content of workfunction layers.Certainly, those skilled in the art will be appreciated that and by controlling the heat treated time, can control nitrogen (N) proportion of metal nitride, thus increase work function.
When the heat treatment of etching stop layer and workfunction layers is carried out respectively, as one embodiment of the present of invention, the technological parameter that etching stop layer is heat-treated is comprised: described reaction chamber pressure is between 1torr to 30torr; Described heat treatment temperature between 500 DEG C to 800 DEG C, described heat treatment time between 1 second to 100 seconds, described NH
3gas flow is between 1sccm to 60slm.
It should be noted that further, because NH
3specific activity is better, is easy to decompose, and the embodiment of the present invention utilizes NH
3workfunction layers and/or etching stop layer are heat-treated, to increase nitrogen (N) proportion in metal nitride, thus increase work function, but those skilled in the art will be appreciated that, adopt other nitrogenous gas being easy to decompose to heat-treat workfunction layers, also can obtain same technique effect.
After heat-treating, with reference to figure 9, perform step S4, described workfunction layers 170 forms gate electrode 180.As one embodiment of the present of invention, chemical vapor deposition method can be utilized in pseudo-grid recess 50 to fill metal material further, such as, be that metallic aluminium, titanium, copper or other low resistance metal form gate electrode 180.
The method of the formation PMOS transistor of example two of the present invention is described below in conjunction with Fig. 2 and Figure 10 ~ Figure 15.
First, in conjunction with reference to figure 2, and Figure 10 to Figure 13, perform step S1, provide the substrate being formed with gate dielectric layer, this step S1 comprises again further:
S121, provides substrate; S122, forms pseudo-gate electrode over the substrate; S123, forms the interlayer dielectric layer covering described substrate, the upper surface of described interlayer dielectric layer and the upper surface flush of pseudo-gate electrode; Remove described pseudo-gate electrode, form pseudo-grid recess; S124 forms gate dielectric layer in described pseudo-grid recess.
Still with reference to figure 2, perform step S121, substrate 10 is provided.This step S121 and example one step S111 is similar, does not repeat them here.
Next, with reference to Figure 10, step S122, described substrate 10 forms polysilicon layer, graphical described polysilicon layer, the polysilicon layer after this is graphical forms pseudo-gate electrode 240;
Further, with reference to Figure 11, after the pseudo-gate electrode 240 of formation, before forming interlayer dielectric layer 260, also be included in pseudo-gate electrode 240 sidewall and form side wall 250, and with described pseudo-gate electrode 240 and side wall 250 for mask, carry out source region and drain region (not shown) ion implantation, in substrate, form source electrode and drain electrode.The step of concrete formation side wall and source electrode and drain electrode is well known to those skilled in the art, and does not repeat them here.
With reference to Figure 12, step S123, form interlayer dielectric layer 260 over the substrate, the upper surface of described interlayer dielectric layer 260 and the upper surface flush of pseudo-gate electrode 240; Remove pseudo-gate electrode 240, form pseudo-grid recess 50.
As one embodiment of the present of invention, the method forming interlayer dielectric layer 260 is specially: form the interlayer dielectric layer 260 covering described pseudo-gate electrode 240 and side wall 250; Interlayer dielectric layer 260 described in planarization is to exposing described pseudo-gate electrode 240.
Pseudo-gate electrode 240 can be removed by wet method or dry etch process.As one embodiment of the present of invention, adopt wet-etching technology, this wet-etching technology adopts and etches pseudo-gate electrode containing hydroxide solution (such as ammonium hydroxide), hydrogen peroxide or other solution be applicable to.
With reference to Figure 13, step S124, in described pseudo-grid recess 50, form gate dielectric layer 220, the material of described gate dielectric layer 220 is high K medium materials, and described high K medium material can comprise HfO
2, HfSiON, ZrO
2, Al
2o
3any one or its combination in any.Described gate dielectric layer 220 is formed in the bottom of described pseudo-grid recess 50, or described gate dielectric layer 220 is formed in bottom and the sidewall of described pseudo-grid recess 50.
As one embodiment of the present of invention, the material of described gate dielectric layer 220 is HfO
2, and gate dielectric layer can be formed by techniques such as PVD, ALD.As one embodiment of the present of invention, described ALD technique comprises hafnium source and oxygen source, and it is HfO that described hafnium source and oxygen source ALT pulse arrival substrate surface form material
2gate dielectric layer 220, described hafnium source and oxygen source are such as respectively HfCl
4and H
2o.
It should be noted that, before step S124 forms gate dielectric layer 220, interface oxide layer (interfaciallayer) (not shown) can also be formed in described pseudo-grid recess 50, in order to improve the interfacial characteristics between gate dielectric layer and substrate.
Then, with reference to Figure 14, perform step S2, form the workfunction layers 270 of covering gate dielectric layer 220.
After formation workfunction layers 270, perform step S3, in the reaction chamber at described substrate place, pass into NH
3gas, and described workfunction layers 270 is heat-treated, to increase the nitrogen content of workfunction layers.
After heat-treating, with reference to Figure 15, perform step S4, described workfunction layers 270 forms gate electrode 280.It should be noted that, in example two, above-mentioned steps S2 ~ S4 and example one step S2 ~ S4 is similar, does not repeat them here.
The method of the formation PMOS transistor of example three of the present invention is described below in conjunction with Figure 16 to Figure 19.
In example three, the formation method of gate dielectric layer, workfunction layers and gate electrode comprises: step S311, provides substrate; Step S312, forms dielectric layer, workfunction layers and polysilicon layer over the substrate successively; Step S313, graphical described dielectric layer, workfunction layers and polysilicon layer, described graphical after polysilicon layer form gate electrode, described graphical after dielectric layer be gate dielectric layer.Wherein, it should be noted that, after formation workfunction layers, before forming polysilicon layer, perform step S3, in the reaction chamber at described substrate place, pass into NH
3gas, and described workfunction layers is heat-treated, to increase the nitrogen content of workfunction layers.
Below example three is described in detail.
First, with reference to figure 2, perform step S311, provide substrate 10, described step S311 and example one step S111 is similar, does not repeat them here.
Referring to figures 16 to Figure 18, perform step S312, described substrate 10 is formed dielectric layer 320, workfunction layers 330 and polysilicon layer 340 successively;
First, with reference to Figure 16, described substrate 10 forms dielectric layer 320, the method and the example one step S112 that form dielectric layer are similar, do not repeat them here.
With reference to Figure 17, dielectric layer 320 forms workfunction layers 330.Described workfunction layers 330 is in order to regulate the work function of PMOS transistor.Described workfunction layers 330 is metal nitride, and described workfunction layers can comprise one or more layers, such as can comprise in TiN, TaN, WN, MoN or TaSiN wherein one or more.As one embodiment of the present of invention, described workfunction layers is a Rotating fields, and its material can be TiN or TaN.The thickness of described workfunction layers is approximately 30 to 200 dusts.
Described workfunction layers can adopt PVD or ALD technique to be formed, and as one embodiment of the present of invention, adopt ALD technique to form workfunction layers 330, such as, described ALD technique comprises titanium source (as TiCl
4) and nitrogenous source (as NH
3), described titanium source and nitrogenous source ALT pulse arrive substrate surface and form the workfunction layers 330 comprising TiN.This ALD technique can repeat the secondary workfunction layers forming any desired thickness arbitrarily.
With reference to Figure 18, described workfunction layers 330 forms polysilicon layer 340.As one embodiment of the present of invention, can utilize chemical vapor deposition method in workfunction layers, form polysilicon layer 340, the thickness of described polysilicon layer is approximately 300 to 400 dusts.
Afterwards, with reference to Figure 19, perform step S313, graphical described polysilicon layer 340, workfunction layers 330 and dielectric layer 320, form the grid structure of PMOS transistor.Wherein, for ease of illustrating, described graphical after dielectric layer be denoted as gate dielectric layer 320 ', described graphical after workfunction layers be denoted as workfunction layers 370, described graphical after polysilicon layer be denoted as gate electrode 380.Described grid structure comprises the gate dielectric layer 320 ' be formed in successively on substrate, workfunction layers 370 and gate electrode 380.
Further, after the formation of a gate structure, the sidewall being also included in grid structure forms side wall 350, and with described grid structure and side wall for mask, carries out source/drain regions (not shown) ion implantation, in substrate, form source/drain.The step of concrete formation side wall and source/drain is well known to those skilled in the art, and does not repeat them here.
It should be noted that, after step S312 forms workfunction layers 330, before forming polysilicon layer 340, perform step S3, in the reaction chamber at described substrate place, pass into NH
3gas, and described workfunction layers is heat-treated, to increase the nitrogen content of workfunction layers.
As previously mentioned, owing to being difficult to obtain higher PMOS transistor work function by adjustment ALD technological parameter, the embodiment of the present invention is heat-treated described workfunction layers, improve the content of the nitrogen (N) of metal nitride in PMOS workfunction layers, in metal nitride, nitrogen content increases, cause the increase of PMOS work function, thus reduce the threshold voltage of PMOS transistor, improve device electric property.
As one embodiment of the present of invention, described process of thermal treatment parameter comprises: described reaction chamber pressure is between 1torr to 30torr; Described heat treatment temperature between 500 DEG C to 800 DEG C, described heat treatment time between 1 second to 100 seconds, described NH
3gas flow is between 1sccm to 60slm.
Be presented above the method that three kinds form PMOS transistor, but be not limited with above-described embodiment.Next, also nmos pass transistor can be formed as required, because the work function value of nmos device is lower, (work function of NMOS is approximately 4.2eV, the work function of PMOS is approximately 5.2eV), usually the work function of applicable nmos device just can be obtained by forming workfunction layers, without the need to increasing PMOS work function by the nitrogen content improved in workfunction layers disclosed in previous embodiment, therefore, the method forming nmos pass transistor can be any method well-known to those skilled in the art.
Figure 20 is that the present invention is through NH
3after heat treatment before (curve A) and heat treatment (curve B) workfunction layers (TiN) in x-ray power spectrum (XPS) figure of nitrogen element; Figure 21 is that the present invention is through NH
3the threshold voltage variation figure of the PMOS transistor after heat treatment and before heat treatment.Process conditions are, heat treatment temperature is 600 DEG C, and heat treatment time is 40 seconds.
In Figure 20, abscissa represents photoelectronic binding energy (bondingenergy), and ordinate represents photoelectronic relative intensity (intensity).X-ray energy spectrum analysis utilizes radiation exposure sample, makes the electronics stimulated radiation of sample Atom or molecule produce photoelectron, then measure these photoelectronic Energy distribution.Can find out that the peak value of curve A is greater than the peak value of curve B, this illustrates that the present invention is through NH
3the energy of heat treated nitrogen element strengthens, and namely nitrogen content increases.
In Figure 21, ordinate represents the threshold voltage of PMOS transistor, and in abscissa, #3 represents and do not carry out NH
3heat treatment, #24 represents and has carried out NH
3heat treatment, a string circle shown in figure, each circle represents the threshold voltage value of certain point on wafer to be measured.Can find out, the present invention is through NH
3threshold voltage decreasing after heat treatment.
In sum, according to the formation method of the PMOS transistor that the embodiment of the present invention provides, NH is utilized
3described workfunction layers is heat-treated, improves the ratio of the nitrogen (N) of metal nitride in PMOS workfunction layers, cause the increase of work function, thus reduce the threshold voltage of PMOS transistor, improve device electric property.Further, the embodiment of the present invention solves prior art cannot regulate PMOS transistor work function technical problem by adjustment ALD technological parameter, after utilizing ALD technique formation PMOS workfunction layers (such as TiN or TaN), carries out NH
3heat treatment, thus the work function increasing PMOS transistor.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (19)
1. a formation method for PMOS transistor, is characterized in that, comprising:
There is provided the substrate being formed with gate dielectric layer, described gate dielectric layer surface is formed with etching stop layer;
Form the workfunction layers covering described gate dielectric layer and described etching stop layer, the material of described workfunction layers is metal nitride, and described etching stop layer and described workfunction layers play the effect of regulatory work function jointly;
NH is passed in the reaction chamber at described substrate place
3gas, and described workfunction layers and described etching stop layer are heat-treated, to increase the nitrogen content of workfunction layers and etching stop layer, increase work function;
After heat-treating, described workfunction layers forms gate electrode.
2. the formation method of PMOS transistor as claimed in claim 1, is characterized in that, described reaction chamber pressure between 1torr to 30torr, described heat treated temperature between 500 DEG C to 800 DEG C, the described heat treated time between 1 second to 100 seconds, described NH
3gas flow is between 1sccm to 60slm.
3. the formation method of PMOS transistor as claimed in claim 1, it is characterized in that, the material of described workfunction layers is TiN or TaN.
4. the formation method of PMOS transistor as claimed in claim 1, is characterized in that, utilize atom layer deposition process to form described workfunction layers.
5. the formation method of PMOS transistor as claimed in claim 1, it is characterized in that, the material of described gate dielectric layer is high K medium material.
6. the formation method of PMOS transistor as claimed in claim 5, it is characterized in that, described high K medium material comprises HfO
2, HfSiON, ZrO
2, Al
2o
3in any one or its combination in any.
7. the formation method of PMOS transistor as claimed in claim 1, is characterized in that, described in the substrate being formed with gate dielectric layer is provided, described gate dielectric layer surface is formed with etching stop layer and comprises:
Substrate is provided;
Form pseudo-grid structure over the substrate, described pseudo-grid structure comprises pseudo-gate electrode, the gate dielectric layer between described pseudo-gate electrode and described substrate, the etching stop layer between gate dielectric layer and pseudo-gate electrode;
Form interlayer dielectric layer over the substrate, the upper surface of described interlayer dielectric layer and the upper surface flush of pseudo-grid structure;
Remove described pseudo-gate electrode.
8. the formation method of PMOS transistor as claimed in claim 7, is characterized in that, after the pseudo-grid structure of formation, before forming interlayer dielectric layer, forms source electrode and drain electrode in described substrate.
9. the formation method of PMOS transistor as claimed in claim 7, it is characterized in that, the step of the pseudo-grid structure of described formation comprises:
Substrate is provided;
Form dielectric layer and etching stop layer successively over the substrate;
Described etching stop layer forms polysilicon layer, and graphical described polysilicon layer, forms pseudo-gate electrode;
With described pseudo-gate electrode for mask, etch described dielectric layer and etching stop layer, form pseudo-grid structure, the dielectric layer after described etching forms gate dielectric layer.
10. the formation method of PMOS transistor as claimed in claim 9, it is characterized in that, the material of described etching stop layer is TiN or TaN.
The formation method of 11. PMOS transistor as claimed in claim 9, is characterized in that, utilize atom layer deposition process to form described etching stop layer.
The formation method of 12. PMOS transistor as claimed in claim 9, is characterized in that, after the described etching stop layer of formation, before forming polysilicon layer, also comprises: in described reaction chamber, pass into NH
3gas, and described etching stop layer is heat-treated, to increase the nitrogen content of described etching stop layer.
The formation method of 13. PMOS transistor as claimed in claim 12, it is characterized in that, in the step that described etching stop layer is heat-treated, described reaction chamber pressure is between 1torr to 30torr, described heat treatment temperature is between 500 DEG C to 800 DEG C, described heat treatment time between 1 second to 100 seconds, described NH
3gas flow is between 1sccm to 60slm.
The formation method of 14. PMOS transistor as claimed in claim 1, is characterized in that, described in provide the substrate being formed with gate dielectric layer to comprise:
Substrate is provided;
Form pseudo-gate electrode over the substrate;
Form the interlayer dielectric layer covering described substrate, the upper surface of described interlayer dielectric layer and the upper surface flush of pseudo-gate electrode;
Remove described pseudo-gate electrode, form pseudo-grid recess;
Gate dielectric layer is formed in described pseudo-grid recess.
The formation method of 15. PMOS transistor as claimed in claim 14, is characterized in that, after forming pseudo-gate electrode, is formed before interlayer dielectric layer, also comprises: in described substrate, pseudo-gate electrode both sides form source electrode and drain electrode.
The formation method of 16. PMOS transistor as described in claim 7 or 15, it is characterized in that, the material of described gate electrode is metal.
The formation method of 17. PMOS transistor as claimed in claim 16, is characterized in that, the material of described gate electrode is titanium, aluminium or copper.
The formation method of 18. PMOS transistor as claimed in claim 1, it is characterized in that, the formation method of described gate dielectric layer, etching stop layer, workfunction layers and gate electrode comprises:
Substrate is provided;
Form dielectric layer, etching stop layer, workfunction layers and polysilicon layer successively over the substrate;
Graphical described dielectric layer, etching stop layer, workfunction layers and polysilicon layer, described graphical after polysilicon layer form gate electrode, described graphical after dielectric layer be gate dielectric layer; Wherein, NH is passed into described in
3gas and heat treated step, after formation workfunction layers, are carried out before forming polysilicon layer.
The formation method of 19. PMOS transistor as claimed in claim 18, is characterized in that, is formed after gate electrode, and in described substrate, gate electrode both sides form source electrode and drain electrode.
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| CN108573921B (en) * | 2017-03-07 | 2021-03-09 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN107039283A (en) * | 2017-04-11 | 2017-08-11 | 中国科学院微电子研究所 | A kind of transistor device based on variable work function grid and preparation method thereof |
| CN110867489A (en) * | 2019-11-19 | 2020-03-06 | 上海华力集成电路制造有限公司 | P-type semiconductor device and method of manufacturing the same |
| CN114121658A (en) * | 2020-08-28 | 2022-03-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| CN101740372A (en) * | 2008-11-06 | 2010-06-16 | 台湾积体电路制造股份有限公司 | Gate structure including modified high-k gate dielectric and metal gate interface |
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| CN101740372A (en) * | 2008-11-06 | 2010-06-16 | 台湾积体电路制造股份有限公司 | Gate structure including modified high-k gate dielectric and metal gate interface |
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