CN103414486B - The zero intermediate frequency I/Q mismatch compensation circuit of 60GHz communication system - Google Patents
The zero intermediate frequency I/Q mismatch compensation circuit of 60GHz communication system Download PDFInfo
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Abstract
The present invention relates to 60GHz short distance broadband communications technologies, relate to a kind of zero intermediate frequency I/Q local oscillator mismatch compensation circuit based on IEEE802.11.ad agreement specifically.The zero intermediate frequency I/Q mismatch compensation circuit of 60GHz communication system of the present invention, it is characterized in that, also comprise I/Q mismatch compensation circuit, described I/Q mismatch compensation circuit comprises data correction circuit and coefficient update circuit, described data correction circuit is connected with coefficient update circuit, the switching signal of described each data correction submodule to input is corrected, described coefficient update circuit receives the correction signal that data correction circuit exports, and feeds back to data correction circuit after treatment as parameter signal.Beneficial effect of the present invention is, is suitable for IEEE802.11.ad agreement, throughput reaches 4GSps, can provide enough large signal image ratio, is applicable to amplitude and the larger occasion of phase mismatch, can overcomes the amplitude mismatch of 3dB and the phase mismatch of 10 °.The present invention is particularly useful for zero intermediate frequency reciver.
Description
Technical field
The present invention relates to 60GHz short distance broadband communications technologies, relate to a kind of zero intermediate frequency I/Q local oscillator mismatch compensation circuit based on IEEE802.11.ad agreement specifically.
Background technology
Last decade, the demand for multimedia service in real time, is at a high speed more and more vigorous, and this accelerates the development of ultra broadband (UWB) wireless communication system.UWB system can provide the transmission rate up to 480Mbps in 2 ~ 10 meters of transmission ranges.But UWB system can not meet the transmission rate of the several Gbps needed for high definition stream media business.In order to meet this requirement, recently issue the special IEEE802.11ad agreement for wireless personal domain network (WPANs).This agreement can the transmission rate of support number Gbps; The frequency band that China distributes for it is 59 ~ 64GHz.
Radio communication all needs to use the down conversion module of receiver that radiofrequency signal is become baseband signal, provides enough large image signal decay simultaneously.In theory, the zero intermediate frequency direct down-conversion receiver of quadrature downconvert can provide infinitely-great image signal to decay.But the inevitable mismatch of AFE (analog front end) device can cause I/Q mismatch, that is: the amplitude of the two-way sin/cos signal needed for quadrature downconvert is unequal, and difference is not equal to 90 °.Be mixed into the image signal through overdamping in this zero intermediate frequency baseband signal that down-conversion can be made to obtain, thus reduce the signal to noise ratio of baseband signal, and then worsen the performance of whole receiver.The carrier frequency that IEEE802.11.ad agreement specifies is near 60GHz, and larger I/Q mismatch easily appears in the quadrature oscillator be operated near this high-frequency, and as amplitude mismatch can reach 3dB, phase mismatch can reach 10 °.In addition, the total bandwidth that IEEE802.11.ad agreement specifies is 1.76GHz, must be greater than 3.58GHz according to nyquist sampling theorem sample rate, and that is the throughput of baseband digital signal processing unit must be greater than 3.58GSps.Therefore the present invention proposes a kind of specially for the zero intermediate frequency I/Q mismatch compensation circuit of IEEE802.11.ad agreement, it can overcome the amplitude mismatch of 3dB and the phase mismatch of 10 °, and its throughput can reach 4GSps.
Existing I/Q mismatch compensation circuit roughly can be divided into two kinds, all has respective shortcoming.The first compensating circuit utilizes the hypothesis that channel is constant in short-term, allows compensating circuit constantly change inner parameter with close optimum by mode of learning.During work, first under mode of learning, received training sequence change internal filter coefficients makes output signal approach a certain particular sequence gradually, and then is switched to mode of operation to correct Received signal strength, repeatedly switches ever since between these two kinds of patterns.It is applicable to zero-frequency receiver and low intermediate frequency receiver (radiofrequency signal being down-converted to the receiver architecture of a certain lower intermediate frequency).It has three large shortcomings: the first, and this circuit lacks versatility, and it needs transmitter to launch specific training sequence; The second, this circuit for time to become the tracking velocity of mismatch comparatively slow, mainly because the coefficient that obtains remain mode of learning before this in mode of operation under of the coefficient of its filters internal is constant; 3rd, in the application scenario of larger I/Q mismatch compensation, needed for this circuit, filter tap is more, thus complexity and cost higher.The second compensating circuit utilizes the statistical uncorrelation of adjacent channel signal, uses sef-adapting filter to be separated with image signal by the signal of needs, thus reaches the object eliminating I/Q mismatch.This circuit does not need training sequence, and its tracking performance is also better, but it has two large shortcomings: the first, there is leakage signal problem in theory, affects compensation effect; The second, this circuit is not suitable for zero intermediate frequency reciver, is only applicable to low intermediate frequency receiver.
The throughput of existing I/Q mismatch compensation circuit is generally lower than the minimum requirements of IEEE802.11.ad agreement.For this agreement, sample rate must be greater than 3.58GHz, continue increase sample rate can increase signal to noise ratio, but excessive sample rate can make sample circuit be difficult to realize and cost is high, 4GHz be rational sample rate select.The current analog to digital converter that can reach 4GHz sample rate is substantially all time-interleaved pattern number converter, and its way of output is parallel output, can reduce sample clock frequency like this.Fig. 1 shows the down conversion module schematic diagram of the zero intermediate frequency reciver based on IEEE802.11.ad agreement.Described down conversion module comprises: radio-frequency filter, low noise amplifier, local oscillator 1, low pass filter 1, time-interleaved pattern number converter 1, local oscillator 2, low pass filter 2, time-interleaved pattern number converter 2.Especially, the transformation result of time-interleaved pattern number converter 1 and time-interleaved pattern number converter 2 is 16 road parallel outputs, and its sampling clock is 250MHz.This just requires that the I/Q mismatch compensation circuit of rear class can process the parallel complex sampling values in 16 tunnels, and its operating frequency is 250MHz, but existing I/Q mismatch compensation circuit is difficult to meet this requirement.
Summary of the invention
Technical problem to be solved by this invention is exactly for the problems referred to above, proposes a kind of zero intermediate frequency I/Q mismatch compensation circuit of 60GHz communication system.
The present invention solves the problems of the technologies described above adopted technical scheme: the zero intermediate frequency I/Q mismatch compensation circuit of 60GHz communication system, comprise down conversion module, described down conversion module comprises radio-frequency filter, low noise amplifier, first local oscillator, first low pass filter, very first time alternate type analog to digital converter, second local oscillator, second low pass filter and the second time-interleaved pattern number converter, the output of described radio-frequency filter is connected with the input of low noise amplifier, the output of described low noise amplifier is connected with the input of the first local oscillator and the input of the second local oscillator respectively, the output of described first local oscillator is connected with the input of the first low pass filter, the input that the output of described first low pass filter is connected with very first time alternate type analog to digital converter connects, the output of described second local oscillator is connected with the input of the second low pass filter, the output of described second low pass filter is connected with the input of the second time-interleaved pattern number converter, described very first time alternate type analog to digital converter parallel output 16 tunnel first switching signal, described second time-interleaved pattern number converter parallel output 16 tunnel second switching signal, it is characterized in that, also comprise I/Q mismatch compensation circuit, described I/Q mismatch compensation circuit comprises data correction circuit and coefficient update circuit, described data correction circuit comprises 16 parallel data correction submodules, 1 tunnel first switching signal that each data correction submodule exports with very first time alternate type analog to digital converter successively respectively and 1 tunnel second switching signal that the second time-interleaved pattern number converter exports are connected, described data correction circuit is connected with coefficient update circuit, described each data correction submodule is corrected the first switching signal of input and the second switching signal, described coefficient update circuit receives the correction signal that data correction circuit exports, data correction circuit is fed back to after treatment as parameter signal.
The technical scheme that the present invention is total, corrected by 16 of the data correction circuit parallel complex signals of data correction submodule to each branch road, coefficient update circuit provides feedback parameter signal for data correction circuit, wherein each data correction submodule is by 2 × 2 matrix multipliers, receive 2 × 1 vector signals that the real part of analog to digital converter sampling gained complex signal and imaginary part form and 2 × 2 matrix parameter signals that coefficient updating module exports respectively, 2 × 1 vector signals that the matrix multiplication value exporting these two groups inputs forms, realize the correction to data.
Concrete, each data correction submodule of described data correction circuit includes 2 × 2 matrix multipliers, described 2 × 2 matrix multipliers comprise first to fourth multiplier and the first to second adder, an input of described first multiplier and the 3rd multiplier is the first switching signal of very first time alternate type analog to digital converter output, another input is respectively the first parameter signal and the 3rd parameter signal of the output of coefficient update circuit, an input of described second multiplier and the 4th multiplier is the second switching signal of the second time-interleaved pattern number converter output, another input is respectively the second parameter signal and the 4th parameter signal of the output of coefficient update circuit, two inputs of described first adder are connected with the output of the first multiplier and the second multiplier respectively, output exports the first correction signal, two inputs of described second adder are connected with the output of the 3rd multiplier and the 4th multiplier respectively, output exports the second correction signal, coefficient update circuit gathers the first correction signal and the second correction signal, and export first to fourth parameter signal.
Further, described coefficient update circuit comprises the 5th to the 15 multiplier, first to fourth constant multiplier and the 3rd to the 8th adder, two inputs of the 5th multiplier are the first correction signal, output is connected with the input of the first constant multiplier, two inputs of the 6th multiplier are respectively the first correction signal and the second correction signal, output is connected with the input of the second constant multiplier and three constant multiplier respectively, two inputs of the 7th multiplier are the second correction signal, output is connected with the input of the 4th constant multiplier, two inputs of the 3rd adder are respectively output and the constant signal λ+1 of the first constant multiplier, output is connected with an input of the 8th multiplier and the tenth multiplier respectively, the output of the second constant multiplier is connected with an input of the tenth paired multiplier and the 14 multiplier respectively, the output of three constant multiplier is connected with an input of the 9th multiplier and the 11 multiplier respectively, two inputs of the 4th adder are connected with the output of the 4th constant multiplier and constant signal λ+1 respectively, output is connected with an input of the 13 multiplier and the 15 multiplier respectively, two inputs of slender acanthopanax musical instruments used in a Buddhist or Taoist mass are connected with the output of the 8th multiplier and the output of the tenth paired multiplier respectively, output is the first coefficient update signal, two inputs of the 6th adder are connected with the output of the tenth multiplier and the output of the 14 multiplier respectively, output is the second coefficient update signal, two inputs of the 7th adder are connected with the output of the 9th multiplier and the output of the 13 multiplier respectively, output is the 3rd coefficient update signal, two inputs of the 8th adder are connected with the output of the 11 multiplier and the output of the 15 multiplier respectively, output is Quaternary system number update signal, first to fourth coefficient update signal exports first to fourth parameter signal through 4 grades of registers of a cascade, first parameter signal connects another input of the 8th multiplier and the 9th multiplier, second parameter signal connects another input of the tenth multiplier and the 11 multiplier, 3rd parameter signal connects another input of the tenth paired multiplier and the 13 multiplier, 4th parameter signal connects another input of the 14 multiplier and the 15 multiplier.
Beneficial effect of the present invention is, be suitable for IEEE802.11.ad agreement, throughput reaches 4GSps, enough large signal image ratio can be provided, be applicable to amplitude mismatch and reach 3dB and phase mismatch reaches the occasion of 10 °, do not need simultaneously transmitter provide specific training sequence can pair time the I/Q mismatch that becomes desirable tracking performance is provided.
Accompanying drawing explanation
Fig. 1 is the system configuration schematic diagram of the down conversion module of zero intermediate frequency reciver based on IEEE802.11.ad agreement;
Fig. 2 is the schematic diagram of I/Q mismatch digital compensating circuit;
Fig. 3 is the schematic diagram of the data correction module in digital compensation circuit;
Fig. 4 is the schematic diagram of the coefficient updating module in digital compensation circuit;
Fig. 5 is the schematic diagram correcting the contrast of front signal power spectrum;
Fig. 6 is the schematic diagram of power spectrum signal contrast after correcting;
Fig. 7 is the schematic diagram of the convergence track that in the blind correction procedure of signal, coefficient updating module exports.
Embodiment
Below in conjunction with accompanying drawing, describe technical scheme of the present invention in detail:
As shown in Figure 1, the zero intermediate frequency I/Q mismatch compensation circuit of 60GHz communication system of the present invention, comprise down conversion module, described down conversion module comprises radio-frequency filter, low noise amplifier, the first local oscillator 1, first low pass filter 1, very first time alternate type analog to digital converter 1, second local oscillator 2, second low pass filter 2, second time-interleaved pattern number converter 2 and I/Q mismatch compensation circuit, wherein α and
be respectively used to analog amplitude and phase mismatch, described radio-frequency filter is connected with low noise amplifier, described low noise amplifier is connected with the first local oscillator 1 and the second local oscillator 2 respectively, described first low pass filter 1 is connected with the first local oscillator 1 and very first time alternate type analog to digital converter 1 respectively, described second low pass filter 2 is connected with the second local oscillator 2 and the second time-interleaved pattern number converter 2 respectively, described very first time alternate type analog to digital converter 1 parallel output 16 tunnel first switching signal, described second time-interleaved pattern number converter 2 parallel output 16 tunnel second switching signal, I/Q mismatch compensation circuit comprises data correction circuit and coefficient update circuit, described data correction circuit comprises 16 parallel data correction submodules, 1 tunnel first switching signal that each data correction submodule exports with very first time alternate type analog to digital converter 1 successively respectively and 1 tunnel second switching signal that the second time-interleaved pattern number converter 2 exports are connected, data correction circuit is connected with coefficient update circuit, each data correction submodule is corrected the first switching signal of input and the second switching signal, described coefficient update circuit receives the correction signal that data correction circuit exports, data correction circuit is fed back to after treatment as parameter signal.
The 16 road parallel signals conveniently describe, the first switching signal I that hereinafter very first time alternate type analog to digital converter 1 exports replaces, exporting are expressed as x successively
i1to x
i16; The 16 road parallel signals that the second switching signal Q that second time-interleaved pattern number converter 2 exports replaces, export are expressed as x successively
q1to x
q16; 16 tunnel first correction signals that data correction circuit exports are expressed as y successively
i1to y
i16, the second correction signal is expressed as y successively
q1to y
q16, first to fourth parameter signal is expressed as b successively
11, b
12, b
21and b
22, 4 parameter signal composition 2 × 2 matrix signal B
k-4, first to fourth coefficient update signal is expressed as nb successively
11, nb
12, nb
21and nb
22, 4 coefficient update signal composition 2 × 2 matrix signal B
k.
As shown in Figure 2, the input that I/Q mismatch digital compensating circuit of the present invention has 16 tunnels parallel, the input of every road forms a complex signal by I and Q two real number signals; Have the output that 16 tunnels are parallel, every road exports and forms a complex signal by I and Q two real number signals.Wherein z
-1represent a register, z
-4represent 4 registers of cascade.The circuit structure that every bar individual path comprises is identical, introduces for Article 1 individual path, as shown in Figure 3, contains the module of 3 cascades from left to right: 4 grades of registers of a register, a data correction module, a cascade.Register is this area general-purpose device.It is input as x
i, x
qand B
k-4, wherein B
k-4be 2 × 2 matrix signals, by b
11, b
12, b
21and b
22four real signals are formed.It exports as y
iand y
q.Its internal circuit is described from top to bottom: x from left to right
iand b
11be the input of the first multiplier, produce and export m
1; x
qand b
12be the input of the second multiplier, produce and export m
2; x
iand b
21be the input of the 3rd multiplier, produce and export m
3; x
qand b
22be the input of the 4th multiplier, produce and export m
4; m
1and m
2for the input of first adder, produce and export y
i; m
3and m
4for the input of second adder, produce and export y
q.Wherein, first to fourth multiplier is real multipliers, and the first to second adder is real add musical instruments used in a Buddhist or Taoist mass.
Coefficient update path of the present invention is a reaction type path, and concrete structure as shown in Figure 4.Its input signal is y
i1, y
q1, export as B
k-4, B simultaneously
k-4also in feedback fashion as internal input signal.Coefficient update path contains the module of 2 cascades from top to bottom: 4 grades of registers of a coefficient updating module, a cascade.Register is this area general-purpose device.It is input as y
i1, y
q1, export as B
k-4, be 2 × 2 matrix signals, by b
11, b
12, b
21and b
22four real signals are formed.Its internal circuit is described from left to right: two of first real multipliers are input as identical y from top to bottom
i1, export and be
; Two of second real multipliers are input as y
i1and y
q1, export as y
iy
q; Two of 3rd real multipliers are input as identical y
q1, export and be
; Being input as of first constant multiplier
, export and be
(λ gets 2
-7); Second constant multiplier be input as y
iy
q, export as t
12; 3rd constant multiplier be input as y
iy
q, export as t
21; Being input as of 4th constant multiplier
, export and be
; Two inputs of first real add musical instruments used in a Buddhist or Taoist mass are respectively constant λ+1 and signal
, export as t
11; Two inputs of second real add musical instruments used in a Buddhist or Taoist mass are respectively constant λ+1 and signal
, export as t
22; Two of 4th real multipliers are input as t
11and b
11, export as both product b
11t
11; Two of 5th real multipliers are input as t
21and b
11, export as both product b
11t
21; Two of 6th real multipliers are input as t
11and b
12, export as both product b
12t
11; Two of 7th real multipliers are input as t
21and b
12, export as both product b
12t
21; Two of 8th real multipliers are input as t
12and b
21, export as both product b
21t
12; Two of 9th real multipliers are input as t
22and b
21, export as both product b
21t
22; Two of tenth real multipliers are input as t
12and b
22, export as both product b
22t
12; Two of 11 real multipliers are input as t
22and b
22, export as both product b
22t
22; Two inputs of the 3rd real add musical instruments used in a Buddhist or Taoist mass are respectively b
11t
11and b
21t
12, export as nb
11; Two inputs of the 4th real add musical instruments used in a Buddhist or Taoist mass are respectively b
12t
11and b
22t
12, export as nb
12; Two inputs of the 5th real add musical instruments used in a Buddhist or Taoist mass are respectively b
11t
21and b
21t
22, export as nb
21; Two inputs of the 6th real add musical instruments used in a Buddhist or Taoist mass are respectively b
12t
21and b
22t
22, export as nb
22.
Present invention employs EASI(equivariantadaptiveseparationviaindependence) algorithm, and some simplification have been done to this primal algorithm.The course of work of this algorithm is an iterative process, progressively recovers the mutual independence of mismatch signal.Signal Y=[y after correction
i, y
q]
t=B*X, wherein separation matrix
Every new produce a Y after, a new B will be upgraded, thus make the signal after correction become separate gradually.The expression formula upgrading matrix B is B=B-λ * G*B=(I-λ * G) * B, wherein G=Y*Y
t-I+f (Y) * Y
t-Y*f (Y)
t, f (Y)=[0,0], λ=2
-7.
In order to test the error-correcting effect of the present invention to I/Q mismatch, test platform adopts the complex signal (3dB amplitude mismatch and 10 ° of phase mismatchs) with the interference of serious image signal as signal to be tested, its power spectrum illustrates as shown in Figure 5, its positive frequency part is the power spectrum of the complex signal needed, and negative frequency part is the power spectrum of the image signal be mixed into, it is produced by I/Q, can see it only than the power attenuation 14.5dB of positive frequency part, can think an interference that can not ignore.This signal parallel is input to 16 road parallel input terminal of the present invention, then power spectrumanalysis is carried out to output signal, obtain the power spectrum correcting rear signal.After correcting, the power spectrum of signal illustrates as shown in Figure 6, its positive frequency part is the power spectrum of the complex signal needed, and negative frequency part is the power spectrum of image signal, can see that image signal has been attenuated to-26dB, meet the requirement to signal to noise ratio of receiver post-module.
In whole correction procedure, the track of the output of coefficient updating module is shown in Figure 7, can see, these 4 values are slowly approaching certain value separately, and near being stabilized in, this phenomenon also coincidence theory is derived.
In order to proved invention circuit can be performed by FPGA, HDL coded description of the present invention has been carried out comprehensive and placement-and-routing, and have passed FPGA realization flow error-free.The target devices that FPGA realizes is Virtex-7xc7vx485t-3-ffg1761, but is not limited to the fpga chip of this model.Goal time order is the clock frequency of 250MHz, and this sequential is restrained.Resource consumption situation is 75 DSP48E1,1570 SliceLUTs and 1156 SliceRegisters.Specifically as shown in table 1FPGA synthesis result:
Table 1FPGA synthesis result
Therefore, I/Q mismatch compensation circuit provided by the invention, its characteristics and advantages is: be suitable for IEEE802.11.ad agreement, throughput reaches 4GSps, can compensate large I/Q mismatch (at least 3dB amplitude mismatch and 10 ° of phase mismatchs), do not need special training sequence, be suitable for zero intermediate frequency reciver.
Claims (3)
- The zero intermediate frequency I/Q mismatch compensation circuit of 1.60GHz communication system, comprise down conversion module, described down conversion module comprises radio-frequency filter, low noise amplifier, first local oscillator, first low pass filter, very first time alternate type analog to digital converter, second local oscillator, second low pass filter and the second time-interleaved pattern number converter, the output of described radio-frequency filter is connected with the input of low noise amplifier, the output of described low noise amplifier is connected with the input of the first local oscillator and the input of the second local oscillator respectively, the output of described first local oscillator is connected with the input of the first low pass filter, the input that the output of described first low pass filter is connected with very first time alternate type analog to digital converter connects, the output of described second local oscillator is connected with the input of the second low pass filter, the output of described second low pass filter is connected with the input of the second time-interleaved pattern number converter, described very first time alternate type analog to digital converter parallel output 16 tunnel first switching signal, described second time-interleaved pattern number converter parallel output 16 tunnel second switching signal, it is characterized in that, also comprise I/Q mismatch compensation circuit, described I/Q mismatch compensation circuit comprises data correction circuit and coefficient update circuit, described data correction circuit comprises 16 parallel data correction submodules, 1 tunnel first switching signal that each data correction submodule exports with very first time alternate type analog to digital converter successively respectively and 1 tunnel second switching signal that the second time-interleaved pattern number converter exports are connected, described data correction circuit is connected with coefficient update circuit, described each data correction submodule is corrected the first switching signal of input and the second switching signal, wherein each data correction submodule is by 2 × 2 matrix multipliers, receive 2 × 1 vector signals that the real part of analog to digital converter sampling gained complex signal and imaginary part form and 2 × 2 matrix parameter signals that coefficient updating module exports respectively, 2 × 1 vector signals that the matrix multiplication value exporting these two groups inputs forms, described coefficient update circuit receives the correction signal that data correction circuit exports, and feeds back to data correction circuit after treatment as parameter signal.
- 2. the zero intermediate frequency I/Q mismatch compensation circuit of 60GHz communication system according to claim 1, it is characterized in that, each data correction submodule of described data correction circuit includes 2 × 2 matrix multipliers, described 2 × 2 matrix multipliers comprise first to fourth multiplier and the first to second adder, an input of described first multiplier and the 3rd multiplier is the first switching signal of very first time alternate type analog to digital converter output, another input is respectively the first parameter signal and the 3rd parameter signal of the output of coefficient update circuit, an input of described second multiplier and the 4th multiplier is the second switching signal of the second time-interleaved pattern number converter output, another input is respectively the second parameter signal and the 4th parameter signal of the output of coefficient update circuit, two inputs of described first adder are connected with the output of the first multiplier and the second multiplier respectively, output exports the first correction signal, two inputs of described second adder are connected with the output of the 3rd multiplier and the 4th multiplier respectively, output exports the second correction signal, coefficient update circuit gathers the first correction signal and the second correction signal, and export first to fourth parameter signal.
- 3. the zero intermediate frequency I/Q mismatch compensation circuit of 60GHz communication system according to claim 2, it is characterized in that, described coefficient update circuit comprises the 5th to the 15 multiplier, first to fourth constant multiplier and the 3rd to the 8th adder, two inputs of the 5th multiplier are the first correction signal, output is connected with the input of the first constant multiplier, two inputs of the 6th multiplier are respectively the first correction signal and the second correction signal, output is connected with the input of the second constant multiplier and three constant multiplier respectively, two inputs of the 7th multiplier are the second correction signal, output is connected with the input of the 4th constant multiplier, two inputs of the 3rd adder are respectively output and the constant signal λ+1 of the first constant multiplier, output is connected with an input of the 8th multiplier and the tenth multiplier respectively, the output of the second constant multiplier is connected with an input of the tenth paired multiplier and the 14 multiplier respectively, the output of three constant multiplier is connected with an input of the 9th multiplier and the 11 multiplier respectively, two inputs of the 4th adder are connected with the output of the 4th constant multiplier and constant signal λ+1 respectively, output is connected with an input of the 13 multiplier and the 15 multiplier respectively, two inputs of slender acanthopanax musical instruments used in a Buddhist or Taoist mass are connected with the output of the 8th multiplier and the output of the tenth paired multiplier respectively, output is the first coefficient update signal, two inputs of the 6th adder are connected with the output of the tenth multiplier and the output of the 14 multiplier respectively, output is the second coefficient update signal, two inputs of the 7th adder are connected with the output of the 9th multiplier and the output of the 13 multiplier respectively, output is the 3rd coefficient update signal, two inputs of the 8th adder are connected with the output of the 11 multiplier and the output of the 15 multiplier respectively, output is Quaternary system number update signal, first to fourth coefficient update signal exports first to fourth parameter signal through 4 grades of registers of a cascade, first parameter signal connects another input of the 8th multiplier and the 9th multiplier, second parameter signal connects another input of the tenth multiplier and the 11 multiplier, 3rd parameter signal connects another input of the tenth paired multiplier and the 13 multiplier, 4th parameter signal connects another input of the 14 multiplier and the 15 multiplier, wherein λ is 2 -7.
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| CN109861706B (en) * | 2019-02-27 | 2020-09-08 | 中国电子科技集团公司第五十四研究所 | Quadrature mismatch compensation device and method for broadband zero intermediate frequency receiver |
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| CN1183179A (en) * | 1995-03-09 | 1998-05-27 | 艾利森公司 | Slope, drift and offset compensation in zero-if receivers |
| CN102231636A (en) * | 2011-06-21 | 2011-11-02 | 清华大学 | Radio frequency front end device of receiver and signal receiving method thereof |
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