CN103390992B - Switching Power Supply and improve the circuit of its output current regulation - Google Patents
Switching Power Supply and improve the circuit of its output current regulation Download PDFInfo
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Abstract
The invention provides a kind of Switching Power Supply and improve the circuit of its output current regulation, described circuit comprises: voltage amplifier, carries out pre-amplification to sampled voltage; First voltage comparator, first input end is connected with the output of voltage amplifier, and the second input is connected with the output of voltage regulator; First rest-set flip-flop, set input receives external timing signal, and the RESET input is connected with the output of the first voltage comparator, and output produces switch controlling signal; Pulse-generating circuit, produces reseting pulse signal and counting pulse signal; Second voltage comparator, produces direction control signal; Counter take counting pulse signal as clock, carries out incremental count or countdown according to reseting pulse signal and direction control signal; Voltage regulator, according to the internal reference voltage of the count value regulation output that counter exports.Suitable parameters scope of the present invention is comparatively large, and precision is high, improve in output current line regulation with the obvious advantage.
Description
Technical field
The present invention relates to Switching Power Supply and its internal circuit, particularly relate to a kind of Switching Power Supply and improve the circuit of its output current regulation.
Background technology
Switching Power Supply has the little feature of efficiency height volume, is the first-selected power supply scheme of electronic equipment particularly mobile electronic device.For Off-line SMPS, usually need power supply to have constant voltage/constant current output characteristic, namely can provide constant output voltage when load current reaches before current limit, when load voltage reaches constant electricity, power supply exports constant current with constant current mode work.
Flyback power supply realizes output voltage Current adjustment by detecting Transformer Winding information of voltage thus meets the requirement of constant pressure and flow output characteristic, thus system cost is reduced owing to eliminating the device such as Voltage Reference and optocoupler, the requirement of specific precision can be met again simultaneously, be widely used in low-power power adapter and charger.
In prior art, under constant current mode, controller realizes output current adjustment by detecting transformer primary winding current.Controller works with particular switch frequency Fsw, and in each work period, switch is opened, and flows through switching current to shutdown switch during peak current Ipk when detecting.If Switching Power Supply is operated in discontinuous current mode (DCM), the inductance of transformer is L, then according to energy conservation principle, the large I of output current is expressed as:
Wherein η is conversion efficiency, and Vout is output voltage.
No matter under constant voltage or constant current output pattern, Switching Power Supply all requires to have excellent input line regulation, and namely when input voltage changes, output voltage or electric current need to remain unchanged.As can be seen from formula (1), under L, Fsw, η and Vout remain unchanged situation, output current depends on Ipk size.Therefore to realize excellent output current line regulation, must ensure that Ipk remains unchanged in wide input voltage range.
Fig. 1 shows constant current realizing circuit conventional in a kind of prior art.The source electrode adopting resistance 203 to be connected on switch 202 in the circuit realizes the detection of switching current, and its breaker in middle 202 is connected with the primary side coil of transformer 201.Voltage on resistance 203 directly compares with fixing reference voltage vrefoc, realize the restriction of switch peak current, when the voltage cs on resistance 203 reaches vrefoc, the output switching activity of comparator 205, is reset to 0 by the output of rest-set flip-flop 206, and by drive circuit 207 shutdown switch 202.Therefore in each switch periods, the peak current flowing through switch 202 can be expressed as:
Wherein Rcs represents the resistance value of switch 202, Vin is the direct voltage of input transformer 201, Tdelay represents the propagation delay time of comparator 205, rest-set flip-flop 206 and drive circuit 207, and L is the inductance of the primary side coil of transformer 201, and vrefoc is the magnitude of voltage of reference voltage vrefoc.
Fig. 2 gives the switching current waveform under different Vin condition.Under a lower input voltage vinl and high-line input voltage vinh, due to the effect of transmission delay, the actual peak current flowing through switch can be expressed as:
Wherein, Δ Ipkl is the difference current under lower input voltage vinl, and Δ IpkH is the difference current under high-line input voltage vinh, and the implication of other parameters is identical with parameter corresponding in formula (2).In above formula (3) and (4), because L and Tdelay remains unchanged, due to vinh > vinl, therefore Ipkh > Ipkl, due to the impact of Tdelay, actual output current will raise with input voltage, thus increase causes output current line regulation to be deteriorated.
In order to improve the line regulation performance of output current, with the change of input voltage, there are some compensation methodes in prior art in necessary compensated peak electric current I pk.
Fig. 3 shows signal curve corresponding to a kind of compensation method of the prior art, this approach application one resistance detection vin also produces a compensated current reference vrefoc, when input voltage being changed by adjustment non-essential resistance, to equal the overcurrent momentum that Tdelay causes poor for the knots modification of current reference vrefoc, namely (vrefocl-vrefoch)/Rcs=Δ Ipkh-Δ Ipkl is made, wherein Rcs represents the resistance value of switch, Δ Ipkl is the difference current under lower input voltage vinl, Δ IpkH is the difference current under high-line input voltage vinh, vrefocl is the smaller value of current reference vrefoc, vrefoch is the higher value of current reference vrefoc.The method, by regulating current reference vrefoc, can ensure that the peak current Ipk flowing through switch when input voltage changes remains unchanged.
Fig. 4 shows signal curve corresponding to another compensation method, this method produces a time dependent current reference signal vrefoc, size with the increase current reference signal vrefoc of service time increases, when low input, service time is long, therefore corresponding current reference signal vrefocl is larger, when high input voltage, service time is short, therefore corresponding current reference signal vrefoch is less, white fungus, by designing suitable current reference signal vrefoc rate over time, can meet peak current Ipk when input voltage changes and remain unchanged.
But the suitable parameters scope of the various technical schemes of prior art is less, and precision is not high.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of Switching Power Supply and improves the circuit of its output current regulation, and suitable parameters scope is comparatively large, and precision is high, improve in output current line regulation with the obvious advantage.
For solving the problems of the technologies described above, the invention provides a kind of circuit improving switch power supply output current line regulation, the switch that described Switching Power Supply comprises transformer, contact with the primary side coil of described transformer, and the output of the described switch sampling resistor of contacting, the current conversion flowing through described switch is sampled voltage by described sampling resistor, described circuit comprises voltage amplifier, the first voltage comparator, the second voltage comparator, pulse-generating circuit, counter, voltage regulator, the first rest-set flip-flop, wherein
Described voltage amplifier receives described sampled voltage and carries out pre-amplification to it;
The first input end of described first voltage comparator is connected with the output of described voltage amplifier, and the second input is connected with the output of described voltage regulator;
The set input of described first rest-set flip-flop receives external timing signal, and the RESET input is connected with the output of described first voltage comparator, and its output produces switch controlling signal, and described switch controlling signal transfers to the control end of described switch;
Described pulse-generating circuit receives described switch controlling signal, produces reseting pulse signal when the rising edge of described switch controlling signal arrives, and produces counting pulse signal when the trailing edge of described switch controlling signal arrives after the time of delay of presetting;
The first input end of described second voltage comparator is connected with the output of described voltage amplifier, and the second input receives external reference voltage, and its output produces direction control signal;
Described counter for clock, carries out incremental count or countdown according to described reseting pulse signal and direction control signal with described counting pulse signal;
Described voltage regulator receives described external reference voltage, and the internal reference voltage of the count value regulation output exported according to described counter, described internal reference voltage reduces when described count value increases, and increases when described count value reduces.
Alternatively, described voltage regulator comprises:
First operational amplifier, its in-phase input end receives described external reference voltage, and its inverting input is connected with its output;
First resistance, its one end connects the output of described first operational amplifier, and the other end connects the output of described voltage regulator;
Controllable current circuit, according to the size of described count value regulation output electric current, and transfers to the output of described voltage regulator by output current.
Alternatively, described controllable current circuit comprises:
Multiple current mirror, the output current of each current mirror doubles successively, and wherein the output of each current mirror controls respectively by one the output that transistor is connected to described voltage regulator, and each grid controlling transistor receives each bit of described count value respectively.
Alternatively, described pulse-generating circuit comprises:
First not gate, its input receives described switch controlling signal;
First delayer, its input is connected with the output of described first not gate;
First NAND gate, its first input end is connected with the output of described first delayer, and its second input receives described switch controlling signal;
Second not gate, its input connects the output of described first NAND gate, and its output produces described reseting pulse signal;
Second delayer, its input receives described switch controlling signal;
3rd not gate, its input connects the output of described second delayer;
4th not gate, its input connects the output of described 3rd not gate;
3rd delayer, its input connects the output of described 4th not gate;
Second NAND gate, its first input end connects the output of described 3rd delayer, and its second input connects the output of described 3rd not gate;
5th not gate, its input connects the output of described second NAND gate, and its output produces described counting pulse signal.
Alternatively, described counter comprises:
Second rest-set flip-flop, its set input receives described direction control signal, and its RESET input receives described reseting pulse signal;
Multiple counting units of contacting successively, wherein highest counting unit comprises:
First JK flip-flop, its J input is connected the output of prime counting unit with K input; Every one-level counting unit except described highest counting unit comprises:
Second JK flip-flop, its J input is connected the output of prime counting unit with K input, the J input of the second JK flip-flop of lowermost level counting unit and K input receive logic high level;
3rd NAND gate, its input connects the positive output end of described second rest-set flip-flop and the second JK flip-flop respectively;
4th NAND gate, its input connects the reversed-phase output of described rest-set flip-flop and the second JK flip-flop respectively;
5th NAND gate, its input connects the output of described 3rd NAND gate and the 4th NAND gate respectively, and its output is as the output of this grade of counting unit;
6th NAND gate, its first to the 3rd input connects the positive output end of described second rest-set flip-flop and the first JK flip-flop and the J input of described first JK flip-flop respectively;
7th NAND gate, its first to the 3rd input connects the reversed-phase output of described second rest-set flip-flop and the first JK flip-flop and the J input of described first JK flip-flop respectively;
8th NAND gate, its first and second input connects the output of described 6th NAND gate and the 7th NAND gate respectively, and its 3rd input receives described counting pulse signal;
6th not gate, its input is connected with the output of described 8th NAND gate, and its output produces internal clock signal and the input end of clock of the first JK flip-flop transferred in counting unit at different levels and the second JK flip-flop.
Alternatively, described circuit also comprises: oscillator, for generation of described external timing signal.
Alternatively, described circuit also comprises: drive circuit, and the switch controlling signal that described rest-set flip-flop exports transfers to the control end of described switch after being driven by described drive circuit.
Present invention also offers a kind of Switching Power Supply, comprise the circuit of the raising switch power supply output current line regulation described in above any one.
Compared with prior art, the present invention has the following advantages:
The Switching Power Supply of the embodiment of the present invention and improve in the circuit of its output current regulation, the counting direction of control counter is carried out according to the comparative result of sampled voltage and external reference voltage, correspondingly adjust the size of internal reference voltage afterwards again according to the count value of counter, and then keep the constant of output current.Technical scheme adaptation parameter scope of the present invention is wide, and precision is high, has clear superiority improving in output current line regulation.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of a kind of Switching Power Supply of the prior art;
Fig. 2 is the curve chart of the switching current of Switching Power Supply under different input voltage when not providing any compensation;
Fig. 3 be in prior art a kind of afford redress after switching current and the curve chart of input voltage;
Fig. 4 be in prior art another kind of afford redress after switching current and the curve chart of input voltage;
Fig. 5 is the circuit diagram of the Switching Power Supply of the embodiment of the present invention;
Fig. 6 is the working signal sequential chart of the Switching Power Supply of the embodiment of the present invention;
Fig. 7 is the detailed circuit diagram of the pulse-generating circuit in the Switching Power Supply of the embodiment of the present invention;
Fig. 8 is the detailed circuit diagram of the counter in the Switching Power Supply of the embodiment of the present invention;
Fig. 9 is the detailed circuit diagram of the voltage regulator in the Switching Power Supply of the embodiment of the present invention;
Figure 10 is the graph of relation of the count value of the internal reference voltage that exports of voltage regulator in the Switching Power Supply of the embodiment of the present invention and input.
Embodiment
Below in conjunction with specific embodiments and the drawings, the invention will be further described, but should not limit the scope of the invention with this.
Fig. 5 shows the circuit diagram of the Switching Power Supply of the present embodiment, those skilled in the art are to be understood that, basically illustrate in Fig. 5 and improve the circuit 50 of switch power supply output current line regulation and the miscellaneous part with its direct correlation, and and not shown complete circuit, those skilled in the art should know the complete circuit of this Switching Power Supply in conjunction with known peripheral circuit.
With reference to figure 5, this Switching Power Supply comprises transformer 502, the switch 501 of contact with the primary side coil of transformer 502, and switch 501 sampling resistor 503 of contacting, and the current conversion flowing through switch 501 is sampled voltage cs by sampling resistor 503.The present embodiment breaker in middle 501 adopts a transistor to realize, and its source electrode and drain electrode are respectively as input, output, and its grid is as control end.
This Switching Power Supply also comprises the circuit 20 improving switch power supply output current line regulation, this circuit 20 specifically comprises: voltage amplifier 512, first voltage comparator 509, second voltage comparator 504, pulse-generating circuit 505, counter 506, voltage regulator 507, rest-set flip-flop 510, comprise oscillator 508, drive circuit 511 in addition.
Wherein, two inputs of voltage amplifier 512 are connected with the two ends of sampling resistor 503 respectively, receive sampled voltage cs and carry out pre-amplification to it.
The first input end of the first voltage comparator 509 is connected with the output of voltage amplifier 512, and the second input is connected with the output of voltage regulator 507, and output is connected with the RESET input of rest-set flip-flop 510.First voltage comparator 509 compares for the internal reference voltage vrefoc produced the sampled voltage vcs after pre-amplification and voltage regulator 507.In the present embodiment, the sampled voltage vcs after pre-amplification transfers to the in-phase input end of the first voltage comparator 509, and internal reference voltage vrefoc transfers to the inverting input of the first voltage comparator 509.
Oscillator 508 for generation of external timing signal clk, and transmits it to the set input of rest-set flip-flop 510.
The output of the set input connection oscillator 508 of rest-set flip-flop 510, for receiving external timing signal clk; The RESET input of rest-set flip-flop 510 connects the output of the first voltage comparator 509; The output of rest-set flip-flop 510 produces switch controlling signal gate, and this switch controlling signal gate transfers to the control end of switch 501, for conducting or the shutoff of control switch 501.In the present embodiment, switch controlling signal gate is first by transferring to the control end of switch 502 again after the driving of drive circuit 511.
Pulse-generating circuit 505 receives this switch controlling signal gate, produce reseting pulse signal rst when the rising edge of switch controlling signal gate arrives, after the time of delay of presetting, produce counting pulse signal clkc when the trailing edge of switch controlling signal gate arrives.
The first input end of the second voltage comparator 504 is connected with the output of voltage amplifier 512, and the second input receives external reference voltage vref, and its output produces direction control signal updn.
Wherein, external reference voltage vref can be provided by inner or outside reference voltage source, and its magnitude of voltage can be the magnitude of voltage preset needing according to actual design and determine.
Counter 506 for clock, carries out incremental count or countdown according to reseting pulse signal rst and direction control signal updn with counting pulse signal clkc.The bit wide of the count value that counter 506 exports can adjust according to actual needs, as a nonrestrictive example, is 5 bit counter in the present embodiment, and its count value exported is b4:b0.
Voltage regulator 507 receives external reference voltage vref, and the magnitude of voltage of internal reference voltage vrefoc of the count value regulation output exported according to counter 506, internal reference voltage vrefoc reduces when count value increases, and internal reference voltage vrefoc increases when count value reduces.
Fig. 6 shows the working signal sequential chart of the circuit of the raising switch power supply output current line regulation of the present embodiment, composition graphs 5 and Fig. 6, in each switch periods, the rising edge of the external timing signal clk that oscillator 508 produces is to rest-set flip-flop 510 set, make its Output rusults be logical one, namely switch controlling signal gate is logical one; Switch controlling signal gate transfers to the control end of switch 501 after overdrive circuit 511 drives, and switch 501 is opened.The electric current flowing through switch 501 forms sampled voltage cs at the two ends of sampling resistor 503, and the size of sampled voltage cs reflects the size of current flowing through switch 501.Sampled voltage cs is through voltage amplifier 512 pre-amplification, and the sampled voltage vcs after pre-amplification transfers to the first input end of the first voltage comparator 509.The internal reference voltage vrefoc of the second input receiver voltage adjuster 507 generation of the first voltage comparator 509.
When the sampled voltage vcs after pre-amplification reaches internal reference voltage vrefoc, the output voltage oc of the first voltage comparator 509 overturns, and rest-set flip-flop 510 is resetted, and namely switch controlling signal gate is reset to logical zero, and then switch 501 is disconnected.Thus in each switch periods, the crest voltage on sampling resistor 503 can be expressed as:
Wherein, A is the multiplication factor of voltage amplifier 511, and Vin is the input voltage of input transformer 502 primary side coil, and Tdelay is the propagation delay time of the first voltage comparator 509 and drive circuit 511, Rcs is the resistance value of sampling resistor 503, and L is transformer 502 primary side inductance value.
In each switch periods, when the rising edge of switch controlling signal gate arrives, pulse-generating circuit 505 produces reseting pulse signal rst, and the direction controlling of counter 506 resets by this reseting pulse signal rst; When the trailing edge of switch controlling signal gate arrives, the time of delay that pulse-generating circuit 505 is being preset produces counting pulse signal clkc after tdgate, and this counting pulse signal clkc transfers to counter 506.In addition, when the trailing edge of switch controlling signal gate arrives, second voltage comparator 504 compares the sampled voltage vcs after pre-amplification and external reference voltage vref, if the sampled voltage vcs after pre-amplification reaches the magnitude of voltage of external reference voltage vref, the then Output rusults upset of the second voltage comparator 504, direction control signal updn is set to logic l, represent that the current counting direction of counter 506 is for upwards to increase progressively, when counting pulse signal clkc arrives, the count value of counter 506 increases by 1.Based on the count value increased, voltage regulator 507 reduces the magnitude of voltage of the internal reference voltage vrefoc exported, thus reduces the crest voltage cspk in next cycle on sampling resistor 503.
Otherwise, if when the trailing edge of switch controlling signal gate arrives, sampled voltage after pre-amplification does not reach external reference voltage vref, then the second voltage comparator 504 can not overturn, direction control signal updn is logical zero, represent that current counting direction is for successively decrease downwards, when counting pulse signal clkc arrives, the count value of counter 506 reduces 1.Based on the count value reduced, voltage regulator 507 increases the magnitude of voltage of the internal reference voltage vrefoc exported, thus increases the crest voltage cspk in next cycle on sampling resistor 503.
In the state of the equilibrium, due to the regulating action of the second voltage comparator 504, the peak electricity pressure drop of the sampled voltage vcs after pre-amplification outside portion's reference voltage vref up and down between swing, the size of its mean value equals external reference voltage vref, and the crest voltage cspk therefore on sampling resistor 503 can be expressed as:
The peak current flowing through switch 501 can be expressed as:
It should be noted that, have ignored the impact of the time of delay of the second voltage comparator 504 in above-mentioned formula (6) and (7), such as the second voltage comparator 504 is designed to high-speed comparator, the impact that its time of delay brings can be ignored.
In addition, as a nonrestrictive example, in the present embodiment, counter 506 upwards incremental count when direction control signal updn is logical one, correspondingly control voltage adjuster 507 reduces the magnitude of voltage of the internal reference voltage exported; Counter 506 is downward countdown when direction control signal updn is logical zero, correspondingly control voltage adjuster 507 increases the magnitude of voltage of the internal reference voltage exported, but the specific implementation of counter 506 and voltage regulator 507 is including but not limited to above-mentioned design.
Fig. 7 shows the detailed circuit diagram of the pulse-generating circuit in the circuit of the raising switch power supply output current line regulation of the present embodiment, comprising: the first not gate 701, its input receiving key control signal gate; First delayer 702, its input is connected with the output of the first not gate 701; First NAND gate 703, its first input end is connected with the output of the first delayer 702, and its second input receives this switch controlling signal gate; Second not gate 704, its input connects the output of the first NAND gate 703, and its output produces reseting pulse signal rst; Second delayer 705, its input receiving key control signal gate; 3rd not gate 706, its input connects the output of the second delayer 705; 4th not gate 707, its input connects the output of the 3rd not gate 706; 3rd delayer 708, its input connects the output of the 4th not gate 707; Second NAND gate 709, its first input end connects the output of the 3rd delayer 708, and its second input connects the output of the 3rd not gate 706; 5th not gate 710, its input connects the output of the second NAND gate 709, and its output produces counting pulse signal clkc.
When the rising edge of switch controlling signal gate arrives, first logic high arrives the input of the first NAND gate 703, simultaneously through the delayed action of the first delayer 702, another input of first NAND gate 703 becomes low level from high level through the time of delay of the first delayer 702 after td, two inputs of the first NAND gate 703 can occur that high level lasting time is td simultaneously before this, therefore a undersuing is produced at the output of the first NAND gate 703, by producing reseting pulse signal rst after the second not gate 704, it is positive pulse signal, width is td.At the trailing edge of switch controlling signal gate, through the second delayer 705 and the 3rd not gate 706 delay and anti-phase after, the trailing edge of switch controlling signal gate produces rising edge at the output of the 3rd not gate 706 through time of delay after tdgate, the functional equivalent of gate 707 to 710 in the function of gate 701 to 704, thus produces counting pulse signal clkc at the output of the 5th not gate 710.
As a nonrestrictive example, in the present embodiment, reseting pulse signal rst and counting pulse signal clkc is positive pulse, and width is designated as td (being about 100ns in the present embodiment).In addition, counting pulse signal clkc produces after being the predetermined time delay tdgate after the trailing edge of switch controlling signal gate, in the present embodiment, predetermined time delay tdgate is that the design of 2.5 μ about s, td and tdgate there is no strict restriction, also can be other values.
Fig. 8 shows the detailed circuit diagram of the counter in the present embodiment, comprising: the second rest-set flip-flop 801, its set input receive direction control signal updn, and its RESET input receives reseting pulse signal rst; Multiple counting units 802 ~ 806 of contacting successively; 6th NAND gate 807, its first to the 3rd input connects the second rest-set flip-flop 801 and the positive output end of the first JK flip-flop 8061 and the J input of the first JK flip-flop 8061 respectively; 7th NAND gate 808, its first to the 3rd input connects the second rest-set flip-flop 801 and the reversed-phase output of the first JK flip-flop 8061 and the J input of the first JK flip-flop 8061 respectively; 8th NAND gate 809, its first and second input connects the output of the 6th NAND gate 807 and the 7th NAND gate 808 respectively, its 3rd input count pick up pulse signal clkc; 6th not gate 810, its input is connected with the output of the 8th NAND gate 809, and its output produces internal clock signal and the input end of clock of the first JK flip-flop 8061 transferred in counting unit at different levels and the second JK flip-flop I0.
Wherein highest counting unit 806 comprises: the first JK flip-flop 8061, and its J input is connected the output of prime counting unit (being 805 in Fig. 8) with K input; For lowermost level counting unit 802, every one-level counting unit except highest counting unit 806 comprises: the second JK flip-flop I0, its J input is connected the output (for lowermost level counting unit 802, its J input and K input receive logic high level and logical one) of prime counting unit with K input; 3rd NAND gate I1, its input connects the positive output end of the second rest-set flip-flop 801 and the second JK flip-flop I0 respectively; 4th NAND gate I2, its input connects the reversed-phase output of rest-set flip-flop 801 and the second JK flip-flop I0 respectively; 5th NAND gate I3, its input connects the output of the 3rd NAND gate I1 and the 4th NAND gate I2 respectively, and its output is as the output of this grade of counting unit.
It should be noted that, the count value bit of the correspondence that individual count unit 802 ~ 806 exports produces at the positive output end of the second JK flip-flop I0 and the first JK flip-flop 8061, is followed successively by b0 ~ b4 in the present embodiment.In addition, Fig. 8 is only signal, and the quantity of counting unit can adjust as required, is not restricted to 5 shown in Fig. 8.
Counter operationally, the upwards index signal up that its counting direction produces by the positive output end of the second rest-set flip-flop 801 and downward index signal dn that reversed-phase output produces controls, when upwards index signal up is logical one, upwards incremental count when downward index signal dn is logical zero; When upwards index signal up is logical zero, downward countdown when downward index signal dn is logical one.
In each switch periods, first reseting pulse signal rst occurs that a positive pulse upwards will be set to 1 by index signal up, and whether apparent direction control signal updn occurs that positive pulse determines counting direction when a switch is off.If direction control signal updn occurs that positive pulse upwards will be set to logical one by index signal up, downward index signal dn is set to logical zero, then control counting unit 802 ~ 806 and upwards count.If direction control signal updn does not occur positive pulse during switch OFF, then upwards index signal up remains logical zero, and downward index signal dn remains logical one, and counting unit 802 ~ 806 counts downwards.6th NAND gate 807 and the 7th NAND gate 808 are for judging complete 1 and full 0 state of counter, and as b4:b0=11111, it is 0 that the 6th NAND gate 807 exports upstop, are stoped by counting clock signal clkc thus stop counter upwards to count; As b4:b=00000, the output dnstop of the 7th NAND gate 808 is 0, is stoped by counting clock signal clkc thus stops counter counts downward.
Fig. 9 shows the detailed circuit diagram of the voltage regulator of the present embodiment, comprising: the first operational amplifier 801, and its in-phase input end receives external reference voltage vref, and its inverting input is connected with its output; First resistance 802, its one end connects the output of the first operational amplifier 801, and the other end connects the output of voltage regulator, namely exports internal reference voltage vrefoc; Controllable current circuit, according to the size of the count value regulation output electric current that counter exports, and transfers to the output of voltage regulator by output current.
Wherein, controllable current circuit can comprise: multiple current mirror, the output current of each current mirror doubles successively, and wherein the output of each current mirror controls respectively by one the output that transistor is connected to voltage regulator, each each bit controlling the grid difference count pick up value of transistor.In the present embodiment, transistor M1 and M2 to M6 form respectively 5 current mirrors, its current ratio is followed successively by 1: 1,2: 1,4: 1,8: 1,16: 1, each current mirror shares same transistor M1, transistor M1 receives reference current Iref, thus makes electric current that in each current mirror, M2 to M6 exports be respectively 1 times, 2 times, 4 times, 8 times and 16 times of reference current Iref.The output (source electrode or drain electrode) of transistor M2 is connected with and controls transistor M7, the lowest order b0 of the count value that the grid receive counter controlling transistor M7 exports, whether the electric current that namely the lowest order b0 of count value can control in transistor M2 circulates, similarly, other of count value transfer to the grid controlling transistor M8 ~ M11 respectively, in order to control other current mirrors whether output current, thus control flow check is through the electric current of the first resistance 802, namely control the magnitude of voltage of the internal reference voltage vrefoc that the first resistance 802 exports.The magnitude of voltage of internal reference voltage vrefoc and the relation of b0 ~ b4 can be expressed as:
Vrefoc＝vref-Iref(b0+2*b1+4*b2+8*b3+16*b4)*R
Wherein, b0 ~ b4 according to count value be 0 or 1, R be the resistance value of the first resistance 802, Iref is the current value of reference current Iref, vref is the magnitude of voltage of external reference voltage vref, and the magnitude of voltage of internal reference voltage vref and the relation of count value b4:b0 are as shown in Figure 10.
It should be noted that, the bit wide of the present embodiment count value is 5, and the quantity of corresponding current mirror is also 5, but the quantity of the bit wide of count value and current mirror can adjust as required, is not limited to 5 and 5.
To sum up, circuit in the present embodiment is under steady-working state, by detection and the regulating action of the second voltage comparator, counter and voltage regulator, the peak value of sampled voltage vcs can be made to remain unchanged, thus ensure that the peak current flowing through switch is constant, significantly improve the line regulation of constant current output.Because this implementation completes by self-regulation, therefore there is very high consistency, easily ensure the consistency of batch production.
Technical solution of the present invention, except being applied to the Switching Power Supply of separate AC/DC topological structure, is equally also applicable to non-isolated switch power supply system, and in office what is the need for will accurately control all can obtain good effect in the system of peak current.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible variation and amendment, the scope that therefore protection scope of the present invention should define with the claims in the present invention is as the criterion.
Claims (8)
1. one kind is improved the circuit of switch power supply output current line regulation, the switch that described Switching Power Supply comprises transformer, contact with the primary side coil of described transformer, and the output of the described switch sampling resistor of contacting, the current conversion flowing through described switch is sampled voltage by described sampling resistor, it is characterized in that, described circuit comprises: voltage amplifier, the first voltage comparator, the second voltage comparator, pulse-generating circuit, counter, voltage regulator, the first rest-set flip-flop, wherein
Described voltage amplifier receives described sampled voltage and carries out pre-amplification to it;
The first input end of described first voltage comparator is connected with the output of described voltage amplifier, and the second input is connected with the output of described voltage regulator;
The set input of described first rest-set flip-flop receives external timing signal, and the RESET input is connected with the output of described first voltage comparator, and its output produces switch controlling signal, and described switch controlling signal transfers to the control end of described switch;
Described pulse-generating circuit receives described switch controlling signal, produces reseting pulse signal when the rising edge of described switch controlling signal arrives, and produces counting pulse signal when the trailing edge of described switch controlling signal arrives after the time of delay of presetting;
The first input end of described second voltage comparator is connected with the output of described voltage amplifier, and the second input receives external reference voltage, and its output produces direction control signal;
Described counter for clock, carries out incremental count or countdown according to described reseting pulse signal and direction control signal with described counting pulse signal;
Described voltage regulator receives described external reference voltage, the output of described voltage regulator exports internal reference voltage, the internal reference voltage of the count value regulation output that described voltage regulator exports according to described counter, described internal reference voltage reduces when described count value increases, and increases when described count value reduces.
2. the circuit of raising switch power supply output current line regulation according to claim 1, it is characterized in that, described voltage regulator comprises:
First operational amplifier, its in-phase input end receives described external reference voltage, and its inverting input is connected with its output;
First resistance, its one end connects the output of described first operational amplifier, and the other end connects the output of described voltage regulator;
Controllable current circuit, according to the size of described count value regulation output electric current, and transfers to the output of described voltage regulator by output current.
3. the circuit of raising switch power supply output current line regulation according to claim 2, it is characterized in that, described controllable current circuit comprises:
Multiple current mirror, the output current of each current mirror doubles successively, and wherein the output of each current mirror controls respectively by one the output that transistor is connected to described voltage regulator, and each grid controlling transistor receives each bit of described count value respectively.
4. the circuit of raising switch power supply output current line regulation according to claim 1, it is characterized in that, described pulse-generating circuit comprises:
First not gate, its input receives described switch controlling signal;
First delayer, its input is connected with the output of described first not gate;
First NAND gate, its first input end is connected with the output of described first delayer, and its second input receives described switch controlling signal;
Second not gate, its input connects the output of described first NAND gate, and its output produces described reseting pulse signal;
Second delayer, its input receives described switch controlling signal;
3rd not gate, its input connects the output of described second delayer;
4th not gate, its input connects the output of described 3rd not gate;
3rd delayer, its input connects the output of described 4th not gate;
Second NAND gate, its first input end connects the output of described 3rd delayer, and its second input connects the output of described 3rd not gate;
5th not gate, its input connects the output of described second NAND gate, and its output produces described counting pulse signal.
5. the circuit of raising switch power supply output current line regulation according to claim 1, it is characterized in that, described counter comprises:
Second rest-set flip-flop, its set input receives described direction control signal, and its RESET input receives described reseting pulse signal;
Multiple counting units of contacting successively;
6th NAND gate;
7th NAND gate;
8th NAND gate;
6th not gate;
Wherein, the highest counting unit in described multiple counting unit comprises:
First JK flip-flop, its J input is connected the output of prime counting unit with K input; Every one-level counting unit in described multiple counting unit except described highest counting unit comprises:
Second JK flip-flop, its J input is connected the output of prime counting unit with K input, the J input of the second JK flip-flop of lowermost level counting unit and K input receive logic high level;
3rd NAND gate, its input connects the positive output end of described second rest-set flip-flop and the second JK flip-flop respectively;
4th NAND gate, its input connects the reversed-phase output of described rest-set flip-flop and the second JK flip-flop respectively;
5th NAND gate, its input connects the output of described 3rd NAND gate and the 4th NAND gate respectively, and its output is as the output of this grade of counting unit;
Wherein, described 6th NAND gate, its first to the 3rd input connects the positive output end of described second rest-set flip-flop and the first JK flip-flop and the J input of described first JK flip-flop respectively;
Described 7th NAND gate, its first to the 3rd input connects the reversed-phase output of described second rest-set flip-flop and the first JK flip-flop and the J input of described first JK flip-flop respectively;
Described 8th NAND gate, its first and second input connects the output of described 6th NAND gate and the 7th NAND gate respectively, and its 3rd input receives described counting pulse signal;
Described 6th not gate, its input is connected with the output of described 8th NAND gate, and its output produces internal clock signal and the input end of clock of the first JK flip-flop transferred in counting unit at different levels and the second JK flip-flop.
6. the circuit of raising switch power supply output current line regulation according to claim 1, is characterized in that, also comprise: oscillator, for generation of described external timing signal.
7. the circuit of raising switch power supply output current line regulation according to claim 1, it is characterized in that, also comprise: drive circuit, the switch controlling signal that described rest-set flip-flop exports transfers to the control end of described switch after being driven by described drive circuit.
8. a Switching Power Supply, is characterized in that, comprises the circuit of the raising switch power supply output current line regulation according to any one of claim 1 to 7.
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| CN101562391A (en) * | 2008-04-15 | 2009-10-21 | 绿达光电股份有限公司 | Current-level decision device for a power supply device and related power supply device |
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| JP3708088B2 (en) * | 2003-03-28 | 2005-10-19 | Ｔｄｋ株式会社 | Output control method for switching power supply, output control circuit, and switching power supply |
| US9246391B2 (en) * | 2010-01-22 | 2016-01-26 | Power Systems Technologies Ltd. | Controller for providing a corrected signal to a sensed peak current through a circuit element of a power converter |
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| US5534770A (en) * | 1992-12-17 | 1996-07-09 | Texas Instruments Incorporated | Method and device for resistive load compensation |
| CN101562391A (en) * | 2008-04-15 | 2009-10-21 | 绿达光电股份有限公司 | Current-level decision device for a power supply device and related power supply device |
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