CN103390657A - Selective grid of silicon nanometer column array photocell and preparation method of selective grid - Google Patents
Selective grid of silicon nanometer column array photocell and preparation method of selective grid Download PDFInfo
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Abstract
The invention discloses a selective grid of a silicon nanometer column array photocell and a preparation method of the selective grid. A photocell surface with no etched nanometer column array is covered with the selective grid, and silicon nanometer column arrays formed through etching are arranged on other photocell surfaces besides the surface covered with the selective grid. According to the method, silicon surface selective nanometer texturing is completed with an ultraviolet light etching technology, a self-assembly cesium chloride nanometer island technology and a micro processing plasma etching technology, a P-N junction structure is manufactured with a thermal diffusion method, and the selective grid of the nanometer texturing photocell is manufactured through an overlay alignment technology and a vacuum coating technology. The selective grid has the characteristics that the cost is low, the technological adaptability is higher, and reflection is reduced by fully using nanometer texturing; and at the same time, the defect of bad ohmic contact caused by whole nanometer texturing of a front surface is avoided, series resistance is reduced, the ohmic contact is increased, and the photoelectric conversion efficiency of the nanometer texturing photocell is improved.
Description
Technical field
The invention belongs to micron and the little processing of Nano semiconductor, nanometer texturing photocell preparing technical field, relate in particular to photronic selectivity grid of a kind of silicon nano column array and preparation method thereof.
Background technology
Nano-array is a kind of novel surface texture, in many fields such as solar cell, LED, huge commercial Application is arranged, and the nanometer texturing has good reduction visible light reflection and improves the characteristic of spectral response.Progressively commercialization of nanometer texturing solar cell now, conventional nanometer texturing solar cell, be all with the whole texturing of front surface, and grid covers on the surface of textured silicon, the kind electrode form can not form good ohmic contact, and the electricity conversion of battery is lower.
Summary of the invention
The technical problem that (one) will solve
In view of this, main purpose of the present invention is to provide photronic selectivity grid of a kind of silicon nano column array and preparation method thereof,, to form good ohmic contact, improves the electricity conversion of battery.
(2) technical scheme
For achieving the above object, the invention provides the photronic selectivity grid of a kind of silicon nano column array, this selectivity grid is the photocell surface that covers the nano column array that is not etched, and is the silicon nano column array that is etched and forms on the photocell surface except covering this selectivity grid.
In such scheme, described photocell surface consists of gate regions and nanometer texture district, and this gate regions obtains by the ultraviolet photolithographic technology, and this nanometer texture district obtains by Nano Islands Lithography.
In such scheme, described gate regions comprises silicon gate figure and silicon alignment mark, before the nanometer texturing, adopt the ultraviolet photolithographic technology to prepare photoresist gate patterns and photoresist alignment mark at silicon chip surface, photoresist gate patterns and photoresist alignment mark shield in nanometer texturing process; After the nanometer texturing, remove photoetching offset plate figure, expose silicon gate figure and silicon alignment mark.
In such scheme, described nanometer texture district is the zone that nano column array is arranged, and selects the cesium chloride self-assembling technique to complete, and cesium chloride structure is formed at silicon face to justify the island structure form, and circle island diameter dimension is in the 50-1500 nanometer.
In such scheme, described cesium chloride island structure, as the plasma etching mask,, by plasma etching technology, is transferred to the cesium chloride island structure on silicon materials, forms the silicon nanometer column structure with cesium chloride island structure identical patterns.
In such scheme, described silicon nanometer column structure height and pattern were controlled by power, gas flow, pressure and the time of plasma etching, formed silicon nanometer cylinder or conical structure, were highly the 0.2-10 micron.
In such scheme, this selectivity grid utilizes hollow out metal mask coating technique to realize, this hollow out metal mask is the nickel sheet metal, formed by vacancy section and entity district, vacancy section comprises the hollow out figure identical with silicon chip surface selectivity grid and the hollow out figure of alignment mark, and the entity district is the nickel metal.This selectivity grid is selected titanium, silver metal, by vacuum coating technology, completes.
For achieving the above object, the present invention also provides the manufacture method of the photronic selectivity grid of a kind of silicon nano column array, and the method comprises:
Produce photoresist gate patterns and photoresist alignment mark figure at silicon chip surface;
, at silicon chip surface growth one deck cesium chloride film, form cesium chloride nanometer circle island structure at silicon chip surface after developing;
The silicon chip that effects on surface has photoresist gate patterns and cesium chloride nanometer circle island structure carries out plasma etching, in the part that there is no the photoresist protection, obtains silicon nanometer column structure;
Remove remaining cesium chloride nanometer island and photoresist, expose the silicon gate figure and silicon alignment mark and the silicon nano column array that are not etched;
Silicon nanometer column structure is carried out the phosphorus oxychloride diffusion, form the P-N junction structure;
Silicon gate figure on hollow out metal mask plate gate patterns and silicon chip, by alignment mark,, with method evaporation titanium and the silver of vacuum coating, is made the selectivity grid.
In such scheme, describedly at silicon chip surface, producing photoresist gate patterns and photoresist alignment mark figure, is to adopt photoetching technique gluing, front baking, exposure and development at silicon chip surface, produces photoresist gate patterns and photoresist alignment mark figure.
In such scheme, described photoresist alignment mark graphical distribution, at four jiaos of the photoresist gate patterns, is the cross figure, shields in nanometer texturing process.
In such scheme, described silicon nanometer column structure is carried out phosphorus oxychloride diffusion is the method that adopts thermal diffusion.
(3) beneficial effect
Can find out from technique scheme, the present invention has following beneficial effect:
1, the photronic selectivity grid of this novel silicon nano column array provided by the invention, the silicon chip under metal gates covers remains intact silicon structure, there is no the etching nano column array, in the zone except grid, has prepared nano column array.This electrode structure is when taking full advantage of the textured characteristic that reduces to reflect of nanometer, the bad drawback of ohmic contact of also having avoided the whole nanometer texturings of front surface to bring, reduce series resistance, increase ohmic contact, improve the photoelectric conversion efficiency of solar cell.
2, the photronic selectivity grid of this novel silicon nano column array provided by the invention, have low cost and stronger Technological adaptability energy, when taking full advantage of the characteristic that the nanometer texturing reduces to reflect, the bad drawback of ohmic contact of also having avoided the whole nanometer texturings of front surface to bring, can reduce series resistance, increase ohmic contact, improve the photoelectric conversion efficiency of nanometer texturing solar cell.
3, the manufacture method of the photronic selectivity grid of this novel silicon nano column array provided by the invention, to utilize ultraviolet photolithographic technology, cesium chloride self assembly and reactive ion etching technology, alignment and vacuum coating technology to complete, can increase ohmic contact, reduce series resistance, improve the photoelectric conversion efficiency of solar cell, have low cost and stronger Technological adaptability energy, can be applied to multiple nanometer texturing photocell, be easy to be extended and applied.
Description of drawings
Fig. 1 is the method flow diagram of the photronic selectivity grid of making silicon nano column array provided by the invention;
Fig. 2 to Fig. 9 is the process chart according to the photronic selectivity grid of making silicon nano column array of the embodiment of the present invention;
Figure 10 is the I-V test curve (I-short circuit current, U-open circuit voltage) according to the embodiment of the present invention;
Figure 11 is according to the nanometer texturing grid (left side) of the embodiment of the present invention and the SEM figure of nanometer texturing selectivity grid form (right side) titanium and silver-colored coverage rate.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
The present invention is to provide photronic selectivity grid of a kind of silicon nano column array and preparation method thereof, this selectivity grid is the photocell surface that covers the nano column array that is not etched, and is the silicon nano column array that is etched and forms on the photocell surface except covering this selectivity grid.Wherein, the photocell surface consists of gate regions and nanometer texture district, and this gate regions obtains by the ultraviolet photolithographic technology, and this nanometer texture district obtains by Nano Islands Lithography.
Gate regions comprises silicon gate figure and silicon alignment mark, before the nanometer texturing, adopt the ultraviolet photolithographic technology to prepare photoresist gate patterns and photoresist alignment mark at silicon chip surface, photoresist gate patterns and photoresist alignment mark shield in nanometer texturing process; After the nanometer texturing, remove photoetching offset plate figure, expose silicon gate figure and silicon alignment mark.Nanometer texture district is the zone that nano column array is arranged, and selects the cesium chloride self-assembling technique to complete, and cesium chloride structure is formed at silicon face to justify the island structure form, and circle island diameter dimension is in the 50-1500 nanometer.The cesium chloride island structure, as the plasma etching mask,, by plasma etching technology, is transferred to the cesium chloride island structure on silicon materials, forms the silicon nanometer column structure with cesium chloride island structure identical patterns.Silicon nanometer column structure height and pattern were controlled by power, gas flow, pressure and the time of plasma etching, formed silicon nanometer cylinder or conical structure, were highly the 0.2-10 micron.
This selectivity grid utilizes hollow out metal mask coating technique to realize, this hollow out metal mask is the nickel sheet metal, consist of vacancy section and entity district, vacancy section comprises the hollow out figure identical with silicon chip surface selectivity grid and the hollow out figure of alignment mark, and the entity district is the nickel metal.This selectivity grid is selected titanium, silver metal, by vacuum coating technology, completes.
The present invention adopts ultraviolet photolithographic technology, self assembly cesium chloride nanometer island technology and micro-machined plasma etching technology to complete the texturing of silicon face selectivity nano, method through thermal diffusion is made the P-N junction structure, produce the photronic selectivity grid of nanometer texturing by overlay alignment technology and vacuum coating technology again, specifically as shown in Figure 1, its concrete steps are as follows:
Step 1: at silicon chip surface, produce photoresist gate patterns and photoresist alignment mark figure;
Step 2:, at silicon chip surface growth one deck cesium chloride film, form cesium chloride nanometer circle island structure at silicon chip surface after developing;
Step 3: the silicon chip that effects on surface has photoresist gate patterns and cesium chloride nanometer circle island structure carries out plasma etching, in the part that there is no the photoresist protection, obtains silicon nanometer column structure;
Step 4: remove remaining cesium chloride nanometer island and photoresist, expose the silicon gate figure and silicon alignment mark and the silicon nano column array that are not etched;
Step 5: silicon nanometer column structure is carried out the phosphorus oxychloride diffusion, form the P-N junction structure;
Step 6: the silicon gate figure on hollow out metal mask plate gate patterns and silicon chip, by alignment mark,, with method evaporation titanium and the silver of vacuum coating, is made the selectivity grid.
Wherein, at silicon chip surface, producing photoresist gate patterns and photoresist alignment mark figure, is to adopt photoetching technique gluing, front baking, exposure and development at silicon chip surface, produces photoresist gate patterns and photoresist alignment mark figure.Photoresist alignment mark graphical distribution, at four jiaos of the photoresist gate patterns, is the cross figure, shields in nanometer texturing process.It is the method that adopts thermal diffusion that silicon nanometer column structure is carried out the phosphorus oxychloride diffusion.
Fig. 2 to Fig. 9 shows the process chart according to the photronic selectivity grid of making silicon nano column array of the embodiment of the present invention, and its concrete technology is as follows:
As shown in Figure 2, the silicon chip that silicon materials select semi-conductor industry to use, thickness 0.2-0.5 millimeter, P type, resistivity are 1-3 Ω cm, surface is burnishing surface or hair side.The textured manufacture method of this selectivity nano be above-mentioned Wafer Cleaning is clean after, 3000 rev/mins of spin-coating method resist coatings (AZ1818), front baking 90 degree 25 minutes, thickness is 2 microns, the exposure of ultraviolet photolithographic machine is after 20 seconds, be to develop 2 minutes in 3/1000ths. seven NaOH developer solution in concentration, as shown in Figure 3, at silicon chip surface, obtain photoresist gate patterns and photoresist alignment mark.
As shown in Figure 4, the silicon chip with photoetching offset plate figure is put into the vacuum coating cavity, thermal evaporation cesium chloride film, thickness 200-7000 dust.After the cesium chloride film has plated, to the gas that passes into certain humidity in cavity, relative humidity is 10%-70%, development cesium chloride film, cesium chloride is reunited under the effect of humidity gas, at silicon chip surface, form the nanometer cesium chloride peninsular structure of similar water droplet one by one.
As shown in Figure 5,, take the cesium chloride island structure of reuniting as mask, utilize the plasma etching technology etch silicon, thereby cesium chloride structure is transferred on silicon face, the part of photoresist protection is not etched.
As shown in Figure 6, after the silicon face etching was completed, sample was put into water 2 minutes, the cesium chloride of remnants can be dissolved, the NaOH that is placed in concentration again and is ten Percent obtains selectivity nano texturing silicon face after removing photoresist in liquid and removing photoetching offset plate figure, comprises gate regions and nanometer texture district.Gate regions comprises again silicon gate figure and silicon alignment mark, is to be subject to photoresist protect and be not etched, the not impaired zone of lattice.The silicon gate figure is the silicon chip part of reserving for preparing grid, the silicon alignment mark is the mark of hollow out metal mask plate gate patterns and silicon gate graphs coincide, when each hollow out metal mask plate alignment mark all overlapped with the silicon alignment mark, hollow out metal mask plate gate patterns obtained to overlap with the silicon gate figure.Nanometer texture district is that diameter is the 50-1500 nanometer, is highly the nano column array of 0.2-10 micron.
Then, as shown in Figure 7, with the method for thermal diffusion, make the P-N junction structure, liquid phosphorus oxychloride is carried and is entered in the diffusion furnace furnace chamber by nitrogen, and phosphorus atoms, because thermal diffusion is moved into matrix, forms the P-N knot when high temperature.
Finally, as shown in Figure 8, utilize hollow out metal mask coating technique to prepare metal gates.The hollow out metal mask plate is a kind of nickel sheet metal, formed by vacancy section and entity district, vacancy section is the figure of needed hollow out, comprise that the hollow out figure (metal mask plate gate patterns) of the grid identical with silicon chip surface and the hollow out figure (metal mask plate alignment mark) of alignment mark form, the entity district is the nickel metal, and the zone except figure all belongs to nickel metal solid district.Before making electrode, at body formula operation microscopically, hollow out metal mask alignment mark is overlapped with the silicon alignment mark of silicon chip surface, guarantee that with this metal mask plate gate patterns and Si-gate line graph overlap, and fixing, like this, the silicon photocell surface only has silicon gate figure and silicon alignment mark out exposed by the vacancy section of hollow out metal mask plate, and the nanometer texture district on silicon photocell surface is covered by the entity district of hollow out metal mask plate fully.
As shown in Figure 9, with the method for vacuum coating, Evaporation preparation grid, namely in the vacuum coating cavity, at the silicon gate patterned surface of hollow out metal mask plate and exposure, the titanium adhesion layer of Evaporation preparation 40 nanometers and the silver metal layer of 3 microns.
Separate hollow out metal mask plate and silicon photocell, so just the photronic selectivity grid of silicon nano column array has been completed in preparation, and namely grid covers the silicon face that remains intact, and there is no the etching nano column array, increases ohmic contact, reduces lattice defect.Prepare nano column array in the zone except grid line, played the effect that reduces to reflect.
Embodiment
Describe the method for the photronic selectivity grid of making silicon nano column array provided by the invention in detail below in conjunction with a specific embodiment, the method comprises the following steps:
Step 1: at silicon chip surface spin-coating method resist coating AZ1818,3000 rev/mins, 90 degrees centigrade of front bakings 25 minutes, photoresist thickness is 2 microns.
Step 2: the ultraviolet photolithographic mask version of gate patterns is covered 1 silicon chip surface that scribbles photoresist, ultraviolet photolithographic machine exposure 20 seconds, 3/1000ths. seven NaOH developing liquid developing 2 minutes, obtain photoresist gate patterns and photoresist alignment mark figure at silicon chip surface.
Step 3: step 2 surface is had the method evaporation cesium chloride film of the silicon chip surface of photoetching offset plate figure with vacuum coating, film thickness 200 nanometers.
Step 4: it is 40% ventilation cavity that the silicon chip of the surperficial evaporation cesium chloride of step 3 film is put into humidity, and humidity, by the wet gas flow control that passes into cavity, was developed 30 minutes under this damp condition, at silicon chip surface, forms cesium chloride nanometer island structure.Cesium chloride nanometer island average diameter 400 nanometers.
Step 5: have the silicon chip of cesium chloride island structure to put into the etching cavity of plasma etching machine on step 4 surface, the etching technics parameter is pressure 5Pa, etching gas SF6 (60sccm) and C4F8 (100sccm), 400 watts of exciting powers, substrate bias power is 30 watts, etch period 5 minutes.
Step 6: will put into water after the silicon chip extracting in step 5, soaked 1 minute, remaining cesium chloride nanometer island structure on silicon chip is dissolved.
Step 7: with the NaOH of putting into 10/1000ths after the silicon chip extracting in step 6 liquid that removes photoresist, 2 minutes, obtain selectivity nano texturing silicon face, be that silicon gate figure and silicon alignment mark part are not etched, remainder is nanometer texture district, etch the silicon nano column array, average diameter is 350 nanometers approximately, 1.5 microns of height.Long 1 millimeter of silicon gate pattern line, wide 200 microns, the silicon alignment mark is the cross figure, long 500 microns of lines are wide 50 microns.
Step 8: put into 850 degree diffusion furnaces with 7 and carry out liquid source diffusion in 13 minutes, phosphorus oxychloride is brought into furnace chamber by 100sccm nitrogen, forms the P-N knot, and square resistance is 30 Ω/, and junction depth is 400 nanometers, and organizator is to the P-N junction structure.
Step 9: at body formula operation microscopically, alignment mark on the hollow out metal mask plate is overlapped respectively with the silicon alignment mark on silicon photocell surface, to realize the lip-deep silicon gate graphs coincide of hollow out metal mask plate gate patterns and silicon photocell, and be fixed.Like this, the silicon photocell surface only has silicon gate figure and silicon alignment mark out exposed by the vacancy section of hollow out metal mask plate, and the nanometer texture district on silicon photocell surface is covered by the entity district of hollow out metal mask plate fully.
Step 10: step 9 is aimed at and hollow out metal mask plate and the silicon photocell fixed are placed in the vacuum coating equipment cavity, 1 * 10
-3Under the vacuum of handkerchief, at its surperficial evaporation titanium and silver metal.Titanium and silver metal atom are by the vacancy section of hollow out metal mask plate, be deposited on the exposed silicon gate figure of silicon chip surface and silicon alignment mark zone and form titanium (thickness is 40 nanometers) and silver (thickness is 3 microns) metal level, and the nanometer texture district on silicon photocell surface is because covered by the entity district of hollow out metal mask plate fully, and is not deposited titanium and silver metal atom.
Step 11: separating step 10 hollow out metal mask plate and silicon photocells, so just made the photronic selectivity grid of silicon nano column array, long 1 millimeter of lines, wide 200 microns.
After the photronic selectivity grid of this silicon nano column array that completes, the photronic electricity conversion of this silicon nano column array to be tested, concrete test result is as follows:
Figure 10 is at AM1.5G (1000W/m
2At25 ℃) the solar cell I-V test curve under the solar spectrum simulator, concrete battery behavior parameter is in Table 1, three kinds of batteries be respectively surface do not carry out the textured solar cell of nanometer, surface all the textured solar cells of nanometer be that grid part also has nanometer texturing and nanometer texturing selectivity grid solar cell, area is 1 square centimeter.At first this nanometer texturing can reduce reflection, improves the utilance of solar photon, so short circuit current does not all have textured battery apparently higher than surface.For the textured battery of nanometer, after adopting the selectivity grid structure, because the electrode ohmic contact is good, series resistance reduces, and makes open circuit voltage, short circuit current and fill factor, curve factor all increase, and the photoelectric conversion conversion efficiency rises to 15.37% by 13.28%.
Table 1
Figure 11 is the contrast of nanometer texturing grid and selectivity grid, and the metal electrode that covers nanostructured surface shows as continuous not, level and smooth not.And after making selectivity grid form, metal electrode becomes continuously and is level and smooth, is conducive to form good ohmic contact.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (12)
1. photronic selectivity grid of silicon nano column array, it is characterized in that, this selectivity grid is the photocell surface that covers the nano column array that is not etched, and is the silicon nano column array that is etched and forms on the photocell surface except covering this selectivity grid.
2. the photronic selectivity grid of silicon nano column array according to claim 1, it is characterized in that, described photocell surface consists of gate regions and nanometer texture district, and this gate regions obtains by the ultraviolet photolithographic technology, and this nanometer texture district obtains by Nano Islands Lithography.
3. the photronic selectivity grid of silicon nano column array according to claim 2, it is characterized in that, described gate regions comprises silicon gate figure and silicon alignment mark, before the nanometer texturing, adopt the ultraviolet photolithographic technology to prepare photoresist gate patterns and photoresist alignment mark at silicon chip surface, photoresist gate patterns and photoresist alignment mark shield in nanometer texturing process; After the nanometer texturing, remove photoetching offset plate figure, expose silicon gate figure and silicon alignment mark.
4. the photronic selectivity grid of silicon nano column array according to claim 2, it is characterized in that, described nanometer texture district is the zone that nano column array is arranged, select the cesium chloride self-assembling technique to complete, cesium chloride structure is formed at silicon face to justify the island structure form, and circle island diameter dimension is in the 50-1500 nanometer.
5. the photronic selectivity grid of silicon nano column array according to claim 4, it is characterized in that, described cesium chloride island structure is as the plasma etching mask, pass through plasma etching technology, the cesium chloride island structure is transferred on silicon materials, formed the silicon nanometer column structure with cesium chloride island structure identical patterns.
6. the photronic selectivity grid of silicon nano column array according to claim 4, it is characterized in that, described silicon nanometer column structure height and pattern were controlled by power, gas flow, pressure and the time of plasma etching, forming silicon nanometer cylinder or conical structure, is highly the 0.2-10 micron.
7. the photronic selectivity grid of silicon nano column array according to claim 1, it is characterized in that, this selectivity grid utilizes hollow out metal mask coating technique to realize, this hollow out metal mask is the nickel sheet metal, formed by vacancy section and entity district, vacancy section comprises the hollow out figure identical with silicon chip surface selectivity grid and the hollow out figure of alignment mark, and the entity district is the nickel metal.
8. the photronic selectivity grid of silicon nano column array according to claim 7, is characterized in that, this selectivity grid is selected titanium, silver metal, by vacuum coating technology, completes.
9. the manufacture method of the photronic selectivity grid of silicon nano column array, is characterized in that, the method comprises:
Produce photoresist gate patterns and photoresist alignment mark figure at silicon chip surface;
, at silicon chip surface growth one deck cesium chloride film, form cesium chloride nanometer circle island structure at silicon chip surface after developing;
The silicon chip that effects on surface has photoresist gate patterns and cesium chloride nanometer circle island structure carries out plasma etching, in the part that there is no the photoresist protection, obtains silicon nanometer column structure;
Remove remaining cesium chloride nanometer island and photoresist, expose the silicon gate figure and silicon alignment mark and the silicon nano column array that are not etched;
Silicon nanometer column structure is carried out the phosphorus oxychloride diffusion, form the P-N junction structure;
Silicon gate figure on hollow out metal mask plate gate patterns and silicon chip, by alignment mark,, with method evaporation titanium and the silver of vacuum coating, is made the selectivity grid.
10. the manufacture method of the photronic selectivity grid of silicon nano column array according to claim 9, it is characterized in that, describedly at silicon chip surface, produce photoresist gate patterns and photoresist alignment mark figure, be to adopt photoetching technique gluing, front baking, exposure and development at silicon chip surface, produce photoresist gate patterns and photoresist alignment mark figure.
11. the manufacture method of the photronic selectivity grid of silicon nano column array according to claim 10; it is characterized in that; described photoresist alignment mark graphical distribution, at four jiaos of the photoresist gate patterns, is the cross figure, shields in nanometer texturing process.
12. the manufacture method of the photronic selectivity grid of silicon nano column array according to claim 10, is characterized in that, described silicon nanometer column structure is carried out phosphorus oxychloride diffusion is the method that adopts thermal diffusion.
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| CN106784130A (en) * | 2016-11-22 | 2017-05-31 | 浙江昱辉阳光能源江苏有限公司 | A kind of preparation method of nano-array solar cell |
| CN108469644A (en) * | 2018-02-28 | 2018-08-31 | 中国科学院高能物理研究所 | grating and preparation method thereof |
| CN108469644B (en) * | 2018-02-28 | 2019-10-29 | 中国科学院高能物理研究所 | Grating and preparation method thereof |
| CN110729372A (en) * | 2019-09-29 | 2020-01-24 | 苏州大学 | Narrow-band near-infrared thermal electron photoelectric detector based on embedded grating structure |
| CN112490115A (en) * | 2020-12-01 | 2021-03-12 | 苏州大学 | Transparent flexible monocrystalline silicon material and preparation method thereof |
| CN113745376A (en) * | 2021-09-08 | 2021-12-03 | 深圳市思坦科技有限公司 | Light emitting chip processing method, light emitting chip assembly, display device and light emitting device |
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