CN103390605B - Inductance - Google Patents
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- CN103390605B CN103390605B CN201210139654.3A CN201210139654A CN103390605B CN 103390605 B CN103390605 B CN 103390605B CN 201210139654 A CN201210139654 A CN 201210139654A CN 103390605 B CN103390605 B CN 103390605B
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Abstract
The invention discloses a kind of inductance, comprise inductance coil and substrat structure.Substrat structure comprises: the P type doped region that the employing photoetching of P type semiconductor substrate, N-type epitaxy layer and multiple strip structure and ion implantation technology are formed.The degree of depth of P type doped region is more than or equal to the thickness of N-type epitaxy layer.N-type epitaxy layer is separated into multiple N-type doped region by P type doped region, and forms the structure that N-type doped region and P type doped region be alternately arranged.The N-type doped region be alternately arranged and P type doped region can form depletion region in the substrate, make substrate be high-impedance state, thus can block substrate eddy current; The parasitic capacitance of substrate also can be reduced in depletion region, can improve the quality factor of device.The present invention does not need deep trench isolation technique, and process costs is low.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit, particularly relate to a kind of inductance.
Background technology
In semiconductor integrated circuit, as in radio-frequency devices, usually to use inductance, inductance is integrated in same Semiconductor substrate together with other semiconductor device.In prior art, inductance is generally be formed at Semiconductor substrate as silicon substrate and is separated with one deck insulating medium layer between Semiconductor substrate mutually.Can produce magnetic field when inductance making current, the magnetic field of inductance can pass perpendicularly through Semiconductor substrate, and forms the eddy current contrary with the metal electric flow path direction of upper strata inductance in Semiconductor substrate particularly semiconductor substrate surface.Eddy current not only can bring eddy current loss, and eddy current also can produce an induced field, and its direction is contrary with the direction that spiral inductance produces magnetic field, and this can reduce the inductance value of inductance, reduces the quality factor of inductance.
Therefore needing employing way to block above-mentioned eddy current, being generally by improving the stop realizing eddy current to the structure of Semiconductor substrate in prior art, as shown in Figure 1, is the structural representation of the first inductance existing; The inductance coil 4 of the first inductance existing is formed at the top of P type semiconductor substrate 1 as P-type silicon substrate, between Semiconductor substrate 1 and described inductance coil 4, isolation has oxide layer 3, deep trench 2 is formed, filling oxide layer in deep trench 2 in Semiconductor substrate 1.The first inductance existing adopts the substrat structure of deep trench to block the Be very effective of eddy current, but process costs is relatively high.
As shown in Figure 2, be the structural representation of existing the second inductance; The inductance coil 13 of existing the second inductance is formed at the top of P type semiconductor substrate (PSUB) 11 as P-type silicon substrate.In Semiconductor substrate 11, be formed with N trap (NWELL) 12, utilize N trap 12 to block substrate eddy current.But the shortcoming of existing the second inductance is, because the concentration ratio P type semiconductor substrate 11 of N trap 12 is high a lot, P type semiconductor substrate 11 between the N trap 12 formed and inductance coil 13 can form extra parasitic capacitance, inductance coil 13 is increased with the parasitic capacitance of P type semiconductor substrate 11, counteract the quality factor that part improves so to a certain extent, also can reduce resonance frequency.Above-mentioned parasitic capacitance, can shown in reference diagram 6, and substrate networks equivalent electric circuit goes out by dotted line collimation mark in figure 6, includes the parasitic capacitance C of Semiconductor substrate in substrate networks equivalent electric circuit
si1, C
si2, C
si3with stray inductance R
si1, R
si2, R
si3, the parasitic capacitance C between Semiconductor substrate and inductance coil
ox1, C
ox2, C
ox3.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of inductance, can block substrate eddy current, improves the quality factor of device, and can not increase cost.
For solving the problems of the technologies described above, inductance provided by the invention comprises inductance coil and substrat structure, described inductance coil is positioned at above described substrat structure, and described inductance coil and described substrat structure is isolated one deck insulating medium layer, described substrat structure comprises:
One P type semiconductor substrate.
One is formed at the N-type epitaxy layer in described Semiconductor substrate.
The P type doped region of multiple strip structure, each described P type doped region is all the ion implanted region defined by photoetching process, each described P type doped region also contacts with described Semiconductor substrate through described N-type epitaxy layer, and the degree of depth of each described P type doped region is more than or equal to the thickness of described N-type epitaxy layer; Described N-type epitaxy layer is separated into multiple N-type doped region by each described P type doped region, and form the structure that described N-type doped region and described P type doped region be alternately arranged, each described P type doped region and its contiguous described N-type doped region composition PN junction, the described N-type doped region be alternately arranged and described P type doped region to be positioned at immediately below described inductance coil and for reducing eddy current.
Further be improved to, the region area of the described N-type doped region be alternately arranged and described P type doped region is more than or equal to the area of described inductance coil.
Further be improved to, described inductance coil is single-ended inductor, differential inductance, laminated inductance or transformer.
Further be improved to, overlook on face perpendicular to described Semiconductor substrate, the strip structure of each described P type doped region is arranged in parallel; Or, the arrangement architecture of each described P type doped region is made up of multiple separation structure arranged in parallel, the strip structure of each described P type doped region in each described separation structure arranged in parallel is arranged in parallel, and the strip structure of each described P type doped region between each adjacent separation structure described arranged in parallel is vertical.
Further be improved to, be formed on the semiconductor substrate for being drawn described P type doped region and making the first deriving structure of described P type doped region ground connection, described first deriving structure and described Semiconductor substrate are contacted and are contacted by described Semiconductor substrate and described P type doped region; Described first deriving structure is overlooked on face in a circulus surrounded by the line segment of one or more, described first deriving structure around region be greater than the region that described inductance coil covers, maintain certain intervals between the adjacent termination of each bar line segment of the circulus of described first deriving structure and make the circulus of described first deriving structure not be closed loop.
Further be improved to, the shape of the circulus of described first deriving structure is circular or polygon.
Further be improved to, described N-type epitaxy layer is formed for described N-type epitaxy layer being drawn and making described N-type epitaxy layer connect the second deriving structure of positive potential, described second deriving structure and described N-type epitaxy layer contact; Described second deriving structure is overlooked on face in a circulus surrounded by the line segment of one or more, described second deriving structure around region be greater than the region that described inductance coil covers, maintain certain intervals between the adjacent termination of each bar line segment of the circulus of described second deriving structure and make the circulus of described second deriving structure not be closed loop.
Further be improved to, the shape of the circulus of described second deriving structure is circular or polygon.
Further be improved to, when the PN junction formed in each described P type doped region and its contiguous described N-type doped region is reverse-biased, each described P type doped region and each described N-type doped region can form depletion region, under the width of each described P type doped region and the width requirement of each described N-type doped region are set to the condition that each described P type doped region and each described N-type doped region not exclusively exhaust when ensureing that each described PN junction is reverse-biased, the depletion region that each described P type doped region and each described N-type doped region are formed is the bigger the better.
The present invention by forming the N-type doped region and P type doped region that are alternately arranged on substrate, and can form depletion region in the substrate, depletion region only has space charge and do not have charge carrier, therefore depletion region can present high-impedance state, thus can block substrate eddy current; The formation of depletion region also can reduce the parasitic capacitance of substrate, thus can improve the quality factor of device.Reverse bias can also be carried out in the N-type doped region be alternately arranged and P type doped region by the present invention, can make to form depletion region in substrate and maximize, can strengthen the effect of the quality factor blocking substrate eddy current and improve device.
The present invention does not need the deep trench isolation technique adopting cost higher, but adopts based on the PN junction substrate processing on the germanium silicon technology in radio-frequency devices, so the present invention can not increase cost.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the structural representation of the first inductance existing;
Fig. 2 is the structural representation of existing the second inductance;
Fig. 3 is the cross-sectional view of the embodiment of the present invention one inductance;
Fig. 4 is the plan structure schematic diagram of the embodiment of the present invention one inductance;
Fig. 5 is the plan structure schematic diagram of the embodiment of the present invention two inductance;
Fig. 6 is the substrate networks equivalent electric circuit of inductance;
Fig. 7 is the simulation curve of the quality factor of the embodiment of the present invention one inductance.
Embodiment
As shown in Figure 3, be the cross-sectional view of the embodiment of the present invention one inductance.The embodiment of the present invention one inductance comprises inductance coil 105 and substrat structure.Described inductance coil 105 is single-ended inductor, differential inductance, laminated inductance or transformer.Described inductance coil 105 is positioned at above described substrat structure, and described inductance coil 105 and described substrat structure is isolated one deck insulating medium layer 107, insulating medium layer 107 described in the embodiment of the present invention one is silicon oxide layer.
Described substrat structure comprises:
One P type semiconductor substrate 101.
One is formed at the N-type epitaxy layer 102 in described Semiconductor substrate 101.
The P type doped region 103 of multiple strip structure, each described P type doped region 103 is all the ion implanted region defined by photoetching process, in the embodiment of the present invention, the formation process of each described P type doped region 103 can be: first adopt photoetching process to form photoresist window, each photoresist window defines the region that each described P type doped region 103 will be formed above described N-type epitaxy layer 102, and the photoresist of each photoresist window-external is as barrier layer during ion implantation; Then carry out P type ion implantation and form each described P type doped region 103.
Each described P type doped region 103 also contacts with described Semiconductor substrate 101 through described N-type epitaxy layer 102, and the degree of depth of each described P type doped region 103 is more than or equal to the thickness of described N-type epitaxy layer 102.
Described N-type epitaxy layer 102 is separated into multiple N-type doped region 102 by each described P type doped region 103, and form the structure that described N-type doped region 102 and described P type doped region 103 be alternately arranged, each described P type doped region 103 and its contiguous described N-type doped region 102 form PN junction, and the described N-type doped region 102 be alternately arranged and described P type doped region 103 to be positioned at immediately below described inductance coil 105 and for reducing eddy current.The region area of the described N-type doped region 102 be alternately arranged and described P type doped region 103 is more than or equal to or is slightly less than the area of described inductance coil.
As shown in Figure 4, be the plan structure schematic diagram of the embodiment of the present invention one inductance.Overlook on face perpendicular to described Semiconductor substrate 101, the strip structure of each described P type doped region 103 is arranged in parallel.Wherein, the region area of the described N-type doped region 102 be alternately arranged and described P type doped region 103 is greater than the area of described inductance coil 105, and the region of described inductance coil 105 is the region that dotted line institute frame goes out.
In other embodiments, the arrangement architecture of each described P type doped region 103 is made up of multiple separation structure arranged in parallel, the strip structure of each described P type doped region 103 in each described separation structure arranged in parallel is arranged in parallel, and the strip structure of each described P type doped region 103 between each adjacent separation structure described arranged in parallel is vertical.As shown in Figure 5, be the plan structure schematic diagram of the embodiment of the present invention two inductance, the arrangement architecture of each described P type doped region 103 is made up of 4 separation structures arranged in parallel.Other structure of the embodiment of the present invention two is identical with the embodiment of the present invention one.
Described Semiconductor substrate 101 is formed for being drawn described P type doped region 103 and making the first deriving structure 106 of described P type doped region 103 ground connection, described first deriving structure 106 and described Semiconductor substrate 101 are contacted and are contacted by described Semiconductor substrate 101 and described P type doped region 103.Described first deriving structure 106 is overlooked on face in a circulus surrounded by the line segment of one or more, described first deriving structure 106 around region be greater than the region that described inductance coil 105 covers, maintain certain intervals between the adjacent termination of each bar line segment of the circulus of described first deriving structure 106 and make the circulus of described first deriving structure 106 not be closed loop.The shape of the circulus of described first deriving structure 106 is circular or polygon, and shown in Fig. 4 is a polygon.
Described N-type epitaxy layer 102 is formed for described N-type epitaxy layer 102 being drawn and making described N-type epitaxy layer 102 connect the second deriving structure 107 of positive potential, described second deriving structure 107 and described N-type epitaxy layer 102 contact.Described second deriving structure 107 is overlooked on face in a circulus surrounded by the line segment of one or more, described second deriving structure 107 around region be greater than the region that described inductance coil 105 covers, maintain certain intervals between the adjacent termination of each bar line segment of the circulus of described second deriving structure 107 and make the circulus of described second deriving structure 107 not be closed loop.The shape of the circulus of described second deriving structure 107 is circular or polygon, and shown in Fig. 4 is a polygon.
By connecing positive potential at described second deriving structure 107, described first deriving structure 106 ground connection, the PN junction that each described P type doped region 103 and its contiguous described N-type doped region 102 can be made to form is reverse-biased, at this moment, each described P type doped region 103 and each described N-type doped region 102 can form depletion region, under the width of each described P type doped region 103 and the width requirement of each described N-type doped region 102 are set to the condition that each described P type doped region 103 and each described N-type doped region 102 not exclusively exhaust when ensureing that each described PN junction is reverse-biased, the depletion region that each described P type doped region 103 and each described N-type doped region 102 are formed is the bigger the better.
As shown in Figure 7, be the simulation curve of quality factor of the embodiment of the present invention one inductance.As a comparison, the simulation curve of the quality factor of existing the second inductance is also illustrated in the figure 7.For carrying out the analog simulation of the quality factor of the embodiment of the present invention one inductance, the resistance of one 2000 ohm is inserted in described N-type doped region 102 and described P type doped region 103 interface, can see, compare with existing the second inductance, the quality factor of the embodiment of the present invention one inductance improves 4%, and can see, resonance frequency also improves.In Fig. 7, it is the curve drawn when described second deriving structure 107 and described first deriving structure 106 do not add back-biased current potential.Can predict, if after adding back-biased current potential, due to the reduction of parasitic capacitance, the quality factor of inductance can improve more than 5%.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (9)
1. an inductance, comprises inductance coil and substrat structure, and described inductance coil is positioned at above described substrat structure, and described inductance coil and described substrat structure is isolated one deck insulating medium layer, it is characterized in that, described substrat structure comprises:
One P type semiconductor substrate;
One is formed at the N-type epitaxy layer in described Semiconductor substrate;
Multiple in the P type doped region overlooked in strip structure on face perpendicular to described Semiconductor substrate, each described P type doped region is all the ion implanted region defined by photoetching process, each described P type doped region also contacts with described Semiconductor substrate through described N-type epitaxy layer, and the degree of depth of each described P type doped region is more than or equal to the thickness of described N-type epitaxy layer; Described N-type epitaxy layer is separated into multiple N-type doped region by each described P type doped region, and form the structure that described N-type doped region and described P type doped region be alternately arranged, each described P type doped region and its contiguous described N-type doped region composition PN junction, the described N-type doped region be alternately arranged and described P type doped region to be positioned at immediately below described inductance coil and for reducing eddy current.
2. inductance as claimed in claim 1, is characterized in that: the region area of the described N-type doped region be alternately arranged and described P type doped region is more than or equal to the area of described inductance coil.
3. inductance as claimed in claim 1, is characterized in that: described inductance coil is single-ended inductor, differential inductance, laminated inductance or transformer.
4. inductance as claimed in claim 1, is characterized in that: overlook on face perpendicular to described Semiconductor substrate, the strip structure of each described P type doped region is arranged in parallel;
Or, the arrangement architecture of each described P type doped region is made up of multiple separation structure arranged in parallel, the strip structure of each described P type doped region in each described separation structure arranged in parallel is arranged in parallel, and the strip structure of each described P type doped region between each adjacent separation structure described arranged in parallel is vertical.
5. inductance as claimed in claim 1, it is characterized in that: be formed on the semiconductor substrate for being drawn described P type doped region and making the first deriving structure of described P type doped region ground connection, described first deriving structure and described Semiconductor substrate are contacted and contacted by described Semiconductor substrate and described P type doped region; Described first deriving structure is overlooked on face in a circulus surrounded by the line segment of one or more, described first deriving structure around region be greater than the region that described inductance coil covers, maintain certain intervals between the adjacent termination of each bar line segment of the circulus of described first deriving structure and make the circulus of described first deriving structure not be closed loop.
6. inductance as claimed in claim 5, is characterized in that: the shape of the circulus of described first deriving structure is circular or polygon.
7. inductance as claimed in claim 1, it is characterized in that: be formed in described N-type epitaxy layer for described N-type epitaxy layer being drawn and making described N-type epitaxy layer connect the second deriving structure of positive potential, described second deriving structure and described N-type epitaxy layer contact; Described second deriving structure is overlooked on face in a circulus surrounded by the line segment of one or more, described second deriving structure around region be greater than the region that described inductance coil covers, maintain certain intervals between the adjacent termination of each bar line segment of the circulus of described second deriving structure and make the circulus of described second deriving structure not be closed loop.
8. inductance as claimed in claim 7, is characterized in that: the shape of the circulus of described second deriving structure is circular or polygon.
9. inductance as claimed in claim 1, it is characterized in that: when the PN junction formed in each described P type doped region and its contiguous described N-type doped region is reverse-biased, each described P type doped region and each described N-type doped region can form depletion region, under the width of each described P type doped region and the width requirement of each described N-type doped region are set to the condition that each described P type doped region and each described N-type doped region not exclusively exhaust when ensureing that each described PN junction is reverse-biased, the depletion region that each described P type doped region and each described N-type doped region are formed is the bigger the better.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210139654.3A CN103390605B (en) | 2012-05-08 | 2012-05-08 | Inductance |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210139654.3A CN103390605B (en) | 2012-05-08 | 2012-05-08 | Inductance |
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| CN103390605A CN103390605A (en) | 2013-11-13 |
| CN103390605B true CN103390605B (en) | 2016-02-10 |
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| CN201210139654.3A Active CN103390605B (en) | 2012-05-08 | 2012-05-08 | Inductance |
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| CN103426729A (en) * | 2013-08-29 | 2013-12-04 | 上海宏力半导体制造有限公司 | Method for improving Q value of inductor which is integrated passive device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1434511A (en) * | 2002-01-25 | 2003-08-06 | 联华电子股份有限公司 | Blocking circuit for IC |
| CN1604300A (en) * | 2004-10-28 | 2005-04-06 | 复旦大学 | Optimized design method for PN junction underlay isolation on-chip inductance |
| CN101465351A (en) * | 2007-12-17 | 2009-06-24 | 东部高科股份有限公司 | Inductor of semiconductor device and method for manufacturing the same |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2440365A (en) * | 2006-07-21 | 2008-01-30 | X Fab Uk Ltd | A semiconductor device |
| TWI349362B (en) * | 2007-12-07 | 2011-09-21 | Realtek Semiconductor Corp | Integrated inductor |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1434511A (en) * | 2002-01-25 | 2003-08-06 | 联华电子股份有限公司 | Blocking circuit for IC |
| CN1604300A (en) * | 2004-10-28 | 2005-04-06 | 复旦大学 | Optimized design method for PN junction underlay isolation on-chip inductance |
| CN101465351A (en) * | 2007-12-17 | 2009-06-24 | 东部高科股份有限公司 | Inductor of semiconductor device and method for manufacturing the same |
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