CN103378005A - Method for manufacturing fin-shaped structures of multi-gate field effect transistor - Google Patents
Method for manufacturing fin-shaped structures of multi-gate field effect transistor Download PDFInfo
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- CN103378005A CN103378005A CN2012101211621A CN201210121162A CN103378005A CN 103378005 A CN103378005 A CN 103378005A CN 2012101211621 A CN2012101211621 A CN 2012101211621A CN 201210121162 A CN201210121162 A CN 201210121162A CN 103378005 A CN103378005 A CN 103378005A
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Abstract
The invention provides a method for manufacturing fin-shaped structures of a multi-gate field effect transistor. The method comprises the steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a P-type area and an N-type area; forming a first mask layer on the N-type area, and forming a silicon-germanium layer on the semiconductor substrate; removing the first mask layer; forming second mask layers on the P-type area and the N-type area; etching the second mask layers so as to form a P-type area groove and an N-type area groove; filling the P-type area groove and the N-type area groove with silicon layers; removing the silicon layers outside the P-type area groove and the N-type area groove, and performing an etching-back process; forming third mask layers in the P-type area groove and the N-type area groove; removing the second mask layers so as to form a P-type area fin-shaped structure and an N-type area fin-shaped structure. Due to the fact that the P-type area fin-shaped structure and the N-type area fin-shaped structure are formed on the P-type area and the N-type area respectively, the P-type area fin-shaped structure and the N-type area fin-shaped structure which are different in stress can be formed, the technique is simple, and manufacturing cost is lowered.
Description
Technical field
The present invention relates to integrated circuit and make the field, relate in particular to a kind of manufacture method of multiple gate field effect transistor fin structure.
Background technology
Mos field effect transistor (MOSFET) is constantly to the trend development of minification in recent years, this is in order to gather way, improve assembly integrated level and the cost that reduces integrated circuit, transistorized size reduces constantly, the transistorized limit that has reached various performances of dwindling.Wherein the thickness of gate oxide and source/drain junction depth have all reached the limit.
Therefore, industry has been developed multiple gate field effect transistor (Multi-Gate Transistors), and the multiple gate field effect transistor technology is a kind of novel circuit configuration technology.Conventional transistor be each transistor only have grid be used for controlling electric current between two construction units by or interrupt, and then form calculate in required " 0 " and " 1 ".And the multiple-gate transistors Manifold technology is each transistor two or three grids are arranged, thereby improved the ability of transistor controls electric current, i.e. computing capability, and significantly reduced power consumption, reduced the phase mutual interference between electric current.Wherein, multiple gate field effect transistor is the device architecture among a kind of type FET that an above grid is incorporated into individual devices, this means, raceway groove is surrounded by several grids on a plurality of surfaces, thereby the leakage current in the time of can suppressing more " cut-off " state, and can strengthen drive current under " conducting " state, so just obtained the device architecture of lower power consumption and property enhancement.
J.P.Colinge is called one piece of name in the Americana of " FinFETs and other Multi-Gate Transistors " and has introduced polytype multiple gate field effect transistor, comprise double-gated transistor (Double-Gate, FinFET), tri-gate transistors (Tri-Gate), ohm-shaped gate transistor (Ω-Gate) and quadrangle gate transistor (Quad-Gate) etc.
Wherein, take double-gated transistor as example, double-gated transistor has used two grids with the control raceway groove, has greatly suppressed short-channel effect.A concrete distortion of double-gated transistor is exactly fin transistor npn npn (FinFET), described FinFET comprises vertical fin structure and across the grid in described fin structure side, both ends at the fin structure of grid both sides are respectively source electrode and drain electrode, form raceway groove in the fin structure under the grid.As nonplanar device, the size of the fin structure of FinFET has determined the length of effective channel of transistor device.FinFET compares compacter with the MOS transistor on conventional plane, can realize higher transistor density and less whole microelectric technique.In addition, tri-gate transistors is another Common Shape of multiple-gate transistor, and wherein said grid to form three control raceway grooves, further improves the overall performance of device across side and top surface at described fin structure.
The vertical direction height of fin structure and horizontal direction width and length have tremendous influence to performance, short-channel effect and the leakage current etc. of drive current.The fin structure that for example the vertical direction height is higher provides higher drive current, the fin structure that the horizontal direction width is less can suppress leakage current better, yet, because size is constantly dwindled, fin structure vertical direction height reduces gradually, the mobility of raceway groove can decrease in the device, and then the drive current of device can be affected.Therefore, how by a kind of structure and manufacture method thereof of new multiple gate field effect transistor, the mobility that improves multiple gate field effect transistor becomes the problem that industry is demanded urgently studying.
Summary of the invention
The purpose of this invention is to provide a kind of manufacture method that can form simultaneously the multiple gate field effect transistor fin structure of the different N-type fin structure of structure and P type fin structure.
The invention provides a kind of manufacture method of multiple gate field effect transistor fin structure, may further comprise the steps: Semiconductor substrate is provided, and described Semiconductor substrate comprises p type island region and N-type district; Form the first mask layer in described N-type district, cover the second mask layer at described p type island region and germanium-silicon layer; Remove described the first mask layer; Cover the second mask layer at described p type island region and germanium-silicon layer; Described the second mask layer of etching is to form p type island region groove and N-type district groove in described the second mask layer; Carry out epitaxial growth technology, in described p type island region groove and N-type district groove, to fill silicon layer; Utilize cmp to remove described p type island region groove and N-type district groove silicon layer in addition, and return etching technics; Silicon layer in described p type island region groove and N-type district groove forms the 3rd mask layer; Remove described the second mask layer, on described p type island region groove and N-type district groove, to form respectively p type island region fin structure and N-type district fin structure.
Further, the material of described the first mask layer is a kind of or its combination in silicon dioxide, boron nitride and the agraphitic carbon.
Further, the thickness of described the first mask layer is 5～100nm.
Further, the forming process of described the first mask layer comprises: form the first mask film in described Semiconductor substrate; Etching is removed the first mask film on the described p type island region, to form the first mask layer in described N-type district.
Further, form in the step of germanium-silicon layer at described p type island region, adopt epitaxial growth method to form germanium-silicon layer, the reaction temperature of described epitaxial growth method is 500 ℃～800 ℃, reactant comprises silane and germane, the range of flow of described silane is 5sccm～20sccm, and the range of flow of described germane is 1sccm～5sccm.
Further, adopt the wet etching method to remove described the first mask layer.
Further, the thickness of described germanium-silicon layer is greater than 50 dusts.
Further, the material of described the second mask layer is a kind of or its combination in silicon dioxide, boron nitride and the agraphitic carbon, adopts chemical vapour deposition technique to form.
Further, utilize dry etching or wet etching to remove described the second mask layer.
Further, the material of described the 3rd mask layer is silicon nitride, adopts chemical vapour deposition technique to form.
Further, the thickness of described the 3rd mask layer is 5～200nm.
Further, adopt chemical mechanical milling method to remove described the 3rd mask layer.
In sum, the manufacture method of multiple gate field effect transistor fin structure of the present invention is by forming the first mask layer in described N-type district, described the first mask layer is partly remained in subsequent technique in the strong structure of N-type gas, thereby can on Semiconductor substrate, form simultaneously p type island region fin structure and N-type district fin structure, its technical process is simple, and N-type district fin structure is different with the structure of p type island region fin structure, stress is different, thereby forms N-type district FET device and the p type island region FET device architecture that satisfies the different process requirement respectively.
Description of drawings
Fig. 1 is the schematic flow sheet of the manufacture method of multiple gate field effect transistor fin structure in one embodiment of the invention.
Fig. 2～Fig. 9 is the structural representation in the manufacture process of multiple gate field effect transistor fin structure in one embodiment of the invention.
Embodiment
For making content of the present invention more clear understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art also is encompassed in protection scope of the present invention.
Secondly, the present invention utilizes schematic diagram to carry out detailed statement, and when example of the present invention was described in detail in detail, for convenience of explanation, schematic diagram did not amplify according to general ratio is local, should be with this as limitation of the invention.
Fig. 1 is the schematic flow sheet of the manufacture method of multiple gate field effect transistor fin structure in one embodiment of the invention.The invention provides a kind of manufacture method of multiple gate field effect transistor fin structure, may further comprise the steps:
Step S01: Semiconductor substrate is provided, and described Semiconductor substrate comprises p type island region and N-type district;
Step S02: form the first mask layer in described N-type district, and form germanium-silicon layer at described p type island region;
Step S03: remove described the first mask layer;
Step S04: form the second mask layer at described p type island region and N-type district;
Step S05: described the second mask layer of etching, in described the second mask layer, to form p type island region groove and N-type district groove;
Step S06: carry out epitaxial growth technology, in described p type island region groove and N-type district groove, to fill silicon layer;
Step S07: utilize cmp to remove described p type island region groove and N-type district groove silicon layer in addition, and return etching technics;
Step S08: the silicon layer in described p type island region groove and N-type district groove forms the 3rd mask layer;
Step S09: remove described the second mask layer, on described p type island region groove and N-type district groove, to form respectively p type island region fin structure and N-type district fin structure.
Fig. 2～Fig. 9 is the structural representation in the manufacture process of multiple gate field effect transistor fin structure in one embodiment of the invention.Describe the manufacture method of multiple gate field effect transistor fin structure in one embodiment of the invention in detail below in conjunction with Fig. 1～Fig. 9.
As shown in Figure 2, in step S01, provide Semiconductor substrate 100, described Semiconductor substrate comprises p type island region 10 and N-type district 20; The material of wherein said Semiconductor substrate 100 can be monocrystalline silicon, polysilicon, amorphous silicon, silicon Germanium compound or silicon-on-insulator (SOI) etc., the p type island region 10 of described Semiconductor substrate 100 and N-type district 20 are respectively applied to form p type island region fin structure and N-type district fin structure, and then form respectively p type island region FET and N-type district FET device architecture.Because it is different that the stress of p type island region FET and the fin structure of N-type district FET requires, the structure of the p type island region FET fin structure that therefore forms and the fin structure of N-type district FET is different.
As shown in Figure 3, in step S02,20 form the first mask layer 102 in described N-type district, form germanium-silicon layer 104 at described p type island region 20; The material of described the first mask layer 104 is a kind of or its combination in silicon dioxide, boron nitride and the agraphitic carbon.The forming process of described the first mask layer 102 comprises: at first, form the first mask film (not indicating among the figure) in described Semiconductor substrate 100; Then, etching is removed the first mask film on the described p type island region 10, thereby 20 forms the first mask layer 102 in described N-type district, and described the first mask layer 102 better thickness are 5～100nm.The forming process of described germanium-silicon layer 104 comprises: form germanium-silicon film in described Semiconductor substrate 100 first, recycling photoetching and etching technics are removed the described germanium-silicon film of part, to form germanium-silicon layer 104.In preferred embodiment, adopt epitaxial growth method to form germanium-silicon layer 104, reaction temperature is 500 ℃～800 ℃, reactant comprises silane and germane, the range of flow of described silane is 5sccm～20sccm, the range of flow of described germane is 1sccm～5sccm, owing to be coated with the first mask layer 102 in N-type district 20, so utilize epitaxially grown selectivity characrerisitic, only form germanium-silicon layer 104 at p type island region 10, less than 200 dusts, epitaxial growth method can reduce the etching injury to germanium-silicon layer 104 to the thickness of described germanium-silicon layer 104 greater than 50 dusts, improves the interface evenness of germanium-silicon layer 104.
Such as Fig. 3～shown in Figure 4, in step S03, adopt dry etching method to remove described the first mask layer 102.
As shown in Figure 4, in step S04, form the second mask layer 106 at described p type island region 10 and N-type district 20; The material of described the second mask layer 106 can be a kind of or its combination in silicon dioxide, boron nitride and the agraphitic carbon.The thickness range of described the second mask layer 106 is 20nm～500nm, and the thickness of described the second mask layer 106 can specifically be determined according to the p type island region fin structure of follow-up formation and the thickness of N-type district fin structure, will not limit at this.
As shown in Figure 5, in step S05, described the second mask layer 106 of etching is to form p type island region groove 108a and N-type district groove 108b in described the second mask layer 106; Specifically can form by following steps: at first apply photoresist at described the second mask layer 106, and utilize exposure and developing process to form the photoresist of patterning, then utilize the photoresist of patterning to be mask, described the second mask layer 106 of etching, adopt wet etching to remove described the second mask layer 106, stop on the germanium-silicon layer 104 at p type island region 10, stop on the described Semiconductor substrate 100 in N-type district 20, thereby in described the second mask layer 106, form p type island region groove 108a and N-type district groove 108b.
As shown in Figure 6, in step S06, carry out epitaxial growth technology, in described p type island region groove 108a and N-type district groove 108b, to fill silicon layer; Utilize the characteristic of the selective growth of epitaxial growth technology, thus growth silicon layer 110 in the p type island region groove 108a of exposing semiconductor substrate and N-type district groove 108b only, until fill full described p type island region groove 108a and N-type district groove 108b.
Shown in Fig. 6 and 7, in step S07, utilize cmp to remove described p type island region groove 108a and N-type district groove 108b silicon layer 110 in addition, and return etching technics; Return in the etching process, the segment thickness of the silicon layer 110 among p type island region groove 108a and the N-type district groove 108b is etched, and makes the height of silicon layer 110 be lower than the height of described the second mask layer 106.This silicon layer 110 is the thickness of follow-up formation the 3rd mask layer 112 with the difference in height of described the second mask layer 106.
As shown in Figure 8, in step S08, the silicon layer 110 in described p type island region groove 108a and N-type district groove 108b forms the 3rd mask layer 112; The material of described the 3rd mask layer 112 can be silicon nitride, the forming process of described the 3rd mask layer 112 is as follows: at first form one deck silicon nitride film with chemical vapour deposition technique, then remove unnecessary silicon nitride film by the method for cmp, thereby form the 3rd mask layer 112.
In conjunction with Fig. 6, Fig. 8 and Fig. 9; in step S09; remove described the second mask layer 106; on described p type island region groove 108a and N-type district groove 108b, to form respectively p type island region fin structure 201 and N-type district fin structure 202; because the 3rd mask layer 112 is the silicon nitride material; has larger etching selection ratio than the second mask layer 106; thereby when etching is removed the second mask layer 106; can protect the silicon layer 110 of the 3rd mask layer 112 belows; finally form the p type island region fin structure at described p type island region 20,10 form N-type district fin structure in described N-type district.
After the processing step that forms fin structure, form the upper surface at the middle part that is located at described N-type district fin structure 202 and the N-type district grid on the sidewall in described Semiconductor substrate 100, and be located at the upper surface at middle part of described p type island region fin structure 201 and the p type island region grid on the sidewall etc.
In sum, the manufacture method of multiple gate field effect transistor fin structure of the present invention is by forming the first mask layer in described N-type district, described the first mask layer is partly remained in subsequent technique in the strong structure of N-type gas, thereby can on Semiconductor substrate, form simultaneously p type island region fin structure and N-type district fin structure, its technical process is simple, and N-type district fin structure is different with the structure of p type island region fin structure, stress is different, thereby forms N-type district FET device and the p type island region FET device architecture that satisfies the different process requirement respectively.
Although the present invention discloses as above with preferred embodiment; so it is not to limit the present invention; have in the technical field under any and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (13)
1. the manufacture method of a multiple gate field effect transistor fin structure comprises:
Semiconductor substrate is provided, and described Semiconductor substrate comprises p type island region and N-type district;
Form the first mask layer in described N-type district, and form germanium-silicon layer at described p type island region;
Remove described the first mask layer;
Cover the second mask layer at described p type island region and N-type district;
Described the second mask layer of etching is to form p type island region groove and N-type district groove in described the second mask layer;
Carry out epitaxial growth technology, in described p type island region groove and N-type district groove, to fill silicon layer;
Utilize cmp to remove described p type island region groove and N-type district groove silicon layer in addition, and return etching technics;
Silicon layer in described p type island region groove and N-type district groove forms the 3rd mask layer;
Remove described the second mask layer, on described p type island region groove and N-type district groove, to form respectively p type island region fin structure and N-type district fin structure.
2. the manufacture method of multiple gate field effect transistor fin structure as claimed in claim 1 is characterized in that, the material of described the first mask layer is a kind of or its combination in silicon dioxide, boron nitride and the agraphitic carbon.
3. the manufacture method of multiple gate field effect transistor fin structure as claimed in claim 1 is characterized in that, the thickness of described the first mask layer is 5nm～100nm.
4. the manufacture method of multiple gate field effect transistor fin structure as claimed in claim 1 is characterized in that, the forming process of described the first mask layer comprises:
Form the first mask film in described Semiconductor substrate;
Etching is removed the first mask film on the described p type island region, to form the first mask layer in described N-type district.
5. the manufacture method of multiple gate field effect transistor fin structure as claimed in claim 1, it is characterized in that, adopt epitaxial growth method to form germanium-silicon layer, the reaction temperature of described epitaxial growth method is 500 ℃～800 ℃, reactant comprises silane and germane, the range of flow of described silane is 5sccm～20sccm, and the range of flow of described germane is 1sccm～5sccm.
6. the manufacture method of multiple gate field effect transistor fin structure as claimed in claim 1 is characterized in that, adopts the wet etching method to remove described the first mask layer.
7. the manufacture method of multiple gate field effect transistor fin structure as claimed in claim 1 is characterized in that, the thickness of described germanium-silicon layer is greater than 50 dusts.
8. the manufacture method of multiple gate field effect transistor fin structure as claimed in claim 1 is characterized in that, the material of described the second mask layer is a kind of or its combination in silicon dioxide, boron nitride and the agraphitic carbon, adopts chemical vapour deposition technique to form.
9. the manufacture method of multiple gate field effect transistor fin structure as claimed in claim 1 is characterized in that, the thickness range of described the second mask layer is 20nm～500nm.
10. the manufacture method of multiple gate field effect transistor fin structure as claimed in claim 1 is characterized in that, utilizes dry etching or wet etching to remove described the second mask layer.
11. the manufacture method of multiple gate field effect transistor fin structure as claimed in claim 1 is characterized in that, the material of described the 3rd mask layer is silicon nitride, adopts chemical vapour deposition technique to form.
12. the manufacture method of multiple gate field effect transistor fin structure as claimed in claim 1 is characterized in that, the thickness of described the 3rd mask layer is 5nm～200nm.
13. the manufacture method of multiple gate field effect transistor fin structure as claimed in claim 1 is characterized in that, adopts chemical mechanical milling method to remove described the 3rd mask layer.
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Cited By (4)
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| CN104966672A (en) * | 2015-06-30 | 2015-10-07 | 上海华力微电子有限公司 | Fin-type field-effect transistor substrate preparation method |
| CN107275211A (en) * | 2016-04-06 | 2017-10-20 | 中芯国际集成电路制造(上海)有限公司 | The forming method of fin field effect pipe |
| CN107316814A (en) * | 2016-04-26 | 2017-11-03 | 联华电子股份有限公司 | The manufacture method of semiconductor element |
| CN108573851A (en) * | 2017-03-08 | 2018-09-25 | 上海新昇半导体科技有限公司 | The preparation method of autoregistration seed layer and autoregistration film |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104966672A (en) * | 2015-06-30 | 2015-10-07 | 上海华力微电子有限公司 | Fin-type field-effect transistor substrate preparation method |
| CN104966672B (en) * | 2015-06-30 | 2019-01-25 | 上海华力微电子有限公司 | Fin field effect pipe matrix preparation method |
| CN107275211A (en) * | 2016-04-06 | 2017-10-20 | 中芯国际集成电路制造(上海)有限公司 | The forming method of fin field effect pipe |
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| CN108573851A (en) * | 2017-03-08 | 2018-09-25 | 上海新昇半导体科技有限公司 | The preparation method of autoregistration seed layer and autoregistration film |
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