CN103377894A - Metal silicide manufacturing method - Google Patents

Metal silicide manufacturing method Download PDF

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Publication number
CN103377894A
CN103377894A CN2012101189721A CN201210118972A CN103377894A CN 103377894 A CN103377894 A CN 103377894A CN 2012101189721 A CN2012101189721 A CN 2012101189721A CN 201210118972 A CN201210118972 A CN 201210118972A CN 103377894 A CN103377894 A CN 103377894A
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metal silicide
nickel based
thickness
nickel
annealing
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CN103377894B (en
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罗军
邓坚
赵超
钟汇才
李俊峰
陈大鹏
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Ruili Flat Core Microelectronics Guangzhou Co Ltd
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Institute of Microelectronics of CAS
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Abstract

The invention discloses a metal silicide manufacturing method. The metal silicide manufacturing method comprises the steps that a characteristic line is formed on a silicon substrate, and a nickel-base metal layer is formed on the silicon substrate and the characteristic line, wherein the thickness of the nickel-base metal layer is larger than the minimum thickness which is determined by the depth of a source-and-drain junction and is required by forming of nickel-base metal silicide; primary annealing is carried out so as to ensure that the nickel-base metal layer reacts with the silicon substrate to form first nickel-base metal silicide with the even thickness; metal which does not participate in the reaction is removed, and secondary annealing is carried out so as to ensure that the first nickel-base metal silicide is converted to second nickel-base metal silicide with the even thickness. According to the semiconductor device manufacturing method, the thicknesses of thin metal layers are increased, a metal silicide self-alignment technology is utilized, technological parameters are controlled, the metal silicide with the even thickness is formed through two-step annealing, source-drain resistance is evenly reduced, and device performance is further improved.

Description

The metal silicide manufacture method
Technical field
The present invention relates to a kind of metal silicide manufacture method, particularly relate to a kind of method of uniformity of film of energy Effective Raise metal silicide film.
Background technology
The IC integrated level constantly increases needs device size to continue to dwindle by this example, however electrical work voltage sometimes remain unchanged so that actual MOS device internal electric field intensity constantly increases.High electric field brings a series of integrity problems, so that device performance degeneration.For example, the parasitic series resistance meeting between the MOSFET source-drain area is so that the decline of equivalent operating voltage.Especially, for example the physical gate of MOSFET is long during near inferior 30nm when semiconductor device, and living resistance has become whole device equivalent resistance above channel resistance important component part is omitted in the source.For this reason, need to be on source-drain area and/or middle employing metal silicide effectively reduce source-drain contact resistance and parasitic series resistance, improve the device performance of MOSFET with this.
Figure 1A to 1C is depicted as the cutaway view of the silicide self-registered technology step of prior art.Shown in Figure 1A, on the substrate 1 that contains Si, form successively a plurality of gate stack structures that consisted of by gate insulator 2, grid conducting layer 3, form grid curb wall 4 in each gate stack structure both sides, then form thin metal layer 5 in total, its material is the Ni Base Metal, for example is Ni, NiPt, NiCo, NiPtCo etc.It should be noted that, owing to form the normally sputter of technique of thin metal layer 5, be subject to process conditions and sputter principle, on the narrower zone between adjacent gate stack structure (among the figure shown in the dotted line frame), the thickness of thin metal layer 5 is less than the thickness on the wide region outside this zone, also namely has the thickness difference of thin metal layer 5 between the narrow lines of device and wide lines.Below inferior 32nmCMOS process node, this difference in thickness is obvious all the more, even sometimes may cause disappearance, the fracture of thin metal layer 5 on the narrow lines.As shown in Figure 1B, for example carrying out the first short annealing under 250～300 ℃ the lower temperature, so that the nickel based metal silicide 6 of the contained rich Ni phase of Si reaction formation, for example Ni in thin metal layer 5 and the substrate 1 2Si, Ni 2PtSi, Ni 2CoSi, Ni 2PtCoSi.Because the thickness difference of aforesaid thin metal layer 5, so that the thickness of the nickel based metal silicide 6 of the rich Ni phase on the narrow lines reduces, even may lack fully, rupture, namely on this zone, do not form the nickel based metal silicide 6 of rich Ni phase yet.Shown in Fig. 1 C, divest after the unreacted thin metal layer 5, for example carrying out the second short annealing under 450～500 ℃ the higher temperature, so that being converted into, the nickel based metal silicide 6 of rich Ni phase has more low-resistance nickel based metal silicide 7, for example NiSi, NiPtSi, NiCoSi, NiPtCoSi.Because above-mentioned thickness difference, so that the final thickness of nickel based metal silicide 7 on narrow lines and wide lines that forms is also inhomogeneous, namely thickness is obviously less on the part between the intensive gate stack lines, and thickness is obviously larger on other wider portion.Lines are more intensive narrower, and the metal silicide film thickness on this zone is just thinner, and resistance is larger.Yet on the zones of different of different nude film tube cores or wafer, narrow lines are accompanied by wide lines usually, so the metal silicide film thickness distribution is inhomogeneous.The inhomogeneities of this thickness will cause the inconsistent of device contacts, dead resistance, cause the device electric property that the change of not expecting occurs.
This shows that existing metal silicide technology has reduced electric property and the reliability of device so that uneven film thickness is even.
Summary of the invention
From the above mentioned, the object of the present invention is to provide a kind of method, semi-conductor device manufacturing method of energy Effective Raise metal silicide film thickness evenness.
For this reason, the invention provides a kind of metal silicide manufacture method, comprise step: form characteristic line at silicon-containing substrate; Form the nickel based metal layer at silicon-containing substrate and characteristic line, wherein the thickness of nickel based metal layer forms the required minimum thickness of nickel based metal silicide greater than what deeply determined by source-and-drain junction; Carry out the first annealing, so that nickel based metal layer and silicon-containing substrate reaction form the first nickel based metal silicide of uniform thickness; After removing unreacted metal, carry out the second annealing, so that the first nickel based metal silicide is converted into the second nickel based metal silicide of uniform thickness.
Wherein, the thickness of nickel based metal layer is 7～200nm.
Wherein, the nickel based metal layer comprises Ni, Ni-Pt, Ni-Co, Ni-Pt-Co.Wherein, the content of non-Ni metal is 1%～50%.
Wherein, the temperature of the second annealing is higher than the temperature of the first annealing.Wherein, the first annealing temperature is 150～300 ℃, and the second annealing temperature is 450～550 ℃.
Wherein, the Ni content in the first nickel based metal silicide is greater than the Ni content in the second nickel based metal silicide.Wherein, the first nickel based metal silicide comprises Ni 2Si, Ni 2PtSi, Ni 2CoSi, Ni 2PtCoSi, the second nickel based metal silicide comprises NiSi, NiPtSi, NiCoSi, NiPtCoSi.
According to metal silicide manufacture method of the present invention, by improving the thickness of thin metal layer, utilize the metal silicide self-registered technology and control technological parameter, in two steps annealing has formed the metal silicide with uniform thickness, thereby reduced equably the source ohmic leakage, further improved performance of devices.
Description of drawings
Describe technical scheme of the present invention in detail referring to accompanying drawing, wherein:
Figure 1A to 1C is the generalized section of the metal silicide manufacture method of prior art; And
But Fig. 2 to Fig. 4 is the generalized section according to each step of the metal silicide manufacture method of Effective Raise uniformity of film of the present invention.
Embodiment
Describe feature and the technique effect thereof of technical solution of the present invention in detail referring to accompanying drawing and in conjunction with schematic embodiment, but disclose the metal silicide manufacture method of Effective Raise uniformity of film.It is pointed out that structure like the similar Reference numeral representation class, used term " first " among the application, " second ", " on ", D score etc. can be used for modifying various device architectures or manufacturing process.These are modified is not space, order or the hierarchical relationship of hint institute's modification device architecture or manufacturing process unless stated otherwise.
But Fig. 2 to Fig. 4 is the generalized section according to each step of the metal silicide manufacture method of Effective Raise uniformity of film of the present invention.
With reference to accompanying drawing 2, the basis of formation structure.Be illustrated in figure 2 as the generalized section of foundation structure.
Substrate 1 at first is provided, and substrate 1 comprises the Si element at least, for example Si (SOI), SiGe, SiC etc. on body Si, the insulator, and preferably substrate 1 is body Si or SOI.
Secondly, form a plurality of characteristic lines at substrate 1.For MOSFET makes, also namely adopt the conventional method depositions such as LPCVD, PECVD, HDPCVD, MOCVD, MBE to deposit successively gate insulator 2, grid conducting layer 3 at substrate 1, and etching form a plurality of gate stack structures.For front grid technique, after forming, no longer removes gate stack structure, as final gate stack, therefore gate insulator 2 is silica, silicon oxynitride or high k material, high k material includes but not limited to that nitride (for example SiN, AIN, TiN), metal oxide (are mainly subgroup and lanthanide element oxide, for example Al 2O 3, Ta 2O 5, TiO 2, ZnO, ZrO 2, HfO 2, CeO 2, Y 2O 3), Perovskite Phase oxide (PbZr for example xTi 1-xO 3(PZT), Ba xSr 1-xTiO 3(BST)); Correspondingly, grid conducting layer 3 is doped polycrystalline silicon, metal, metal alloy, metal nitride, and wherein said metal comprises W, Cu, Mo, Ti, Al, Ta etc. and combination thereof.For rear grid technique, gate stack is that dummy grid is stacking, will remove in technique after a while and forms gate trench, refills the formation grid for the later stage, therefore gate insulator 2 is silica, silicon oxynitride, and grid conducting layer 3 is polysilicon, microcrystal silicon, amorphous silicon.Form grid curb wall 4 in gate stack structure 2,3 deposition dielectrics and etching, its material for example for silicon nitride, silicon oxynitride, diamond like carbon amorphous carbon (DLC), metal oxide (be preferably have heavily stressed, for example greater than 1GPa, to improve driving force to the raceway groove stress application).For other device architectures, characteristic line can be the Si line of fin structure, intensive sram cell figure etc.
Then, on whole device, also namely pass through for example method depositing metal layers 5 of sputter at substrate 1 and by the characteristic line that grid curb wall 4 and grid conducting layer 3 consist of, as the predecessor that forms metal silicide.The thickness H 1 of metal level 5 is enough thick, surpasses in the accompanying drawing 1 available technology adopting metal silicide self-registered technology and forms the required thickness H0 of metal silicide (among Fig. 2 shown in the dotted line horizontal line).H0 depends on source-and-drain junction dark (also namely dark for source-and-drain junction after forming metal silicide given future, the minimum thickness of required metal level 5) usually, for example is 1～5nm; And H1 for example is 7～200nm for example more than or equal to 1.4 times of H0.The material of metal level 5 is nickel based metal, the metal or metal alloy that also namely comprises at least Ni, for example be Ni, Ni-Pt, Ni-Co, Ni-Pt-Co, wherein the total content of non-Ni metallic element (Pt and/or Co) (atomicity this) is preferably 1%～50%, also is corresponding Ni content for higher by 50%～99%.
With reference to Fig. 3, carry out the first annealing, so that the reaction of the Si in the metal of metal level 5 and the substrate 1 forms the first metal silicide 6, the rich Metal Phase silicide 6 that also namely has high electrical resistance.For example adopt rta technique, annealing temperature is the first lower annealing temperature, is 150～300 ℃, and annealing time is 5 seconds to 5 minutes.The rich Metal Phase silicide 6 that forms is rich nickel phase silicide, for example is Ni 2Si, Ni 2PtSi, Ni 2CoSi, Ni 2PtCoSi.Under this first lower annealing temperature, Ni atom diffusion limited and the self-saturation of being rich in the metal level 5, therefore rich nickel phase silicide 6 growths can be too not thick, just stop to continue reaction after ruing out of thickness and be the Ni Base Metal layer 5 of above-mentioned H0, therefore the part H2 ' of thickness H2 on substrate surface of rich nickel phase silicide 6 equals or approaches above-mentioned by the dark definite required metal layer thickness H0 of metal silicide technology of source-and-drain junction, for example be 1.0～1.1 times of H0 (although be shown as among Fig. 3 equal, in fact can fluctuate).It is self-saturating that the thickness of rich nickel phase silicide 6 is subject to annealing temperature, time and silicatization process, and no longer be subject to the thickness thickness H1 of metal level 5 (because greater than required thickness H0) of metal level 5, therefore rich nickel phase silicide 6 has equal, uniform thickness H2, the uniformity of film in the time of can guaranteeing thus follow-up formation low resistance metal silicide at whole wafer.
With reference to Fig. 4, remove unreacted metal after, carry out the second annealing so that the first metal silicide 6 is converted into the second metal silicide 7, also namely have more low-resistance metal silicide 7.Divesting unreacted metal level 5 among Fig. 3, also is the part (its thickness is H1-H0) that thickness surpasses H0.Adopt rta technique, annealing temperature is 450～550 ℃ for the second higher annealing temperature (also namely the second annealing temperature is higher than the first annealing temperature), and annealing time is 5 seconds to 3 minutes.Metal silicide 7 is the nickel based metal silicide, and Ni content is lower than the Ni content in the first metal silicide 6 in the second metal silicide 7.Particularly, metal silicide 7 for example is NiSi, NiPtSi, NiCoSi, NiPtCoSi.Because the first metal silicide 6 forming processes are self-saturating and have formed the film of even thickness among Fig. 3, so the also corresponding uniformity that kept of thickness of the second metal silicide 7 among Fig. 4, identical thickness H3 also namely had.Different according to annealing temperature and time, H3 can more than or equal to H2, for example be 1.1～1.2 times of H2.
As seen from Figure 4, the final low-resistance Ni Base Metal silicide 7 that forms has unified film thickness, therefore also has identical film resistor, has improved uniformity and the reliability of device.
According to method, semi-conductor device manufacturing method of the present invention, by improving the thickness of thin metal layer, utilize the metal silicide self-registered technology and control technological parameter, in two steps annealing has formed the metal silicide with uniform thickness, thereby reduced equably the source ohmic leakage, further improved performance of devices.
Although with reference to one or more exemplary embodiments explanation the present invention, those skilled in the art can know and need not to break away from the scope of the invention and device architecture is made various suitable changes and equivalents.In addition, can be made by disclosed instruction and manyly may be suitable for the modification of particular condition or material and do not break away from the scope of the invention.Therefore, purpose of the present invention does not lie in to be limited to as being used for and realizes preferred forms of the present invention and disclosed specific embodiment, and disclosed device architecture and manufacture method thereof will comprise all embodiment that fall in the scope of the invention.

Claims (10)

1. metal silicide manufacture method comprises step:
Form characteristic line at silicon-containing substrate;
Form the nickel based metal layer at silicon-containing substrate and characteristic line, wherein the thickness of nickel based metal layer forms the required minimum thickness of nickel based metal silicide greater than what deeply determined by source-and-drain junction;
Carry out the first annealing, so that nickel based metal layer and silicon-containing substrate reaction form the first nickel based metal silicide of uniform thickness;
After removing unreacted metal, carry out the second annealing, so that the first nickel based metal silicide is converted into the second nickel based metal silicide of uniform thickness.
2. metal silicide manufacture method as claimed in claim 1, wherein, the thickness of nickel based metal layer is 7～200nm.
3. metal silicide manufacture method as claimed in claim 1, wherein, the nickel based metal layer comprises Ni, Ni-Pt, Ni-Co, Ni-Pt-Co.
4. metal silicide manufacture method as claimed in claim 3, wherein, the content of non-Ni metal is 1%～50%.
5. metal silicide manufacture method as claimed in claim 1, wherein, the temperature of the second annealing is higher than the temperature of the first annealing.
6. metal silicide manufacture method as claimed in claim 5, wherein, the first annealing temperature is 150～300 ℃.
7. metal silicide manufacture method as claimed in claim 5, wherein, the second annealing temperature is 450～550 ℃.
8. metal silicide manufacture method as claimed in claim 1, wherein, the Ni content in the first nickel based metal silicide is greater than the Ni content in the second nickel based metal silicide.
9. metal silicide manufacture method as claimed in claim 7, wherein, the first nickel based metal silicide comprises Ni 2Si, Ni 2PtSi, Ni 2CoSi, Ni 2PtCoSi.
10. metal silicide manufacture method as claimed in claim 7, wherein, the second nickel based metal silicide comprises NiSi, NiPtSi, NiCoSi, NiPtCoSi.
CN201210118972.1A 2012-04-20 2012-04-20 Metal silicide manufacture method Active CN103377894B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111785622A (en) * 2020-07-15 2020-10-16 上海华力集成电路制造有限公司 Annealing process and device for forming metal silicide and metal contact layer forming method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080136030A1 (en) * 2006-10-23 2008-06-12 Interuniversitair Microelektronicacentrum (Imec) Semiconductor device comprising a doped metal comprising main electrode
CN101211781A (en) * 2006-12-28 2008-07-02 中芯国际集成电路制造(上海)有限公司 Self-aligning metal silicide preparation method
CN101512740A (en) * 2005-10-03 2009-08-19 国际商业机器公司 Method and apparatus for forming nickel silicide with low defect density in FET devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101512740A (en) * 2005-10-03 2009-08-19 国际商业机器公司 Method and apparatus for forming nickel silicide with low defect density in FET devices
US20080136030A1 (en) * 2006-10-23 2008-06-12 Interuniversitair Microelektronicacentrum (Imec) Semiconductor device comprising a doped metal comprising main electrode
CN101211781A (en) * 2006-12-28 2008-07-02 中芯国际集成电路制造(上海)有限公司 Self-aligning metal silicide preparation method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111785622A (en) * 2020-07-15 2020-10-16 上海华力集成电路制造有限公司 Annealing process and device for forming metal silicide and metal contact layer forming method

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