CN103370777B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
CN103370777B
CN103370777B CN201280008771.4A CN201280008771A CN103370777B CN 103370777 B CN103370777 B CN 103370777B CN 201280008771 A CN201280008771 A CN 201280008771A CN 103370777 B CN103370777 B CN 103370777B
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drain electrode
gate electrode
semiconductor device
semiconductor layer
region
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CN103370777A (en
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栗田大佑
吐田真一
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Rohm Co Ltd
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Sharp Corp
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    • H—ELECTRICITY
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L2924/1305—Bipolar Junction Transistor [BJT]
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
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    • H01L2924/1306—Field-effect transistor [FET]
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

By on substrate successively the active region of the GaN layer (1) of lamination, AlGaN layer (2) and the gate electrode formed on substrate, source electrode, drain electrode and AlGaN layer (2) form HFET.Have in the AlGaN layer (2) beyond the active region of this HFET across dielectric film (30 formed can the drain electrode pad (31) of welding region (31a) be connected with drain electrode.Upper and the gate electrode extension (14) be connected with gate electrode can be formed between welding region (31a) at source electrode and drain electrode pad (31) in AlGaN layer (2).Thus provide a kind of can improve when not increasing component size without the drain electrode pad that the dielectric film of interlayer dielectric is formed can withstand voltage semiconductor device between welding region and source electrode.

Description

Semiconductor device
Technical field
The present invention relates to a kind of semiconductor device, the semiconductor device of the particularly a kind of power device withstand voltage as height use.
Background technology
In recent years, people constantly seek to cut down the environmental cure such as carbon dioxide, wherein require that the inverter that uses in power supply etc. and converter realize high efficiency.In high efficiency, carrying out the improvement playing the transistor of function as the power device of key, and researching and developing new device.For these power devices, even the power supply of civilian machine is also estimated to require the withstand voltage of 300 ~ 400V, if vehicle-mounted, then estimate to require the withstand voltage of about 1200V.Have in such power device with GaN be representative horizontal type element and with IGBT(insulated gate bipolar transistor) and SiC be the longitudinal type element of representative.So-called horizontal type element, refers to the element with the structure on a semiconductor substrate source electrode, drain electrode and gate electrode being arranged on the same face side.
Such as, at present, as the horizontal type semiconductor device using GaN, have electronics being formed at the 2DEG(two dimensional electron gas of heterojunction of aluminum gallium nitride (AlGaN) and gallium nitride layer (GaN)) in the HFET(Hetero-junctionFieldEffectTransistor of movement, HFET, such as, with reference to Japanese Unexamined Patent Publication 2008-177527 publication (patent documentation 1)).
In the power device using horizontal type semiconductor element, on drain electrode, be applied with the voltage difference of hundreds of volt relative to source electrode.Therefore, drain electrode pad is also applied with the voltage of hundreds of volt, so guarantee that the insulating properties around drain electrode pad becomes important.
The structure of pad on a kind of sheet (パ ッ De オ Application チ ッ プ) is proposed in patent documentation 1, on sheet in pad structure, what need to consider between pad and active region is withstand voltage, need in addition to do various research, such as, need when the enterprising line lead of pad engages the impact produced active layer to be limited in minimum etc.On the other hand, when pad being arranged at active region and being outer, there is by using prior art the advantage of the technology that can utilize wire-bonded that reliability is high.
Pad in the horizontal type semiconductor device of existing GAN system and the structure of source electrode are as shown in figure 13.In fig. 13,601 is layer of undoped gan, and 602 is undoped algan layer, and 640 is interlayer dielectric.Gate electrode 613 is being arranged at the outside of the active region between source electrode 611 and drain electrode 612, the semiconductor layer surface of the 2DEG of removing heterogeneous interface is arranging surface protection film 630, and be formed with bonding electrodes on surface protection film 630.At this, what why remove drain electrode pad 631 can 2DEG under welding region 631a, and be because when being turned off by gate electrode 613, also only insulate across surface protection film 630 and source electrode 611 or drain electrode 612, the possibility of therefore leaking electricity is larger.In addition, the known voltage owing to especially applying hundreds of volt in bonding electrodes on drain electrode pad 631, therefore to cause between drain electrode pad 631 and source electrode 611 or between drain electrode pad 631 and the part of 2DEG resistance to presses to problem.
That is, in above-mentioned semiconductor device, even if the distance between drain electrode pad 631 and source electrode 611 or between drain electrode pad 631 and the end of 2DEG is set to computationally can be withstand voltage distance, also there is the problem of withstand voltage between drain electrode pad 631 and source electrode 611 or the withstand voltage reduction between drain electrode pad 631 and active region.The present inventor studies intensively for this problem, its result is inferred as owing to having larger leakage current via semiconductor surface conducting between drain electrode pad and source electrode or between drain electrode pad and the exposed division of 2DEG, therefore withstand voltagely drops to below calculated value.
In order to solve this problem, although can be improved by the distance fully expanded between the drain electrode pad of semiconductor device and the 2DEG of active region withstand voltage, exist and constantly must not cause the problem that component size becomes large greatly to the region that semiconductor element characteristic is made contributions.If from the viewpoint of the cost of semiconductor element, be then necessary to reduce as much as possible not to the inactive area that element characteristic is made contributions.
Prior art document
Patent documentation
Patent documentation 1:(Japan) JP 2008-177527 publication (Fig. 8)
Summary of the invention
The technical problem that invention will solve
So, problem of the present invention be to provide a kind of can improve when component size does not increase without the drain electrode pad that the dielectric film of interlayer dielectric is formed can withstand voltage semiconductor device between welding region and source electrode.
For the technical scheme of technical solution problem
In order to solve the problem, the feature of semiconductor device of the present invention is, comprising:
Substrate;
Semiconductor layer, to be formed on aforesaid substrate and to include source region;
Switch element, has the gate electrode, source electrode and the drain electrode that are formed on the above-mentioned active region of above-mentioned semiconductor layer;
Drain electrode pad, is connected with above-mentioned drain electrode, have on the region beyond the above-mentioned active region of above-mentioned semiconductor layer across dielectric film formed can welding region;
Gate electrode extension, to be formed on above-mentioned semiconductor layer and to be at least formed between welding region, can being connected with above-mentioned gate electrode of above-mentioned source electrode and above-mentioned drain electrode pad.
At this, active region refers to semiconductor layer regions charge carrier being flowed between source electrode and drain electrode due to the gate electrode between the source electrode be configured on semiconductor layer and drain electrode applying voltage.
Utilize said structure, on the semiconductor layer and switch element source electrode and drain electrode pad can form the gate electrode extension be connected with the gate electrode of switch element between welding region, thus by controlling to be applied to the voltage of gate electrode and the voltage of control gate electrode extension, the source electrode of switch element and drain electrode pad can gate electrode extension between welding region downside semiconductor layer in form depletion layer, thus can effectively suppress leakage current and improve resistance to piezoelectric voltage.Therefore, it is possible to when not increasing component size, improve without the drain electrode pad that the dielectric film of interlayer dielectric is formed can withstand voltage between welding region and source electrode.That is, height withstand voltageization between the source drain that can realize switch element.
It should be noted that, the switch element of semiconductor device of the present invention is MOSFET(MetalOxideSemiconductorFieldEffectTransistor, metal-oxide layer-semiconductcor field effect transistor), HFET(Hetero-junctionFieldEffectTransistor, HFET) or JFET(JunctionFieldEffectTransistor, junction field effect transistor) etc.
In addition, in the semiconductor device of an execution mode,
Above-mentioned semiconductor layer is included in the first semiconductor layer of lamination successively on aforesaid substrate and forms the second semiconductor layer of heterogeneous interface with this first semiconductor layer;
Above-mentioned switch element is the HFET utilizing the two dimensional electron gas formed at the heterogeneous interface of above-mentioned first semiconductor layer and above-mentioned second semiconductor layer.
Utilize above-mentioned execution mode, depletion layer can be formed in semiconductor layer on the downside of gate electrode extension between welding region at the source electrode of switch element and drain electrode pad by controlling to be applied to the voltage of gate electrode and the voltage of control gate electrode extension, make the two dimensional electron gas of the heterogeneous interface at the first semiconductor layer and the second semiconductor layer disappear thus, thus can effectively suppress leakage current and improve withstand voltage.
In addition, in the semiconductor device of an execution mode,
The heterogeneous interface of above-mentioned first semiconductor layer and above-mentioned second semiconductor layer that form above-mentioned two dimensional electron gas be formed at least except above-mentioned drain electrode pad can region on the aforesaid substrate except welding region underside area.
Utilize above-mentioned execution mode, the heterogeneous interface of the first semiconductor layer and the second semiconductor layer can the underside area of welding region do not formed at least at drain electrode pad, thus two dimensional electron gas can not be present in drain electrode pad can the downside of welding region, can more effectively suppress at the source electrode of switch element and drain electrode pad can leakage current between welding region.
In addition, in the semiconductor device of an execution mode,
Run through a upside part for above-mentioned second semiconductor layer or run through above-mentioned second semiconductor layer and be formed with recess in a part for the upside of above-mentioned first semiconductor layer,
Above-mentioned gate electrode is imbedded at least partially at above-mentioned recess.
Utilize above-mentioned execution mode, by making the recess imbedding the upside part being formed at the second semiconductor layer at least partially of gate electrode, utilize the Schottky junction of the second semiconductor layer and gate electrode, make to there is not two dimensional electron gas under gate electrode, thus threshold voltage raises, and makes the normally closed action of switch element become possibility.
Or, imbedding at least partially of gate electrode is made to run through the second semiconductor layer and the recess formed in the upside of a first semiconductor layer part, heterogeneous interface between first semiconductor layer and the second semiconductor layer is cut off by gate electrode, thus threshold voltage raises, and makes the normally closed action of switch element become possibility.
In addition, in the semiconductor device of an execution mode,
Comprise connecting electrode, this connecting electrode be formed in above-mentioned drain electrode pad can welding region downside and be at least formed in the region relative with above-mentioned gate electrode extension, what this connecting electrode ran through that above-mentioned dielectric film connects above-mentioned drain electrode pad can welding region and above-mentioned semiconductor layer.
Utilize above-mentioned execution mode, utilize drain electrode pad can welding region downside and at least at the connecting electrode that the relative region of gate electrode extension is formed, run through dielectric film and connect drain electrode pad can welding region and semiconductor layer, thus drain electrode pad can welding region downside dielectric film on no longer apply electric field and the insulation breakdown of dielectric film can be prevented.
In addition, in the semiconductor device of an execution mode,
Be included in above-mentioned gate electrode extension and and the above-mentioned source electrode that adjoins of this gate electrode extension between the territory, element separation area that formed, above-mentioned semiconductor layer regions.
Utilize above-mentioned execution mode, because likely formed dummy transistor by the source electrode of switch element, gate electrode extension and connecting electrode and worked, so by gate electrode extension and and the source electrode that adjoins of this gate electrode extension between semiconductor layer regions forming element separated region, utilize territory, element separation area by formed the source electrode of dummy transistor and gate electrode extension from.Thereby, it is possible to reliably prevent from forming delaying work of dummy transistor by the source electrode of switch element, gate electrode extension and connecting electrode.
In addition, in the semiconductor device of an execution mode,
Above-mentioned gate electrode extension is to surround can the mode of welding region being formed on above-mentioned semiconductor layer of above-mentioned drain electrode pad.
Utilize above-mentioned execution mode, even if what the heterogeneous interface of the first semiconductor layer and the second semiconductor layer was formed in drain electrode pad can region on the downside of welding region, by the mode of welding region forming gate electrode extension on the semiconductor layer with what surround drain electrode pad, that effectively can suppress the source electrode of switch element and drain electrode pad can leakage current between welding region.
In addition, in the semiconductor device of an execution mode,
Above-mentioned source electrode has spaced interval and the multiple comb shape source electrode portions be arranged substantially in parallel, and
Above-mentioned drain electrode has and the spaced interval, multiple comb shape source electrode portion of above-mentioned source electrode and the multiple comb shape drain electrode portions be alternately arranged.
Utilize above-mentioned execution mode, the spaced compartment of terrain, multiple comb shape drain electrode portion of multiple comb shape source electrode portion of source electrode and drain electrode be alternately arranged the switch element configured active region near, even if can welding region without what the dielectric film of interlayer dielectric is formed drain electrode pad, that can improve drain electrode pad can withstand voltage between welding region and the source electrode of switch element, thus can reduce component size.
In addition, in the semiconductor device of an execution mode,
Above-mentioned switch element is multiple,
The above-mentioned drain electrode of multiple above-mentioned switch element connects via same above-mentioned drain electrode pad.
Utilizing above-mentioned execution mode, by making multiple switch element share a drain electrode pad, can component size be reduced.
Invention effect
As mentioned above, utilize semiconductor device of the present invention, can when not increasing component size, realize improving without the drain electrode pad that the dielectric film of interlayer dielectric is formed can withstand voltage semiconductor device between welding region and source electrode.
Accompanying drawing explanation
Figure 1A is the schematic top plan view of the semiconductor device of first embodiment of the invention.
Figure 1B is the generalized section of the major part seen from the IB-IB line of Figure 1A.
Fig. 1 C is the schematic top plan view of the size of each several part representing above-mentioned semiconductor device.
Fig. 1 D is the generalized section of the size of the major part representing above-mentioned semiconductor device.
Fig. 1 E is the generalized section of the major part seen from the IE-IE line of Figure 1A.
Fig. 2 A is the schematic top plan view of the semiconductor device of second embodiment of the invention.
Fig. 2 B is the generalized section of the major part seen from the IIB-IIB line of Fig. 2 A.
Fig. 3 A is the schematic top plan view of the semiconductor device of third embodiment of the invention.
Fig. 3 B is the generalized section of the major part seen from the IIIB-IIIB line of Fig. 3 A.
Fig. 4 A is the schematic top plan view of the semiconductor device of four embodiment of the invention.
Fig. 4 B is the generalized section of the major part seen from the IVB-IVB line of Fig. 4 A.
Fig. 5 A is the schematic top plan view of the semiconductor device of fifth embodiment of the invention.
Fig. 5 B is the generalized section of the major part seen from the VB-VB line of Fig. 5 A.
Fig. 6 A is the schematic top plan view of the semiconductor device of sixth embodiment of the invention.
Fig. 6 B is the generalized section of the major part seen from the VIB-VIB line of Fig. 6 A.
Fig. 7 A is the schematic top plan view of the semiconductor device of seventh embodiment of the invention.
Fig. 7 B is the generalized section of the major part seen from the VIIB-VIIB line of Fig. 7 A.
Fig. 8 is the schematic top plan view of the semiconductor device being formed with line.
Fig. 9 is the profile of the major part of grooved semiconductor device.
Figure 10 is the profile of the major part of other groove-shaped semiconductor devices.
Figure 11 is the profile of horizontal type junction type FET.
Figure 12 is the profile of horizontal type power MOSFET.
Figure 13 is the profile of existing horizontal type power device.
Figure 14 A is the schematic top plan view of the semiconductor device of eighth embodiment of the invention.
Figure 14 B is the schematic top plan view of above-mentioned gate electrode when being connected to interelement.
Figure 14 C is the generalized section of the major part seen from the XIVC-XIVC line of Figure 14 A.
Figure 15 A is the schematic top plan view of the semiconductor device of ninth embodiment of the invention.
Figure 15 B is the schematic top plan view of above-mentioned gate electrode when being connected to interelement.
Figure 15 C is the generalized section of the major part seen from the XVC-XVC line of Figure 15 A.
Figure 16 A is the schematic top plan view of the semiconductor device of tenth embodiment of the invention.
Figure 16 B is the schematic top plan view of above-mentioned gate electrode when being connected to interelement.
Figure 16 C is the generalized section of the major part seen from the XVIC-XVIC line of Figure 16 A.
Figure 17 A is the schematic top plan view of the semiconductor device of eleventh embodiment of the invention.
Figure 17 B is the schematic top plan view of above-mentioned gate electrode when being connected to interelement.
Figure 17 C is the generalized section of the major part seen from the XVIIC-XVIIC line of Figure 17 A.
Embodiment
Semiconductor device of the present invention is described in detail referring to illustrated execution mode.
(the first execution mode)
Figure 1A represents the schematic top plan view of the semiconductor device of first embodiment of the invention, is the GaN HFET as semiconductor device one example.
This semiconductor device be formed successively on Si substrate (not shown) as an example of the first semiconductor layer layer of undoped gan 1(as shown in Figure 1B) and as an example of the second semiconductor layer undoped algan layer 2(as shown in Figure 1B).Be 3 μm at this layer of undoped gan 1(thickness) be 30nm with undoped algan layer 2(thickness) interface produce 2DEG(two dimensional electron gas).At this, substrate is not limited to Si substrate, sapphire substrate or SiC substrate can be used, also can on sapphire substrate or SiC substrate, nitride semiconductor layer be grown up, also can on the substrate formed by nitride-based semiconductor, nitride semiconductor layer be grown up, such as, in GaN substrate, make AlGaN layer growth etc.
As shown in Figure 1A, be formed with source electrode 11 at AlGaN layer 2(as shown in Figure 1B), this source electrode 11 has spaced interval and four the comb shape source electrode portion 11a ~ 11d be arranged substantially in parallel and the link base portion 11e linked one end of the source electrode portion 11a ~ 11d of these four comb shapes.In addition, AlGaN layer 2 is formed with drain electrode 12, this drain electrode 12 is by three the comb shape drain electrode portion 12a be arranged between comb shape source electrode portion 11a ~ 11d, and 12b, 12c are formed.In addition, AlGaN layer 2 is formed with gate electrode 13, this gate electrode 13 is by surround each comb shape drain electrode portion 12a, the mode of 12b, 12c and comb shape drain electrode portion 12a, 12b, three gate electrode portion 13a that 12c is formed separated by a distance, 13b, 13c are formed.By above-mentioned source electrode 11, drain electrode 12, gate electrode 13 and be formed with this source electrode 11, drain electrode 12, the active region A1(of the semiconductor layer (GaN layer 1, AlGaN layer 2) of gate electrode 13 is in figure ia with the region that single dotted broken line represents) form switch element S1.
At this, active region A1 is voltage owing to applying the gate electrode 13 between the source electrode 11 be configured in AlGaN layer 2 and drain electrode 12 and between source electrode 11 and drain electrode 12, has semiconductor layer (GaN layer 1, the AlGaN layer 2) region of carrier flow.
Further, in AlGaN layer 2, will be positioned at three gate electrode portion 13a of the opposition side of the link base portion 11e of source electrode 11, one end of 13b, 13c is by connection wiring 21, and 22 connect.
At this, source electrode 11 is 550nm with the thickness of drain electrode 12, and width is 4 μm; The thickness of gate electrode 13 is 200nm, and width is 4.5 μm.
The region except being formed with the region of source electrode 11, drain electrode 12, gate electrode 13 and connection wiring 21 ~ 25 of AlGaN layer is formed for protect the thickness be made up of SiN of AlGaN layer be the dielectric film 30(of 200nm as shown in Figure 1B).In addition, the Si substrate (not shown) being formed with source electrode 11, drain electrode 12, gate electrode 13 is formed the thickness be made up of polyimides be the interlayer dielectric 40(of 9 μm as shown in Figure 1B).
At the link base portion 11e of the ratio source electrode 11 of this interlayer dielectric 40 near the position in outside, the region of 2DEG is eliminated in the part by removing AlGaN layer 2 and GaN layer 1, be formed and expose dielectric film 30(as shown in Figure 1B in bottom) recess 40a, and the drain electrode pad 31(thickness being formed with the region of the link base portion 11e side covering this recess 40a and source electrode 11 is 3 μm).This drain electrode pad 31 and comb shape drain electrode portion 12a, one end of 12b, 12c is overlapping, and in this overlapping region, drain electrode pad 31 and comb shape drain electrode portion 12a, 12b, 12c connect via contact site (not shown).In addition, the dielectric film 30(exposed with the bottom at recess 40a of drain electrode pad 31 is as shown in Figure 2 B) region that connects is can welding region 31a, this can welding region 31a be the region that GaN layer 1 outside the active region A1 being formed with switch element S1 is formed via dielectric film 30.
On the other hand, at above-mentioned interlayer dielectric 40 relative to source electrode 11, side that drain electrode 12 is contrary with recess 40a, GAN layer 1 is formed and exposes dielectric film 30(as shown in Figure 1B in bottom) recess 40b, and the source electrode pad 32(thickness being formed with the region of the opposition side of the link base portion 11e covering this recess 40b and source electrode 11 is 3 μm).This source electrode pad 32 is overlapping with the other end of comb shape source electrode portion 11a ~ 11d, and in this overlapping region, source electrode pad 32 and comb shape drain electrode portion 12a, 12b, 12c connect via contact site (not shown).In addition, the dielectric film 30(exposed with the bottom at recess 40b of source electrode pad 32 is as shown in Figure 1B) region that connects is can welding region 32a.
In addition, source electrode pad 32 can welding region 32a side and in GaN layer 1 across dielectric film 30(as shown in Figure 1B) be formed with this gate electrode pad 33.This gate electrode pad 33 is via connection wiring 23, and 24 are connected with the one end of the gate electrode portion 13c being connected with connection wiring 22.In addition, at source electrode 11 and drain electrode pad 31 can between welding region 31a, the mode of welding region 31a can be formed with gate electrode extension 14 to surround.This gate electrode extension 14 connects via the tie point of connection wiring 25 with connection wiring 23,24.
In addition, source electrode 11 and drain electrode 12 use Ti/Au, the formation such as Hf/Al/Hf/Au, and gate electrode 13, gate electrode extension 14 and connection wiring 21 ~ 25 are used as and the formation such as material such as WN, TiN of AlGaN layer 2 Schottky junction.Drain electrode pad 31, source electrode pad 32, gate electrode pad 33 use the formation such as Ti/Au, Ti/Al.
In addition, the material of dielectric film 30 can use SiO except SiN 2, Al 2o 3deng, the material of interlayer dielectric 40 can use SOG(SpinOnGlass except polyimides, spin-coating glass), BPSG(BoronPhosphorSilicateGlass, boron phosphorus silicate glass) etc. insulating material.
The semiconductor device of this first execution mode is on the Si substrate being formed with GaN layer 1 and AlGaN layer 2, after forming multiple element pattern formed by the source electrode 11 shown in Figure 1A, drain electrode 12, gate electrode 13, a part for the AlGaN layer 2 and GaN layer 1 that remove the region corresponding with electrode pad portion also forms dielectric film 30 and interlayer dielectric 40 successively, the region of removing forms drain electrode pad 31, source electrode pad 32, gate electrode pad 33, carries out cutting along not shown line afterwards and be partitioned into multiple chip.
Figure 1B represents the generalized section of the major part seen from the IB-IB line of Figure 1A, eliminates Si substrate in fig. ib.
As shown in Figure 1B, the 2DEG(two dimensional electron gas formed with the interface of AlGaN layer 2 in GaN layer 1 is produced) and form channel layer.By applying this channel layer of voltage control to gate electrode 13, the HFET conducting with source electrode 11, drain electrode 12 and gate electrode 13 is turned off.This HFET is open type transistor, namely when gate electrode 13 is applied in negative voltage, at gate electrode portion 13a, 13b, 13c(only represent 13c in fig. ib) under GaN layer 1 in form depletion layer, thus be in off state, and when the voltage of gate electrode 13 is zero, at gate electrode portion 13a, 13b, 13c(only represents 13c in fig. ib) under GaN layer 1 in depletion layer disappear, thus be in conducting state.
Be applied in negative voltage and form the off state of depletion layer in GaN layer 1 under at gate electrode 13, the region of GaN layer 1 between welding region 31a can form depletion layer because of the gate electrode extension 14 that can exist between welding region 31a and the active region A1 of the transistor surrounded by single dotted broken line as shown in Figure 1A at drain electrode pad 31 at the link base portion 11e of source electrode 11 and drain electrode pad 31.Thereby, it is possible to effectively suppress at the link base portion 11e of source electrode 11 and drain electrode pad 31 can leakage current between welding region 31a, thus improve withstand voltage.
Fig. 1 C represents the schematic top plan view of the size of each several part of above-mentioned semiconductor device, the Reference numeral that mark is identical with the semiconductor device shown in Figure 1A in fig. 1 c.
In fig. 1 c, the size of drain electrode pad 31 and the left and right directions at Fig. 1 C of source electrode pad 32 changes and changes along with the index (Off ィ ン ガ ー number) of source electrode 11 with drain electrode 12.
Fig. 1 D represents the generalized section of the size of the major part of above-mentioned semiconductor device, in Fig. 1 D, the link base portion 11e of source electrode 11 and drain electrode pad 31 can welding region 31a be spaced apart 53 μm.
In addition, Fig. 1 E is the generalized section of the major part seen from the IE-IE line of Figure 1A.It should be noted that, in fig. ie, in order to easily see figure, the thickness in Thickness Ratio Figure 1B of interlayer dielectric 40 is thin.
As referring to figure 1e, Si substrate 10 is formed by layer of undoped gan 1 and undoped algan layer 2(as shown in Figure 1B) semiconductor layer 20 that forms.
In addition, drain electrode pad 31 and three comb shape drain electrode portion 12a, 12b, 12c(only represents 12a in fig. ie)) connect via the through hole 45 as contact site, contact site is not limited to through hole 45, and the opening arranged on interlayer dielectric etc. can be utilized to connect drain electrode and drain electrode pad (and source electrode and source electrode pad).
In addition, gate electrode 13(only represents gate electrode portion 13a in fig. ie) be formed as the shape becoming field plate structure, and the drain side being configured to gate electrode 13 reaches on dielectric film 30.By being configured to such field plate structure, obtain the effect of the avalanche characteristic of the HFET problem that can suppress as GaN.
Utilize the semiconductor device with said structure, at source electrode 11 and drain electrode pad 31 can between welding region 31, by forming the gate electrode extension 14 be connected with gate electrode 13, control the voltage that is applied on gate electrode 13 and gate electrode extension 14 voltage and source electrode 11 and drain electrode pad 31 can gate electrode extension 14 between welding region 31a downside GaN layer 1 in form depletion layer, thus can effectively suppress leakage current and improve withstand voltage.Therefore, it is possible to when not increasing component size, improve without the drain electrode pad 31 that the dielectric film 30 of interlayer dielectric 40 is formed can withstand voltage between welding region 31a and source electrode 11.
In addition, by the mode of welding region 31a forming gate electrode extension 14 in AlGaN layer 2 with what surround drain electrode pad 31, that reliably can suppress source electrode 11 and drain electrode pad 31 can leakage current between welding region 31a.
In addition, at multiple comb shape source electrode portion 11a ~ 11d of source electrode 11 and multiple comb shape drain electrode portion 12a of drain electrode 12,12b, the spaced interval of 12c and be alternately arranged configuration active region near, even if can welding region 31a without what the dielectric film 30 of interlayer dielectric 40 is formed drain electrode pad 31, that also can improve drain electrode pad 31 can withstand voltage between welding region 31a and source electrode 11 can reduce component size.
(the second execution mode)
Fig. 2 A represents the schematic top plan view of the semiconductor device of second embodiment of the invention.The semiconductor device of this second execution mode, except a part of this point not removing semiconductor layer, has the structure identical with the semiconductor device of the first execution mode, marks identical Reference numeral and omit the description for identical structure division.
As shown in Figure 2 A and 2 B, the semiconductor device of above-mentioned second execution mode is when do not remove outside the active region of transistor AlGaN layer 2, and what AlGaN layer 2 arranged drain electrode pad 31 can welding region 31a.And, the mode of welding region 31a can be provided with gate electrode extension 14 in AlGaN layer 2 to surround.
Negative voltage is applied in and form the off state of depletion layer in GaN layer 1 under at gate electrode 13, also be applied in negative voltage at the gate electrode extension 14 that can be formed between welding region 31a and the active region A1 of transistor of drain electrode pad 31 and form depletion layer, that effectively can suppress the link base portion 11e of source electrode 11 and drain electrode pad 31 thus can leakage current between welding region 31a.Like this, by arranging gate electrode extension 14, that can improve between source electrode 11 and drain electrode pad 31 is withstand voltage, even if therefore there is 2DEG under drain electrode pad, also it doesn't matter.By forming such structure, without the need to removing AlGaN layer 2, so serve the subsidiary effect that can reduce manufacturing cost.
(the 3rd execution mode)
Fig. 3 A represents the schematic top plan view of the semiconductor device of third embodiment of the invention.The semiconductor device of the 3rd execution mode except by drain electrode pad can except the connecting electrode that is connected with semiconductor layer of welding region, there is the structure identical with the semiconductor device of the second execution mode, for identical structure division, mark identical Reference numeral and omit the description.
As shown in Figure 3A, the semiconductor device of the 3rd execution mode drain electrode pad 31 the dielectric film 30(exposed with the bottom at recess 40a as shown in Figure 3 B) region that connects, along the outer rim of welding region 31a being formed with that connect can the connecting electrode 50 of welding region 31a and AlGaN layer 2.
Fig. 3 B represents the generalized section of the major part seen from the IIIB-IIIB line of Fig. 3 A, be applied in negative voltage and form the off state of depletion layer in GaN layer 1 under at gate electrode 13, because of drain electrode pad 31 the gate electrode extension 14 that can exist between welding region 31a and the active region of transistor surrounded with dotted line and the region of GaN layer 1 between welding region 31a can form depletion layer at the link base portion 11e of source electrode 11 and drain electrode pad 31.
Thereby, it is possible to effectively suppress the link base portion 11e of source electrode 11 and drain electrode pad 31 can leakage current between welding region 31a, thus improve withstand voltage.
And, what connect drain electrode pad 31 owing to utilizing the connecting electrode 50 running through dielectric film 30 can welding region 31a and AlGaN layer 2, thus the dielectric film 30 on the downside of welding region 31a can not apply electric field at drain electrode pad 31, the insulation breakdown of dielectric film 30 can be prevented.
Utilize the semiconductor device of above-mentioned 3rd execution mode, there is the effect identical with the semiconductor device of the second execution mode.
(the 4th execution mode)
Fig. 4 A represents the schematic top plan view of the semiconductor device of four embodiment of the invention, and Fig. 4 B represents the generalized section of the major part seen from the IVB-IVB line of Fig. 4 A.The semiconductor device of the 4th execution mode, except having territory, element separation area, has the structure identical with the semiconductor device of the 3rd execution mode, marks identical Reference numeral and omit the description for identical structure division.
As shown in Figure 4 A and 4 B shown in FIG., the semiconductor device of the 4th execution mode gate electrode extension 14 and and the link base portion 11e of the adjacent source electrode 11 of this gate electrode extension 14 between GaN layer 1, AlGaN layer 2 region, formed and run through AlGaN layer 2 and the territory, element separation area 60 imbedding a upside part for GaN layer 1.This territory, element separation area 60 is made up of insulator, especially can be silicon oxide film or silicon nitride film.
Utilize the semiconductor device of above-mentioned 4th execution mode, there is the effect identical with the semiconductor device of the 3rd execution mode.
In addition, even if form dummy transistor (part surrounded with dotted line) by the link base portion 11e of source electrode 11, gate electrode extension 14 and connecting electrode 50, due to gate electrode extension 14 and and the adjacent source electrode 11 of this gate electrode extension 14 between semiconductor layer (GaN layer 1, AlGaN layer 2) region forming element separated region 60, the link base portion 11e of the source electrode 11 forming dummy transistor is separated with gate electrode extension 14 by territory, element separation area 60, thus reliably can prevents the misoperation of dummy transistor.
(the 5th execution mode)
Fig. 5 A is the schematic top plan view of the semiconductor device representing fifth embodiment of the invention, is the GaN HFET as semiconductor device one example.
This semiconductor device formed successively on Si substrate (not shown) as the first semiconductor layer one example layer of undoped gan 101(as shown in Figure 5 B) and as the second semiconductor layer one example undoped algan layer 102(as shown in Figure 5 B).Be 3 μm at this layer of undoped gan 101(thickness) and undoped algan layer 102(thickness be 30nm) interface produce 2DEG(two dimensional electron gas).At this, substrate is not limited to Si substrate, sapphire substrate or SiC substrate can be used, also can on sapphire substrate or SiC substrate, nitride semiconductor layer be grown up, also can on the substrate formed by nitride-based semiconductor, nitride semiconductor layer be grown up, such as, in GaN substrate, make AlGaN layer growth etc.
As shown in Figure 5A, AlGaN layer 102 is formed source electrode 111, and this source electrode 111 has spaced interval and four the comb shape source electrode portion 111a ~ 111d be arranged substantially in parallel and the link base portion 111e linked one end of these four comb shape source electrode portion 111a ~ 111d.At this, the link base portion 111e of source electrode 111 is arranged at the opposition side of the link base portion 11e of the source electrode 11 of the semiconductor device as shown in Figure 1A of the first execution mode.
In addition, AlGaN layer 102 is formed with drain electrode 112, this drain electrode 112 is by three the comb shape drain electrode portion 112a be arranged between comb shape source electrode portion 111a ~ 111d, and 112b, 112c are formed.In addition, AlGaN layer 102 is formed gate electrode 113, this gate electrode 113 is by surround comb shape drain electrode portion 112a respectively, 112b, the mode phase of 112c and comb shape drain electrode portion 112a, three gate electrode portion 113a of 112b, 112c formation spaced apart, 113b, 113c are formed.Gate electrode portion 113a is formed as having end a1 in the side (opposition side of the link base portion 111e of source electrode 111) of gate electrode portion 113a, the コ shape of a2, gate electrode portion 113b is formed as having end b1 in the side (opposition side of the link base portion 111e of source electrode 111) of gate electrode portion 113b, the コ shape of b2, gate electrode portion 113c defines has end c1, the コ shape of c2 in the side (opposition side of the link base portion 111e of source electrode 111) of gate electrode portion 113c.By above-mentioned source electrode 111, drain electrode 112, gate electrode 113 and be formed this source electrode 111, drain electrode 112, gate electrode 113 the active region of semiconductor layer (GaN layer 101, AlGaN layer 102) form switch element S101.
The end a2 adjacent to each other of the open side of above-mentioned gate electrode portion 113a, 113b, b1 utilizes gate electrode extension 115 to connect, and the end b2 adjacent to each other of the open side of gate electrode portion 113b, 113c, c1 utilizes gate electrode extension 116 to connect.The outboard end a1 of the open side of gate electrode portion 113a and the outboard end c2 of the open side of gate electrode portion 113c utilize and surround and can the コ shape gate electrode extension 114 of a part of welding region 131a be connected.
At this, source electrode 111 and the thickness of drain electrode 112 are 550nm, width is 4 μm, and the thickness of gate electrode 113 is 200nm, and width is 4.5 μm.
In AlGaN layer 102 except being formed with source electrode 111, drain electrode 112, gate electrode 113, gate electrode extension 114 described later; 115; 116 and connection wiring 121 region beyond region; in order to protect AlGaN layer 102, be formed the thickness be made up of SiN be the dielectric film 130(of 200nm as shown in Figure 5 B).In addition, be formed source electrode 111, drain electrode 112, gate electrode 113 Si substrate (not shown) above formed the thickness be made up of polyimides be the interlayer dielectric 140(of 9 μm as shown in Figure 5 B).
This interlayer dielectric 140 relative to source electrode 111, drain electrode 112 than gate electrode extension 115,116 to be formed near the position in outside expose dielectric film 130(as shown in Figure 5 B in bottom) recess 140a, and the drain electrode pad 131(thickness forming the region of the link base portion 111e opposition side of the source electrode 111 covered near this recess 140a and recess 140a is 3 μm).This drain electrode pad 131 and comb shape drain electrode portion 112a, 112b, one end of the opposition side of the link base portion 111e of the source electrode 111 of 112c is overlapping, drain electrode pad 131 and comb shape drain electrode portion 112a is connected via contact site (not shown) in this overlapping region, 112b, 112c.In addition, the dielectric film 130(exposed with the bottom at recess 140a of drain electrode pad 131 is as shown in Figure 5 B) region that connects is can welding region 131a.
On the other hand, in the position being positioned at the opposition side of recess 140a relative to source electrode 111, drain electrode 112 of above-mentioned interlayer dielectric 140, be formed in bottom and expose dielectric film 130(as shown in Figure 5 B) recess 140b, and the source electrode pad 132(thickness forming the region of the link base portion 111e side covering this recess 140b and source electrode 111 is 3 μm).This source electrode pad 132 is overlapping with one end of the link base portion 111e side of comb shape source electrode portion 111a ~ 111d, connects source electrode pad 132 and comb shape source electrode portion 111a ~ 111d in this overlapping region via contact site (not shown).In addition, the dielectric film 130(exposed with the bottom at recess 140b of source electrode pad 132 is as shown in Figure 5 B) region that connects is can welding region 132a.
In addition, in AlGaN layer 102 and source electrode pad 132 can the side of welding region 132a, via dielectric film 130(as shown in Figure 5 B) be formed with this gate electrode pad 133.This gate electrode pad 133 is connected with an end c2 of gate electrode portion 113c via connection wiring 121.
In addition, source electrode 111 and drain electrode 112 use the formation such as Ti/Au, Hf/Al/Hf/Au, gate electrode 113 and gate electrode extension 114,115,116 are used as and the formation such as material such as WN/W, TiN/Ti of AlGaN layer 102 Schottky junction.Further, drain electrode pad 131, source electrode pad 132 and gate electrode pad 133 use the formation such as Ti/Au or Ti/Al.
In addition, the material of dielectric film 130 can use SiO except SiN 2, Al 2o 3deng, the material of interlayer dielectric 140 can use the insulating material such as SOG, BPSG except polyimides.
The semiconductor device of the 5th execution mode is on the SI substrate being formed with GaN layer 101 and AlGaN layer 102, after forming an element pattern of multiple source electrode 111, drain electrode 112 and gate electrode 113 as shown in Figure 5A, form dielectric film 130 and interlayer dielectric 140 successively, and after forming drain electrode pad 131, source electrode pad 132 and the gate electrode pad 133 corresponding with each element pattern, carry out cutting along not shown line and be partitioned into multiple chip.
Fig. 5 B represents the generalized section of the major part seen from the VB-VB line of Fig. 5 A, eliminates Si substrate in figure 5b.
As shown in Figure 5 B, the 2DEG(two dimensional electron gas formed with the interface of AlGaN layer 102 in GaN layer 101 is produced) and form channel layer.By applying this channel layer of voltage control to gate electrode 113, make the HFET conducting shutoff with source electrode 111, drain electrode 112, gate electrode 113.This HFET is open type transistor, namely when gate electrode 113 is applied in negative voltage, at gate electrode portion 131a, 113b, 113c and gate electrode extension 114,115,116(only represent 114 in figure 5b, 116) depletion layer is formed in the GaN layer 1 under, thus be in off state, on the other hand, when the voltage of gate electrode 13 is zero, at gate electrode portion 13a, 13b, 13c and gate electrode extension 114,115, depletion layer in GaN layer 1 under 116 disappears, thus is in conducting state.
Negative voltage is applied in and form the off state of depletion layer in GaN layer 1 under at gate electrode 13, because of the gate electrode extension 115 that can exist between welding region 131a and the active region of transistor at drain electrode pad 131, 116(only represents 116 in figure 5b) and depletion layer can be formed in GaN layer 101 region between welding region 131a at the comb shape source electrode portion 111c of source electrode 111 and drain electrode pad 131, that effectively can suppress the comb shape source electrode portion 111c of source electrode 111 and drain electrode pad 131 thus can leakage current between welding region 131a, thus improve withstand voltage.
Utilize the semiconductor device of above-mentioned 5th execution mode, there is the effect identical with the semiconductor device of the first execution mode.
(the 6th execution mode)
Fig. 6 A represents the schematic top plan view of the semiconductor device of sixth embodiment of the invention.The semiconductor device of the 6th execution mode except by drain electrode pad can except the connecting electrode that is connected with semiconductor layer of welding region, with the semiconductor device of the 5th execution mode, there is identical structure, for identical structure division, mark identical Reference numeral and omit the description.
As shown in Figure 6A, the semiconductor device of the 6th execution mode drain electrode pad 131 the dielectric film 130(exposed with the bottom at recess 140a as shown in Figure 6B) region that connects, along the outer rim of welding region 131a being formed with that connect can the connecting electrode 150 of welding region 131a and AlGaN layer 102.
Fig. 6 B represents the generalized section of the major part seen from the VIB-VIB line of Fig. 6 A.Negative voltage is applied in and form the off state of depletion layer in GaN layer 101 under at gate electrode 113, because the gate electrode extension 115,116(that can exist between welding region 131a and the active region of transistor at drain electrode pad 131 only represents 116 in fig. 6b) and depletion layer can be formed in GaN layer 101 region between welding region 131a at the comb shape source electrode portion 111c of source electrode 111 and drain electrode pad 131.
Thereby, it is possible to effectively suppress at the comb shape source electrode portion 111c of source electrode 111 and drain electrode pad 131 can between welding region 131a, the leakage current namely between source electrode 111 and drain electrode 112, thus improve withstand voltage.
And, what connect drain electrode pad 131 owing to utilizing the connecting electrode 150 running through dielectric film 130 can welding region 131a and AlGaN layer 102, dielectric film 130 on the downside of welding region 131a can not apply electric field at drain electrode pad 131, thus the insulation breakdown of dielectric film 130 can be prevented.
Utilize the semiconductor device of above-mentioned 6th execution mode, there is the effect identical with the semiconductor device of the first execution mode.
(the 7th execution mode)
Fig. 7 A represents the schematic top plan view of the semiconductor device of seventh embodiment of the invention.The semiconductor device of the 7th execution mode, except territory, element separation area, has the structure identical with the semiconductor device of the 6th execution mode, for identical structure division, marks identical Reference numeral and omits the description.
Fig. 7 B represents the generalized section of the major part seen from the VIIB-VIIB line of Fig. 7 A.As shown in Figure 7 B, the semiconductor device of the 7th execution mode gate electrode extension 114 and and the link base portion 111e of the adjacent source electrode 111 of this gate electrode extension 114 between GaN layer 101, AlGaN layer 102 region, formed and run through AlGaN layer 102 and the territory, element separation area 160 imbedding a upside part for GaN layer 101.This territory, element separation area 160 is made up of insulator, especially can be silicon oxide film or silicon nitride film.
Utilize the semiconductor device of above-mentioned 7th execution mode, there is the effect identical with the semiconductor device of the second execution mode.
In addition, even if by the comb shape source electrode portion 111c of source electrode 111, gate electrode extension 115, 116 and connecting electrode 150 form dummy transistor (part surrounded with dotted line), due to gate electrode extension 114 and and the adjacent source electrode 111 of this gate electrode extension 114 between semiconductor layer (GaN layer 101, AlGaN layer 102) region forming element separated region 160, territory, element separation area 160 can be utilized to form comb shape source electrode portion 111c and the gate electrode extension 115 of the source electrode 111 of dummy transistor, 116 are separated, thus reliably can prevent the misoperation of dummy transistor.
It should be noted that, in the semiconductor device of the first execution mode, describe and carry out cutting along line and be partitioned into the content of multiple chip.Fig. 8 is on the basis of the semiconductor device structure as shown in Figure 1A of the first execution mode, be formed with the schematic top plan view of the semiconductor device of line 70 further, wherein the element pattern formed by source electrode 11, drain electrode 12, gate electrode 13 is surrounded in line 70.
In fig. 8, when gate electrode extension 14 and connection wiring 25 tie point A apart from rule 70 beeline x be 70 μm time, under source electrode is 0V and gate electrode is the condition of-10V, the maximum voltage that can put on drain electrode is 700V.
Under identical conditions, when beeline x is 100 μm, the maximum voltage that can put on drain electrode is 900V, and when beeline x is 150 μm, the maximum voltage that can put on drain electrode is 1200V.
Like this, by guarantee the tie point A of gate electrode extension 14 and connection wiring 25 apart from rule 70 beeline x be predetermined distance, the atmospherical discharges produced between line 70 and tie point A can be suppressed, thus can improve withstand voltage.
(the 8th execution mode)
Figure 14 A and Figure 14 B represents the schematic top plan view of the semiconductor device of eighth embodiment of the invention.The semiconductor device of the 8th execution mode utilizes drain electrode pad 31 two to be had the switch element S1 with the semiconductor device same structure of the second execution mode, and S2 connects, and marks identical Reference numeral and omit the description for identical structure division.
At this, the semiconductor device of Figure 14 A is the example of the structure that the gate electrode pad 33 of the switch element S2 of downside is not connected with gate electrode extension 14, and the semiconductor device of Figure 14 B does not arrange gate electrode pad in the switch element S2 side of downside and gate electrode 13 is connected to the example of the structure of gate electrode extension 14 via connection wiring 25.
In addition, Figure 14 C is the generalized section of the major part seen from the XIVC-XIVC line of Figure 14 A and Figure 14 B.
As shown in Figure 14 C, this semiconductor device does not remove switch element S1, the active region A1 of S2, the AlGaN layer 2 outside A2, and is provided with drain electrode pad 31 on AlGaN2 layer.In addition, in AlGaN layer 2, gate electrode extension 14 is provided with in the mode of surrounding the region that drain electrode pad 31 contacts in AlGaN layer 2.
In the semiconductor device with said structure, negative voltage is applied in and form the off state of depletion layer in GaN layer 1 under at gate electrode 13, be formed at the active region A1 of region that drain electrode pad 31 contacts on AlGaN2 layer and transistor, gate electrode extension 14 between A2 has also been applied in negative voltage, thus forms depletion layer.Thereby, it is possible to effectively suppress the leakage current between the region that contacts in AlGaN layer 2 at link base portion 11e and the drain electrode pad 31 of source electrode 11.Thus, by arranging gate electrode extension 14, that can improve between source electrode 11 and drain electrode pad 31 is withstand voltage, even if there is 2DEG 31 times at drain electrode pad, also it doesn't matter.Utilize such structure, because without the need to removing AlGaN, so the subsidiary effect reducing manufacturing cost also can be played.
Above-mentioned 8th execution mode semiconductor device has the effect identical with the semiconductor device of the second execution mode.
In addition, due to the public drain electrode pad 31 of above-mentioned two switch element S1, S2, therefore, it is possible to reduce component size.
It should be noted that, drain electrode pad 31 might not weld, and the difference according to loop is not also welded sometimes.
In addition, in the above-described 8th embodiment, describe the semiconductor device with two closing element structures, but the present invention also goes for the semiconductor device with three above structures of switch element.
(the 9th execution mode)
Figure 15 A and Figure 15 B represents the schematic top plan view of the semiconductor device of ninth embodiment of the invention.The semiconductor device of the 9th execution mode has the structure identical with the semiconductor device of the 8th execution mode except connecting electrode 50, marks identical Reference numeral and omit the description for identical structure division.
At this, the semiconductor device of Figure 15 A is the example of the structure that the gate electrode pad 33 of the switch element S2 of downside is not connected with gate electrode extension 14, and the semiconductor device of Figure 15 B does not arrange gate electrode pad in the switch element S2 side of downside and gate electrode 13 is connected to the example of the structure of gate electrode extension 14 via connection wiring 25.
As shown in fig. 15 a and fig. 15b, the semiconductor device of the 9th execution mode drain electrode pad 31 the dielectric film 30(exposed with the bottom at recess 40a as shown in figure 15 c) region that connects, along the outer rim of welding region 31a being formed with that connect can the connecting electrode 50 of welding region 31a and AlGaN layer 2.
Figure 15 C is the generalized section of the major part seen from the XVC-XVC line of Figure 15 A and Figure 15 B, negative voltage is applied in and be formed with the off state of depletion layer in GaN layer 1 under at gate electrode 13, therefore at drain electrode pad 31 can the active region A1 of welding region 31a and the transistor surrounded with dotted line, the gate electrode extension 14 existed between A2 and depletion layer can be formed in GaN layer 1 region between welding region 31a at the link base portion 11e of source electrode 11 and drain electrode pad 31.
Thereby, it is possible to effectively suppress at the link base portion 11e of source electrode 11 and drain electrode pad 31 can leakage current between welding region 31a, thus improve withstand voltage.
And, what connect drain electrode pad 31 owing to utilizing the connecting electrode 50 running through dielectric film 30 can welding region 31a and AlGaN layer 2, no longer can be applied with electric field by dielectric film 30 on the downside of welding region 31a to drain electrode pad 31, thus the insulation breakdown of dielectric film 30 can be prevented.
The semiconductor device of above-mentioned 9th execution mode has the effect identical with the semiconductor device of the 8th execution mode.
(the tenth execution mode)
Figure 16 A and Figure 16 B represents the schematic top plan view of the semiconductor device of tenth embodiment of the invention.The semiconductor device of the tenth execution mode, except territory, element separation area 60, has the structure identical with the semiconductor device of the 9th execution mode, marks identical Reference numeral and omit the description for identical structure division.
At this, the semiconductor device of Figure 16 A is the example of the structure that the gate electrode pad 33 of the switch element S2 of downside is not connected with gate electrode extension 14, and the semiconductor device of Figure 16 B does not arrange gate electrode pad in the switch element S2 side of downside and gate electrode 13 is connected to the example of the structure of gate electrode extension 14 via connection wiring 25.
As shown in Figure 16 A, Figure 16 B and Figure 16 C, the semiconductor device of the tenth execution mode gate electrode extension 14 and and the link base portion 11e of the adjacent source electrode 11 of this gate electrode extension 14 between GaN layer 1, AlGaN layer 2 region, formed and run through AlGaN layer 2 and the territory, element separation area 60 imbedding a upside part for GaN layer 1.This territory, element separation area 60 is made up of insulator, especially can be silicon oxide film or silicon nitride film.
The semiconductor device of this above-mentioned tenth execution mode has the effect identical with the semiconductor device of the 9th execution mode.
In addition, even if form dummy transistor (part surrounded with dotted line) by the link base portion 11e of source electrode 11, gate electrode extension 14 and connecting electrode 50, due to gate electrode extension 14 and and the adjacent source electrode 11 of this gate electrode extension 14 between semiconductor layer (GaN layer 1, AlGaN layer 2) region be formed with territory, element separation area 60, utilize territory, element separation area 60 to be separated with gate electrode extension 14 by the link base portion 11e of the source electrode 11 forming dummy transistor, thus reliably can prevent the misoperation of dummy transistor.
(the 11 execution mode)
Figure 17 A and Figure 17 B represents the schematic top plan view of the semiconductor device of eleventh embodiment of the invention.The semiconductor device of the 11 execution mode, except removing a part of this point of semiconductor layer, has the structure identical with the semiconductor device of the 9th execution mode, marks identical Reference numeral and omit the description for identical structure division.
At this, the semiconductor device of Figure 17 A is the example of the structure that the gate electrode pad 33 of the switch element S2 of downside is not connected with gate electrode extension 14, and Figure 17 B semiconductor device does not arrange gate electrode pad in the switch element S2 side of downside and gate electrode 13 is connected to the example of the structure of gate electrode extension 14 via connection wiring 25.
At the link base portion 11e of the ratio source electrode 11 of this interlayer dielectric 40 near the position in outside, the region of 2DEG is eliminated in the part by removing AlGaN layer 2 and GaN layer 1, be formed in bottom and expose dielectric film 30(as shown in Figure 17 C) recess 40a, and form the drain electrode pad 31 in the region of the link base portion 11e side covering this recess 40a and source electrode 11.
In addition, the semiconductor device of above-mentioned 11 execution mode has the effect identical with the semiconductor device of the 9th execution mode.
For at 2DEG(two dimensional electron gas) and dielectric film on electrode pad between withstand voltage test in the probability of insulation breakdown, there is no gate electrode extension 14,114 ~ 116, connecting electrode 50, the probability of the semiconductor dress of the structure of 150 is about 40%, and the probability of above-mentioned first ~ the 11 execution mode has reduced to 0% significantly.
In addition, in above-mentioned first ~ the 11 execution mode, to describe on substrate lamination GaN layer 1 successively, 101 and AlGaN layer 2, the HFET of 102, but the present invention also to go on substrate successively lamination GaAs layer and n-AlGaAs layer to replace the HFET of GaN layer, AlGaN layer.
In addition, in above-mentioned first ~ the 11 execution mode, describe the finger-type HFET respectively with multiple gate electrode, source electrode and drain electrode, but semiconductor device of the present invention is not limited thereto, the present invention also goes for the semiconductor device comprising the switch element with a group of gate electrode, source electrode and drain electrode.
In addition, in above-mentioned first ~ the 11 execution mode, describe open type HFET, but semiconductor device of the present invention is not limited thereto, the present invention also goes for closed type HFET.
Such as, Fig. 9 represents the profile of the major part of grooved semiconductor device, is the GaN HFET of the example as semiconductor device.Eliminate interlayer dielectric and electrode pad in fig .9.
This semiconductor device is formed successively as the layer of undoped gan 201 of the first semiconductor layer one example and the undoped algan layer 202 as the second semiconductor layer one example on Si substrate (not shown).2DEG(two dimensional electron gas is produced with the interface of undoped algan layer 202) in this layer of undoped gan 201.Identically with above-mentioned first ~ the 11 execution mode, substrate is not limited to Si substrate, sapphire substrate or SiC substrate can be used, also can make to stop up compound semiconductor layer to grow up on sapphire substrate or SiC substrate, also can on the substrate formed by nitride-based semiconductor, nitride semiconductor layer be grown up, such as, in GaN substrate, make AlGaN layer growth etc.
AlGaN layer 202 forms source electrode 211 and drain electrode 212 with separating predetermined distance.Source electrode 211 side between source electrode 211 and drain electrode 212, is provided with recess 200 on AlGaN layer 202 top.The region except this recess 200, source electrode 211, drain electrode 212 of AlGaN layer 202 forms the first dielectric film 230, and forms the second dielectric film 240 of covering first dielectric film 230 and recess 200.Further, gate electrode 213 is formed by the base portion 213a imbedded in the recess 200 that covered by the second dielectric film 240 and the field plate portion 213b formed on this base portion 213a top.
In semiconductor device as shown in Figure 9, the base portion 213a of gate electrode 213 is imbedded in the recess 200 that a part on the upside of AlGaN layer 202 is formed, AlGaN layer 202 contacts with gate electrode 213 via the first dielectric film 230, thus there is not 2DEG(two dimensional electron gas in the heterogeneous interface under gate electrode 213), threshold voltage raises, and makes the normally closed action of switch element become possibility.
In addition, Figure 10 represents the profile of the major part of other groove-shaped semiconductor devices, is the GaN HFET as semiconductor device one example.In Fig. 10, interlayer dielectric and electrode pad is eliminated.
This semiconductor device is formed successively as the layer of undoped gan 201 of the first semiconductor layer one example and the undoped algan layer 302 as the second semiconductor layer one example on Si substrate (not shown).2DEG(two dimensional electron gas is produced) at the interface of this layer of undoped gan 301 and undoped algan layer 302.
AlGaN layer 302 forms active pole electrode 311 and drain electrode 312 with separating predetermined distance.Source electrode 311 side between source electrode 311 and drain electrode 312, runs through AlGaN layer 302 and a part for the upside of GaN layer 301 is provided with recess 300.The region except this recess 300, source electrode 311 and drain electrode 312 of AlGaN layer 302 is formed with the first dielectric film 330.And form the second dielectric film 340 of covering first dielectric film 330 and recess 300.Further, gate electrode 313 is formed by the base portion 313a imbedded in the recess 300 that covered by the second dielectric film 340 and the field plate portion 313b formed on this base portion 313a top.
In the semiconductor device shown in Figure 10, run through AlGaN layer 302 and in the recess 300 that the upside of GaN layer 301 part is formed, imbed the base portion 313a of gate electrode 313, thus utilize gate electrode 313 that the heterogeneous interface of GaN layer 301 and AlGaN layer 302 is interdicted by gate electrode 313, there is not 2DEG(two dimensional electron gas), threshold voltage raises, and makes the normally closed action of switch element become possibility.
In the semiconductor device with structure as shown in Figure 9 and Figure 10, by the gate electrode extension be connected with the gate electrode of switch element is formed on the semiconductor layer and be at least formed in source electrode and drain electrode pad between welding region, also can be suitable for the present invention.Thereby, it is possible to when not increasing component size, realize improving without the drain electrode pad that the dielectric film of interlayer dielectric is formed can withstand voltage closed type HFET between welding region and source electrode.
In addition, semiconductor device of the present invention is not limited to HFET, and the present invention also goes for the semiconductor device of the charge carrier such as horizontal type junction type FET as shown in figure 11 and horizontal type power MOSFET as shown in figure 12 along real estate movement in the horizontal.
In the Figure 11 of general structure representing horizontal type junction type FET, 401 are n-type semiconductor substrates, 413 is gate electrodes, and 421 is source region, and 422 is drain region, and 423 is grid layer, and 430 is dielectric film, and 440 is oxide-film.
In addition, in the Figure 12 of general structure representing horizontal type power MOSFET, 501 is p-type semiconductor substrates, and 511 is source electrodes, and 512 is drain electrodes, and 513 is gate electrodes, and 521 is source regions, and 522 is drain regions, and 530 is dielectric films.
In the semiconductor device with structure as is illustrated by figs. 11 and 12, by the gate electrode extension be connected with the gate electrode of switch element is formed on the semiconductor layer and be at least formed in the source electrode of switch element and drain electrode pad between welding region, also can be suitable for the present invention.Thereby, it is possible to when not increasing component size, realize improving without the drain electrode pad that the dielectric film of interlayer dielectric is formed can withstand voltage closed type HFET between welding region and source electrode.
Be explained above the specific embodiment of the present invention, but the invention is not restricted to above-mentioned execution mode, can various change be carried out and implement within the scope of the invention.
Symbol description
1,101 ... GaN layer
2,102 ... AlGaN layer
11,111 ... source electrode
11a ~ 11d, 111a ~ 111d ... comb shape source electrode portion
11e, 111e ... link base portion
12,112 ... drain electrode
12a, 12b, 12c, 112a, 112b, 112c ... comb shape drain electrode portion
13,113 ... gate electrode
13a, 13b, 13c, 113a, 113b, 113c ... gate electrode portion
14,114,115,116 ... gate electrode extension
21 ~ 25,121 ... connection wiring
30,130 ... dielectric film
31,131 ... drain electrode pad
31a, 131a ... can welding region
32,132 ... source electrode pad
32a, 132a ... can welding region
33,133 ... gate electrode pad
40,140 ... interlayer dielectric
40a, 40b, 140a, 140b ... recess
45 ... through hole
50,150 ... connecting electrode
60,160 ... territory, element separation area
200,300 ... recess
201,301 ... GaN layer
202,302 ... AlGal layer
211,311 ... source electrode
212,312 ... drain electrode
213,313 ... gate electrode
213a, 313a ... base portion
213b, 313b ... field plate portion
401 ... n-type semiconductor substrate
413 ... gate electrode
421 ... source region
422 ... drain region
423 ... grid layer
430 ... dielectric film
440 ... oxide-film
501 ... p-type semiconductor substrate
511 ... source electrode
512 ... drain electrode
513 ... gate electrode
521 ... source region
522 ... drain region
530 .... dielectric film
A1, A2 .... active region
S1, S2, S101 ... switch element

Claims (9)

1. a semiconductor device, is characterized in that, comprising:
Substrate;
Semiconductor layer (1,2,101,102), is formed on the substrate and includes source region;
Switch element (S1, S2, S101), has at described semiconductor layer (1,2,101,102) gate electrode (13 that described active region is formed, 113), source electrode (11,111) and drain electrode (12,112);
Drain electrode pad (31,131), with described drain electrode (12,112) connect, have at described semiconductor layer (1,2,101,102) on the region beyond described active region across dielectric film (30,130) formed can welding region;
Gate electrode extension (14,114,115,116), be formed in described semiconductor layer (1,2,101,102) go up and be at least formed in described source electrode (11,111) with described drain electrode pad (31,131) between welding region, can connect with described gate electrode (13,113);
Described gate electrode extension (14,114,115,116) runs through described dielectric film (30,130) and described semiconductor layer (1,2,101,102) Schottky junction.
2. semiconductor device as claimed in claim 1, is characterized in that,
Described semiconductor layer (1,2,101,102) the first semiconductor layer (1 of lamination successively is on the substrate comprised, 101) and with this first semiconductor layer (1,101) second semiconductor layer (2,102) of heterogeneous interface is formed;
Described switch element (S1, S2, S101) is the HFET utilizing the two dimensional electron gas formed with the heterogeneous interface of described second semiconductor layer (2,102) at described first semiconductor layer (1,101).
3. semiconductor device as claimed in claim 2, is characterized in that,
Form described first semiconductor layer (1 of described two dimensional electron gas, 101) with described second semiconductor layer (2,102) heterogeneous interface be formed at least except described drain electrode pad (31,131) can region on the described substrate beyond welding region underside area.
4. semiconductor device as claimed in claim 2, is characterized in that,
Run through described second semiconductor layer (2,102) part of upside or run through described second semiconductor layer (2,102) recess (200,300) is formed with in a part for the upside of described first semiconductor layer (1,101);
Described gate electrode (13,113) has been imbedded at least partially at described recess (200,300).
5. the semiconductor device according to any one of Claims 1-4, is characterized in that,
Comprise connecting electrode (50,150), this connecting electrode (50,150) described drain electrode pad (31 is formed in, 131) can welding region downside and at least with described gate electrode extension (14,114,115,116) relative region, this connecting electrode (50,150) described dielectric film (30 is run through, 130) what connect described drain electrode pad (31,131) can welding region and described semiconductor layer (1,2,101,102).
6. semiconductor device as claimed in claim 5, is characterized in that,
Comprise territory, element separation area (60,160), this territory, element separation area (60,160) described gate electrode extension (14,114,115 is formed in, 116) and with this gate electrode extension (14,114,115,116) adjacent described source electrode (11,111) the described semiconductor layer (1 between, 2,101,102) region.
7. the semiconductor device according to any one of Claims 1-4, is characterized in that,
Described gate electrode extension (14,114,115,116) is to surround can the mode of welding region being formed on described semiconductor layer (1,2,101,102) of described drain electrode pad (31,131).
8. the semiconductor device according to any one of Claims 1-4, is characterized in that,
Described source electrode (11,111) has spaced interval and the multiple comb shape source electrode portions (11a ~ 11d, 111a ~ 111d) be arranged substantially in parallel,
Described drain electrode (12,112) has multiple comb shape drain electrode portion (12a, 12b, 12c, 112a, 112b, 112c), multiple described comb shape drain electrode portion (12a, 12b, 12c, 112a, 112b, 112c) and described source electrode (11,111) the spaced compartment of terrain of multiple comb shape source electrode portion (11a ~ 11d, 111a ~ 111d) is alternately arranged configuration.
9. the semiconductor device according to any one of Claims 1-4, is characterized in that,
Described switch element (S1, S2) for multiple,
The described drain electrode (12) of multiple described switch element (S1, S2) connects via same described drain electrode pad (31).
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