CN103367429A - Secondary-growth one-dimensional electron gas GaN-based HEMT (High Electron Mobility Transistor) device and preparation method - Google Patents
Secondary-growth one-dimensional electron gas GaN-based HEMT (High Electron Mobility Transistor) device and preparation method Download PDFInfo
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Abstract
The invention discloses a secondary-growth one-dimensional electron gas GaN-based HEMT (High Electron Mobility Transistor) device and a preparation method, which mainly solve the problems that the high temperature and high pressure characteristic, the frequency characteristic and the power characteristic of an existing one-dimensional electron gas device are poorer. The secondary-growth one-dimensional electron gas GaN-based HEMT device comprises a substrate, a buffer layer, a barrier layer, a passivation layer and a protection layer from bottom to top, wherein two ends of the barrier layer are respectively provided with a source electrode and a drain electrode, the passivation layer is positioned on the barrier layer between the source electrode and the drain electrode, the passivation layer is provided with a grid groove, the grid groove is internally provided with a grid electrode, the buffer layer adopts GaN, the barrier layer adopts AlGaN, the buffer layer is etched with a plurality of quantum wire grooves and quantum wire convex plates, the quantum wire grooves and the quantum wire convex plates are in periodical arrangement, the width of the quantum wire grooves and the quantum wire convex plates is in a nanometer level, and one-dimensional electron gas is formed in a heterogenous junction which is right under the quantum wire grooves and the quantum wire convex plates. Compared with a Si-based and GaAs-based one-dimensional electron gas device, the secondary-growth one-dimensional electron gas GaN-based HEMT device has the advantages of good high temperature and high pressure characteristic, good frequency characteristic and good power characteristic, and the one-dimensional electron gas device in super high speed and low power consumption can be manufactured.
Description
Technical field
The invention belongs to microelectronics technology, relate to semiconductor device, particularly based on a dimensional electron gas HEMT device of GaN semi-conducting material heterojunction structure, can be used as the basic device of microwave, millimeter wave communication system and radar system.
Background technology
The III-V group iii v compound semiconductor material is the third generation semi-conducting material that develops rapidly during the last ten years, such as semi-conducting materials such as GaN are basic, GaAs is basic, InP is basic, their energy gap is very large, and can form alloy semiconductor with InN, AlN etc., makes its energy gap adjustable.People utilize these III-V group iii v compound semiconductor materials to form various heterojunction structures usually, because there is larger difference in the energy gap of the III-V group iii v compound semiconductor material of heterojunction boundary both sides, produced a quantum well near making heterojunction boundary.People can produce the two-dimensional electron gas of high concentration by material being mixed or utilizing the characteristics such as polarity effect of material in quantum well.This two-dimensional electron gas is bound in the quantum well, has realized charge carrier and ionized impurity separating spatially greatly reducing the scattering between charge carrier and the ionization alms giver, thereby greatly having improved electron mobility.If the two-dimensional electron gas that is parallel to semiconductor surface (x-y plane) is further compressed in the y direction, make it be closed in the long L that is
x, wide is L
yFilament in, work as L
yBig or small same L
zThe same, when all similar with electron wavelength, claim that then this filament is quantum wire.The width of quantum wire is nanometer scale.If L
yAnd L
zEnough little, then quantized energy level spacing is larger, only may have a few quantum state in filament.At this moment the motion of electronics is only along the x direction of filament, its energy only by the x direction wave number k
xDecide, the electron system in this quantum wire is a dimensional electron gas.
One dimensional electron gas has some special transport properties.At first, because the quantization of a dimensional electron gas energy is remarkable, then number of electrons is more, and gross energy is just higher, thus speed v
xAlso just higher.In other words, electron concentration N is higher, the speed v of electronics
xJust larger.Mobility [mu] also will increase along with increasing of electron concentration simultaneously.The mobility of expection electronics can be increased to 10
7Cm
2/ vs; Secondly, because a dimensional electron gas is difficult for changing the direction of motion, even have elastic scattering, only have back scattering, probability is also minimum, thereby energy is high also can not the transmitting optics wave sound and transit to lower state again, and then the inelastic scattering probability is also very little.So a dimensional electron gas suffers the probability of various scatterings very little.Just because of this, speed v under high electric field
xAlso unsaturated, in other words, also have very high speed at next dimensional electron gas of high electric field; At last, because a dimensional electron gas only has one degree of freedom, so do not produce the Hall effect.
1987, Holland scientist Bart J.Van Wees and Henk Van Houten have at first reported and have utilized the GaAs/AlGaAs High Electron Mobility Transistor forming the accurate one dimension electron gas channel that forms under the split metal grid structural condition, and observe quantum conductance phenomenon under the accurate One-dimensional Quantum line minus gate voltage, referring to " Quantized conductance of point contacts in a two-dimensional electron gas ", Bart J.Van Wees, Physical Review Letters, Volume60, Number9, February1988.
1987, the people such as Toshiro Hiramoto reported that the method for utilizing focused ion to inject prepares one dimension GaAs quantum wire.At first injecting the formation width at the enterprising line focusing Si ion beam of semi-insulated GaAs substrate is the conductive layer of 20 μ m, then carrying out radius is the focusing Si Implantation formation high resistance area of 0.1 μ m, make conductive layer form a very narrow conducting channel, thereby obtain quantum wire.Referring to " One-dimensional GaAs wires fabricated by focused ion beam implantation ", Toshiro Hiramoto, Applied Physics Letters, Volume51, Number 20, November1987.
1993, the people such as K.Eberl and P.Grambow utilized molecular beam epitaxy diauxic growth technology to prepare the quantum wire structure at the AlGaAs of photoetching moulding resilient coating.During molecular beam epitaxial growth, the Ga atom has different diffusion velocities at the not coplanar of etching table top.The diffusion velocity of Ga atom on side wall surface is very high, be easy to move on the top layer, thereby GaAs is very slow in the speed of growth of sidewall, and the GaAs layer of growth is very thin.Thin GaAs layer has produced quantum wire effect for the thicker GaAs layer region of table top provides the restriction of extra transverse movement dimension on the sidewall.Referring to " Quantum wires prepared by molecular beam epitaxy regrowth on patterned AlGaAs buffer layers ", K.Eberl, Applied Physics Letters, Volume63, Number8, August1993.
Nineteen ninety-five, the people such as Shi Yi and Zheng Youdou has delivered the method that a kind of SiGe/Si of utilization heterostructure prepares silicon quantum wire, it is characterized in that the heterofilm at silicon single crystal growth Si/SiGe/Si, adopt photoetching and reactive ion etching technology to form groove, adopt and select chemical corrosion removal SiGe layer and form the silicon line, by the low thermal oxidation process silicon line is carried out refinement and smoothly reaches final desirable size, obtain simultaneously high-quality Si/SiO
2Heterogeneous interface.Firm referring to executing, Zheng Youdou etc. " a kind of method for preparing silicon quantum wire with the SiGe/Si heterostructure ", China, 1146639,1997-04-02.
1996, the people such as M.L.Osowski delivered and have utilized constituency metal-organic chemical vapor deposition equipment technology to prepare InGaAs – GaAs quantum wire array array structure.The constituency epitaxy technology is mainly derived from the advantage that etching is compared with the diauxic growth technology can adjust the position that the semiconductor growing parameter obtains the high-quality buried regions on the window area.This is so that nanostructure can obtain by single step growth, and the crystal property of growth is so that we can control horizontal crystalline size.Referring to " Lateral inhomogeneity in InGaAs – GaAs quantum wire arrays by selective-area metalorganic chemical vapor deposition ", M.L.Osowski, Applied Physics Letters, Volume68, Number8, February1996.
The process of present preparation quantum wire mainly contains following several, referring to " molecular beam epitaxy self-organization grown quantum line structure material preparation method " China such as Yan Fawang, Zhang Wenjun, and 1312583,2001-09-12:
⑴ utilize magnetic field that charge carrier is carried out another dimension restriction take two-dimensional material as the basis;
⑵ splitting bar technology adds back bias voltage by gate electrode and exhausts the charge carrier realization;
⑶ carry out cleavage to two-dimensional material take two-dimensional material as the basis when growth, then carry out secondary epitaxy at section and form " T-shaped " quantum wire structure;
⑷ utilize the electron beam lithography dry etching before epitaxial growth, the substrate surface " preprocessing " that grow is gone out certain shape;
⑸ on the substrate of little drift angle the self-organizing method growth;
⑹ utilize the characteristics of molecular beam epitaxy technique and the out-of-flatness of high index substrate own, and extension of self-organizing prepares quantum line structure material in molecular beam epitaxial device.
In sum, outer research and the preparation to a dimensional electron gas of Present Domestic all is based on first generation semiconductor Si or second generation semiconductor GaAs material.Because himself material property of Si and GaAs semiconductor is relatively poor, a dimensional electron gas characteristic will be well below ideal situation, and main manifestations is as follows:
One. because the energy gap of Si and GaAs semi-conducting material is less, thereby intrinsic carrier concentration is higher and breakdown electric field is less, so that the HTHP characteristic of the Si of preparation base and GaAs base device is relatively poor, Radiation hardness is very weak;
Two. because the electrons transport property of Si and GaAs semi-conducting material is relatively poor, so that the Si of preparation base and GaAs base device frequency characteristic are relatively poor;
Three. because Si and GaAs semi-conducting material its polarization characteristic when forming heterojunction is relatively poor, electron concentration is very restricted, so that the Si of preparation base and GaAs base device power characteristic are also relatively poor.
Summary of the invention
The object of the invention is the deficiency for above-mentioned prior art, proposes a kind of dimensional electron gas GaN HEMT and preparation method of diauxic growth, to improve HTHP characteristic, frequency characteristic and the power characteristic of a dimensional electron gas device.
Technical scheme of the present invention is achieved in that
One, know-why
Compare the characteristics that first generation semi-conducting material Si and second generation semi-conducting material GaAs have greater advantages according to third generation semi-conducting material GaN, the present invention utilizes the AlGaN/GaN heterojunction to prepare a dimensional electron gas, to obtain high electron mobility and high electron concentration, make device be operated in higher frequency and power bracket, the dimensional electron gas device for the development new construction provides necessary means simultaneously.When resilient coating adopts the GaN semi-conducting material, when barrier layer adopts the AlGaN semi-conducting material, because GaN has different energy gaps with AlGaN, can form at the interface the AlGaN/GaN heterojunction structure, in the AlGaN/GaN of routine heterojunction, have the two-dimensional electron gas conducting channel of high concentration.Behind extension GaN resilient coating on the substrate, first at the GaN resilient coating quantum wire groove that to etch some width spaced apart from each other be nanometer scale, obtaining some width is the quantum wire boss of nanometer scale, and then growth AlGaN barrier layer, this process that material is carried out putting back to behind etching or other treatment steps growth room's continued growth again is called diauxic growth.During diauxic growth AlGaN barrier layer, because the width of quantum wire boss is very little, be nanometer scale, then the GaN layer thickness on the quantum wire boss sidewall is nanometer scale, be not enough to form resilient coating, thereby in quantum wire boss sidewall heterojunction, can not produce two-dimensional electron gas, and laterally cut off the two-dimensional electron gas conducting channel in the heterojunction under quantum wire boss and the quantum wire groove, form a dimensional electron gas.
Two, technical scheme
1. a dimensional electron gas GaN HEMT structure
According to above-mentioned principle, a dimensional electron gas GaN HEMT of the present invention, its structure comprises from bottom to top: substrate 1, resilient coating 2, barrier layer 5, passivation layer 9 and protective layer 10; Two ends on the barrier layer 5 are respectively source electrode 7 and drain electrode 8, and passivation layer 9 has the grid groove on this passivation layer 9 on source electrode 7 and the barrier layer 5 between 8 of draining, be provided with grid 6 in the grid groove, it is characterized in that:
Described resilient coating 2 adopts the GaN semi-conducting material, the quantum wire groove 3 that to be etched with some evenly distributed width on this resilient coating 2 be nanometer scale, obtaining some width is the quantum wire boss 4 of nanometer scale, and quantum wire groove 3 and quantum wire boss 4 periodic arrangement form a dimensional electron gas in the heterojunction under quantum wire groove 3 and quantum wire boss 4;
Described barrier layer 5 adopts the AlGaN semi-conducting material.
An above-mentioned dimensional electron gas GaN HEMT is characterized in that the width of quantum wire groove 3 is 10nm～100nm, and the width of quantum wire boss 4 is 10nm～100nm.
2. the method for preparing a dimensional electron gas GaN HEMT
According to above-mentioned principle, the preparation method of a dimensional electron gas GaN HEMT of the present invention may further comprise the steps:
(1) epitaxial thickness is the GaN semi-conducting material of 1～5 μ m on substrate, as resilient coating;
(2) be coated with electric lithography glue at resilient coating, adopt electron beam lithography to go out needed quantum wire figure, then at the resilient coating quantum wire groove that to etch some width spaced apart from each other be nanometer scale, obtaining some width is the quantum wire boss of nanometer scale, wherein the width of quantum wire groove is 10nm～100nm, the width of quantum wire boss is 10nm～100nm, and quantum wire groove and quantum wire boss are periodic arrangement;
(3) regrowth thickness is the AlGaN semi-conducting material of 10～50nm on the resilient coating after the etching, and as barrier layer, wherein the Al component of AlGaN material is 15%～30%;
(4) on barrier layer, make mask for the first time, carry out source electrode and drain electrode photoetching, and at the two ends of barrier layer depositing metal, make respectively source electrode and drain electrode;
(5) make mask for the second time on barrier layer, carry out table top photoetching and mesa etch, the two-dimensional electron gas conducting channel is carved fully broken to realize the isolation to device, wherein the mesa etch degree of depth is 100nm～300nm, and the table top spacing is 3～9 μ m;
(6) on the top of source electrode and drain electrode and the passivation layer that is 0.05～0.7 μ m of other the regional deposition thickness on the barrier layer;
(7) make mask at passivation layer, etching grid groove, and in the grid groove depositing metal, make grid;
(8) be the protective layer of 0.1～2.0 μ m at the top of grid and passivation layer deposition thickness;
(9) at passivation layer and protective layer interconnect perforate photoetching and etching and evaporation interconnecting metal.
Device of the present invention and an existing dimensional electron gas device relatively have the following advantages:
1. HTHP characteristic, radiation-resisting performance and the frequency characteristic of a dimensional electron gas device have further been improved.
The present invention adopts the GaN semi-conducting material, because third generation semi-conducting material GaN compares first generation semi-conducting material Si and second generation semi-conducting material GaAs has larger energy gap, thereby intrinsic carrier concentration is lower and breakdown electric field is larger, so that the HTHP characteristic of a dimensional electron gas GaN HEMT of preparation is better, Radiation hardness is very strong.Simultaneously because the GaN material has excellent electrons transport property, so that a dimensional electron gas GaN HEMT of preparation can work in high-frequency range.
2. further improved the power characteristic of a dimensional electron gas device.
Resilient coating of the present invention adopts the GaN semi-conducting material, barrier layer adopts the AlGaN semi-conducting material, GaN has different energy gaps with AlGaN, the AlGaN/GaN heterojunction structure can formed at the interface, because the piezoelectric polarization that the GaN material is extremely strong and the existence of spontaneous polarization electric field, even in the situation without any doping, also can form at heterojunction boundary the two-dimensional electron gas of high concentration, and then obtain than a dimensional electron gas concentration higher in the second generation compound semiconductor heterojunction device, so that a dimensional electron gas GaN HEMT of preparation has preferably power characteristic.
3. further improved the uniformity of a dimensional electron gas.
The present invention adopts the diauxic growth method, first resilient coating is carried out the etching barrier layer of then growing, so that the size of quantum wire, shape and density are controlled, thereby a dimensional electron gas of preparation has preferably uniformity.
Further specify technology contents of the present invention and effect below in conjunction with drawings and Examples.
Description of drawings
Fig. 1 is the structural representation of device of the present invention;
Fig. 2 is the structure elevation cross-sectional view of device of the present invention;
Fig. 3 is the structure side pseudosection of device of the present invention;
Fig. 4 is the fabrication processing figure of device of the present invention.
Embodiment
With reference to Fig. 1, Fig. 2 and Fig. 3, a dimensional electron gas GaN HEMT of the present invention, its structure comprises substrate 1, resilient coating 2, barrier layer 5, passivation layer 9 and protective layer 10 from bottom to top; Two ends on the barrier layer 5 are respectively source electrode 7 and drain electrode 8, and passivation layer 9 has the grid groove on this passivation layer 9 on source electrode 7 and the barrier layer 5 between 8 of draining, be provided with grid 6 in the grid groove; Resilient coating 2 adopts the GaN semi-conducting material, the quantum wire groove 3 that to be etched with some evenly distributed width on this resilient coating 2 be nanometer scale, obtaining some width is the quantum wire boss 4 of nanometer scale, can not produce two-dimensional electron gas in the quantum wire boss 4 sidewall heterojunction, laterally the Two-dimensional electron gas channel in the heterojunction under partition quantum wire groove 3 and the quantum wire boss 4 forms a dimensional electron gas; Barrier layer 5 adopts the AlGaN semi-conducting material.The width of quantum wire groove 3 is 10nm～100nm, and the width of quantum wire boss 4 is 10nm～100nm, and quantum wire groove 3 is periodic arrangement with quantum wire boss 4.
Embodiments of the invention have provided three kinds of device architectures, wherein the device architecture of embodiment 1 is: substrate 1 is sapphire, resilient coating 2 is GaN, barrier layer 5 is AlGaN, and passivation layer 9 is SiN, and protective layer 10 is SiN, quantum wire groove 3 degree of depth are 20nm, width is 10nm, and quantum wire boss 4 width are 10nm, and quantum wire groove 3 is periodic arrangement with quantum wire boss 4; The device architecture of embodiment 2 is: substrate 1 is carborundum, and resilient coating 2 is GaN, and barrier layer 5 is AlGaN, and passivation layer 9 is SiN, and protective layer 10 is SiO
2, quantum wire groove 3 degree of depth are 40nm, and width is 50nm, and quantum wire boss 4 width are 50nm, and quantum wire groove 3 is periodic arrangement with quantum wire boss 4; The device architecture of embodiment 3 is: substrate 1 is silicon, and resilient coating 2 is GaN, and barrier layer 5 is AlGaN, and passivation layer 9 is SiO
2, protective layer 10 is SiN, and quantum wire groove 3 degree of depth are 70nm, and width is 100nm, and quantum wire boss 4 width are 100nm, and quantum wire groove 3 is periodic arrangement with quantum wire boss 4.
With reference to Fig. 4, the present invention makes the method for a dimensional electron gas GaN HEMT, provides following six kinds of embodiment:
Embodiment 1; making substrate 1 is sapphire; resilient coating 2 is GaN; barrier layer 5 is AlGaN, and passivation layer 9 is SiN, and protective layer 10 is SiN; quantum wire groove 3 degree of depth are 20nm; width is 10nm, and quantum wire boss 4 width are 10nm, and quantum wire groove 3 is a dimensional electron gas GaN based hemts of periodic arrangement with quantum wire boss 4.
Step 1, adopting metal organic chemical vapor deposition technology MOCVD epitaxial thickness on Sapphire Substrate 1 is the GaN semi-conducting material of 1 μ m, as resilient coating 2; The process conditions of extension GaN resilient coating 2 are: temperature is 1020 ℃, and pressure is 200Torr, and hydrogen flowing quantity is 4600sccm, and ammonia flow is 4600sccm, and the gallium source flux is 200 μ mol/min.
Step 2 is coated with electric lithography glue at resilient coating 2, adopts electron beam lithography to go out needed quantum wire figure, then uses reactive ion etching method to adopt Cl
2It is that 20nm, width are the quantum wire groove 3 of 10nm that reacting gas etches some degree of depth spaced apart from each other at resilient coating 2, and obtaining some width is the quantum wire boss 4 of 10nm, and quantum wire groove 3 is periodic arrangement with quantum wire boss 4.
The process conditions of etching quantum line groove 3 are: reacting gas Cl
2Flow be 3sccm, pressure is 5mT, power is 80W.
Step 3, adopting metal organic chemical vapor deposition technology MOCVD regrowth thickness on resilient coating 2 is the AlGaN semi-conducting material of 10nm, as barrier layer 5, the Al component of this AlGaN material is 15%; The process conditions of growth AlGaN barrier layer 5 are: temperature is 1050 ℃, and pressure is 200Torr, and hydrogen flowing quantity is 4600sccm, and ammonia flow is 4600sccm, and the gallium source flux is 28 μ mol/min, and the aluminium source flux is 5 μ mol/min.
Step 4 is made for the first time mask on barrier layer 5, carrying out source electrode and drain electrode photoetching, and use electron beam evaporation technique at its two ends depositing metal, again at N
2Carry out rapid thermal annealing in the atmosphere, make respectively source electrode 7 and drain electrode 8, wherein the metal of institute's deposit is the Ti/Al/Ni/Au metallic combination, and the thickness of Ti is 0.01 μ m, and the thickness of Al is 0.05 μ m, and the thickness of Ni is 0.03 μ m, and the thickness of Au is 0.02 μ m.
The process conditions of depositing metal are: vacuum degree is less than 2.0 * 10
-6Torr, power are 200W, evaporation rate less than
The process conditions of rapid thermal annealing are: temperature is 870 ℃, and the time is 30s.
Step 5 is made for the second time mask on barrier layer 5, carrying out the table top photoetching, and adopt reactive ion etching method to carry out mesa etch, and etching depth is 100nm, and the table top spacing is 3 μ m.
The process conditions of etching table top are: reacting gas is Cl
2, Cl
2Flow be 15sccm, pressure is 10mT, power is 100W.
Step 6 is used plasma enhanced CVD on the top of source electrode 7 and drain electrode 8 and other the regional deposition thickness on the barrier layer 5 is the SiN passivation layer 9 of 50nm.
The process conditions of deposit passivation layer 9 are: gas 2%SiH
4/ N
2Flow be 200sccm, gas NH
3Flow be 2sccm, gas N
2Flow be 0sccm, the flow of gas He is 200sccm, pressure is 600mTorr, temperature is 250 ℃, power is 22W.
Step 7, make mask at passivation layer 9, carry out the photoetching of grid groove, and adopt reactive ion etching method to etch the grid groove at passivation layer 9, and then adopt electron beam evaporation depositing metal in the grid groove, make grid 6, wherein the metal of institute's deposit adopts the Ni/Au/Ni metallic combination, and the thickness of ground floor Ni is 0.01 μ m, and the thickness of Au is 0.08 μ m, and the thickness of second layer Ni is 0.01 μ m.
The process conditions of etching grid groove are: reacting gas is CF
4, CF
4Flow be 20sccm, pressure is 5mT, power is 50W; The process conditions of depositing metal are: vacuum degree is less than 2.0 * 10
-6Torr, power are 500W, evaporation rate less than
Step 8 uses plasma enhanced CVD at the top deposition thickness of grid 6 and the passivation layer 9 SiN protective layer 10 as 100nm.
The process conditions of deposit protective layer 10 are: gas 2%SiH
4/ N
2Flow be 200sccm, gas NH
3Flow be 2sccm, gas N
2Flow be 0sccm, the flow of gas He is 200sccm, pressure is 600mTorr, temperature is 250 ℃, power is 22W.
Step 9 is at passivation layer 9 and protective layer 10 interconnect perforate photoetching and etching and evaporation interconnecting metal.
At first, in the perforate photoetching that interconnects of passivation layer 9 and protective layer 10;
Secondly, adopt the reactive ion etching method perforate etching that interconnects, the process conditions of interconnection perforate etching are: reacting gas is CF
4And O
2, CF
4Flow be 45sccm, O
2Flow be 5sccm, pressure is 10mT, power is 100W;
Then, adopt electron beam evaporation technique to carry out the interconnecting metal evaporation, the metal that evaporates adopts the Ti/Au metallic combination, and wherein the thickness of Ti is 0.02 μ m, and the thickness of Au is 0.1 μ m; The process conditions of interconnecting metal evaporation are: vacuum degree is less than 2.0 * 10
-6Torr, power are 200W, evaporation rate less than
Embodiment 2, and making substrate 1 is carborundum, and resilient coating 2 is GaN, and barrier layer 5 is AlGaN, and passivation layer 9 is SiN, and protective layer 10 is SiO
2, quantum wire groove 3 degree of depth are 40nm, and width is 50nm, and quantum wire boss 4 width are 50nm, and quantum wire groove 3 is a dimensional electron gas GaN based hemts of periodic arrangement with quantum wire boss 4.
Step 1, epitaxial thickness is the GaN resilient coating 2 of 3 μ m on silicon carbide substrates 1.
Using metal organic chemical vapor deposition MOCVD equipment is 1020 ℃ in temperature, pressure is 200Torr, hydrogen flowing quantity is 5000sccm, ammonia flow is 5000sccm, the gallium source flux is under the process conditions of 220 μ mol/min, and epitaxial thickness is the GaN resilient coating 2 of 3 μ m on silicon carbide substrates 1.
Step 2 makes needed quantum wire figure by lithography at resilient coating 2, and etches some quantum wire grooves 3 spaced apart from each other at resilient coating 2, obtains some quantum wire boss 4.
At first, be coated with electric lithography glue at resilient coating 2, adopt electron beam lithography to go out needed quantum wire figure;
Then, adopting reactive ion etching method is 8mT at pressure, and power is 100W, reacting gas Cl
2Flow be under the process conditions of 10sccm, etching some degree of depth spaced apart from each other at resilient coating 2 is that 40nm, width are the quantum wire groove 3 of 50nm, obtaining some width is the quantum wire boss 4 of 50nm, and quantum wire groove 3 is periodic arrangement with quantum wire boss 4.
Step 3, regrowth thickness is the AlGaN barrier layer 5 of 30nm on GaN resilient coating 2.
Using metal organic chemical vapor deposition MOCVD equipment is 1080 ℃ in temperature, pressure is 200Torr, hydrogen flowing quantity is 5000sccm, ammonia flow is 5000sccm, the gallium source flux is 19 μ mol/min, the aluminium source flux is under the process conditions of 7 μ mol/min, and regrowth thickness is the AlGaN barrier layer 5 of 30nm on GaN resilient coating 2, and the Al component of this AlGaN material is 27%.
Step 4 is made mask for the first time on barrier layer 5, and at the two ends of barrier layer 5 depositing metal, makes respectively source electrode 7 and drain electrode 8.
At first, on barrier layer 5, make mask for the first time, carry out source electrode and drain electrode photoetching;
Secondly, use electron beam evaporation technique in vacuum degree less than 2.0 * 10
-6Torr, power are 500W, evaporation rate less than
Process conditions under, in the two ends of barrier layer 5 deposit Ti/Al/Ni/Au metallic combination, make respectively source electrode 7 and drain electrode 8, wherein the thickness of Ti is 0.022 μ m, the thickness of Al is 0.14 μ m, the thickness of Ni is 0.055 μ m, Au thickness be 0.045 μ m;
Then, be N in atmosphere
2, temperature is 870 ℃, the time is to carry out rapid thermal annealing under the process conditions of 30s.
Step 5 is made mask for the second time on barrier layer 5, carry out table top photoetching and etching.
At first, on barrier layer 5, make mask for the second time, carry out the table top photoetching;
Secondly, adopting reactive ion etching method is 10mT at pressure, and power is 100W, reacting gas Cl
2Flow be to carry out mesa etch under the process conditions of 15sccm, etching depth is 200nm, the table top spacing is 5 μ m.
Step 6 is on the top of source electrode 7 and drain electrode 8 and the SiN passivation layer 9 that other the regional deposition thickness on the barrier layer 5 is 100nm.
Use plasma enhanced CVD to be 600mTorr at pressure, temperature is 250 ℃, and power is 22W, gas 2%SiH
4/ N
2Flow be 200sccm, gas NH
3Flow be 2sccm, gas N
2Flow be 0sccm, the flow of gas He is under the process conditions of 200sccm, on the top of source electrode 7 and drain electrode 8 and the SiN passivation layer 9 that other the regional deposition thickness on the barrier layer 5 is 100nm.
Step 7 is made mask at passivation layer 9, carries out the photoetching of grid groove and etching, and depositing metal is made grid 6 in the grid groove.
At first, make mask at passivation layer 9, carry out the photoetching of grid groove;
Secondly, adopting reactive ion etching method is 5mT at pressure, and power is 50W, reacting gas CF
4Flow be under the process conditions of 20sccm, etch the grid groove at passivation layer 9;
Then, use electron beam evaporation technique in vacuum degree less than 2.0 * 10
-6Torr, power are 500W, evaporation rate less than
Process conditions under, grid 6 is made in deposit Ni/Au/Ni metallic combination in the grid groove, wherein the thickness of ground floor Ni is 0.05 μ m, the thickness of Au is 0.2 μ m, the thickness of second layer Ni is 0.03 μ m.
Step 8 is the SiO of 500nm at the top deposition thickness of grid 6 and passivation layer 9
2Protective layer 10.
Use plasma enhanced CVD to be 1000mTorr at pressure, temperature is 250 ℃, and power is 25W, gas N
2The flow of O is 800sccm, gas SiH
4The process conditions of flow 150sccm under, be the SiO of 500nm at the top deposition thickness of grid 6 and passivation layer 9
2Protective layer 10.
Step 9 is at passivation layer 9 and protective layer 10 interconnect perforate photoetching and etching and evaporation interconnecting metal.
At first, in the perforate photoetching that interconnects of passivation layer 9 and protective layer 10;
Secondly, adopting reactive ion etching method is 10mT at pressure, and power is 100W, reacting gas CF
4Flow be 45sccm, O
2Flow be the perforate etching that interconnects under the process conditions of 5sccm.
Then, adopt electron beam evaporation technique in vacuum degree less than 2.0 * 10
-6Torr, power are 500W, evaporation rate less than
Process conditions under carry out interconnecting metal evaporation, the metal that evaporates adopts the Ti/Au metallic combination, wherein the thickness of Ti is 0.02 μ m, the thickness of Au is 0.1 μ m.
Embodiment 3, and making substrate 1 is silicon, and resilient coating 2 is GaN, and barrier layer 5 is AlGaN, and passivation layer 9 is SiO
2, protective layer 10 is SiN, and quantum wire groove 3 degree of depth are 70nm, and width is 100nm, and quantum wire boss 4 width are 100nm, and quantum wire groove 3 is a dimensional electron gas GaN based hemts of periodic arrangement with quantum wire boss 4.
Steps A, epitaxial thickness is the GaN resilient coating 2 of 5 μ m on silicon substrate 1.
Using metal organic chemical vapor deposition MOCVD equipment epitaxial thickness on silicon substrate 1 is the GaN resilient coating 2 of 5 μ m; The process conditions of extension GaN resilient coating 2 are: temperature is 1060 ℃, and pressure is 200Torr, and hydrogen flowing quantity is 5200sccm, and ammonia flow is 5200sccm, and the gallium source flux is 240 μ mol/min.
Step B makes needed quantum wire figure by lithography at resilient coating 2, and etches some quantum wire grooves 3 spaced apart from each other at resilient coating 2, obtains some quantum wire boss 4.
B1) be coated with electric lithography glue at resilient coating 2, adopt electron beam lithography to go out needed quantum wire figure;
B2) use reactive ion etching method to adopt Cl
2It is that 70nm, width are the quantum wire groove 3 of 100nm that reacting gas etches some degree of depth spaced apart from each other at resilient coating 2, and obtaining some width is the quantum wire boss 4 of 100nm, and quantum wire groove 3 is periodic arrangement with quantum wire boss 4.Wherein the process conditions of etching quantum line groove 3 are: reacting gas Cl
2Flow be 15sccm, pressure is 10mT, power is 200W.
Step C, regrowth thickness is the AlGaN barrier layer 5 of 50nm on GaN resilient coating 2.
Use metal organic chemical vapor deposition MOCVD equipment regrowth thickness on GaN resilient coating 2 to be the AlGaN barrier layer 5 of 50nm, the Al component of this AlGaN material is 30%; The process conditions of growth AlGaN barrier layer 5 are: temperature is 1100 ℃, and pressure is 200Torr, and hydrogen flowing quantity is 5200sccm, and ammonia flow is 5200sccm, and the gallium source flux is 18 μ mol/min, and the aluminium source flux is 8 μ mol/min.
Step D makes mask for the first time on barrier layer 5, and at the two ends of barrier layer 5 depositing metal, makes respectively source electrode 7 and drain electrode 8.
D1) on barrier layer 5, make mask for the first time, carry out source electrode and drain electrode photoetching;
D2) use electron beam evaporation technique in vacuum degree less than 2.0 * 10
-6Torr, power are 500W, evaporation rate less than
Process conditions under, in the two ends of barrier layer 5 deposit Ti/Al/Ni/Au metallic combination, make respectively source electrode 7 and drain electrode 8, wherein the thickness of Ti is 0.05 μ m, the thickness of Al is 0.3 μ m, the thickness of Ni is 0.2 μ m, Au thickness be 0.15 μ m;
D3) be N in atmosphere
2, temperature is 870 ℃, the time is to carry out rapid thermal annealing under the process conditions of 30s.
Step e is made mask for the second time on barrier layer 5, carry out table top photoetching and etching.
E1) on barrier layer 5, make mask for the second time, carry out the table top photoetching;
E2) adopt reactive ion etching method to carry out mesa etch, etching depth is 300nm, and the table top spacing is 9 μ m.The process conditions of etching table top are: reacting gas is Cl
2, Cl
2Flow be 15sccm, pressure is 10mT, power is 100W.
Step F is used plasma enhanced CVD on the top of source electrode 7 and drain electrode 8 and the SiO that other the regional deposition thickness on the barrier layer 5 is 0.7 μ m
2Passivation layer 9.
Use plasma enhanced CVD on the top of source electrode 7 and drain electrode 8 and the SiO that other the regional deposition thickness on the barrier layer 5 is 0.7 μ m
2Passivation layer 9.Deposit SiO
2The process conditions of passivation layer 9 are: gas N
2The flow of O is 800sccm, gas SiH
4Flow be 150sccm, pressure is 1000mTorr, temperature is 250 ℃, power is 25W.
Step G makes mask at passivation layer 9, carries out the photoetching of grid groove and etching, and depositing metal is made grid 6 in the grid groove.
G1) make mask at passivation layer 9, carry out the photoetching of grid groove;
G2) adopting reactive ion etching method is 5mT at pressure, and power is 50W, reacting gas CF
4Flow be under the process conditions of 20sccm, etch the grid groove at passivation layer 9;
G3) use electron beam evaporation technique deposit Ni/Au/Ni metallic combination in the grid groove, make grid 6, wherein the thickness of ground floor Ni is 0.2 μ m, and the thickness of Au is 0.5 μ m, and the thickness of second layer Ni is 0.2 μ m.The process conditions of deposit Ni/Au/Ni metallic combination are: vacuum degree is less than 2.0 * 10
-6Torr, power are 500W, evaporation rate less than
Step H, using plasma enhanced CVD is the SiN protective layer 10 of 2.0 μ m at the top deposition thickness of grid 6 and passivation layer 9.
Using plasma enhanced CVD is the SiN protective layer 10 of 2.0 μ m at the top deposition thickness of grid 6 and passivation layer 9.The process conditions of deposit SiN protective layer 10 are: gas 2%SiH
4/ N
2Flow be 200sccm, gas NH
3Flow be 2sccm, gas N
2Flow be 0sccm, the flow of gas He is 200sccm, pressure is 600mTorr, temperature is 250 ℃, power is 22W.
Step I is at passivation layer 9 and protective layer 10 interconnect perforate photoetching and etching and evaporation interconnecting metal.
I1) the perforate photoetching that on passivation layer 9 and protective layer 10, interconnects first;
I2) adopting reactive ion etching method is 10mT at pressure again, and power is 100W, reacting gas CF
4Flow be 45sccm, O
2Flow be the perforate etching that interconnects under the process conditions of 5sccm.
I3) adopt electron beam evaporation technique in vacuum degree less than 2.0 * 10
-6Torr, power are 700W, evaporation rate less than
Process conditions under carry out interconnecting metal evaporation, the metal that evaporates adopts the Ti/Au metallic combination, wherein the thickness of Ti is 0.02 μ m, the thickness of Au is 0.1 μ m.
Embodiment 4; making substrate 1 is sapphire; resilient coating 2 is GaN; barrier layer 5 is AlGaN, and passivation layer 9 is SiN, and protective layer 10 is SiN; quantum wire groove 3 degree of depth are 20nm; width is 10nm, and quantum wire boss 4 width are 10nm, and quantum wire groove 3 is a dimensional electron gas GaN based hemts of periodic arrangement with quantum wire boss 4.
The 1st step, identical with the step 1 of embodiment 1;
The 2nd step was coated with electric lithography glue at resilient coating 2, adopted electron beam lithography to go out needed quantum wire figure, then used the inductively coupled plasma lithographic method to adopt Cl
2It is that 20nm, width are the quantum wire groove 3 of 10nm that reacting gas etches some degree of depth spaced apart from each other at resilient coating 2, and obtaining some width is the quantum wire boss 4 of 10nm, and quantum wire groove 3 is periodic arrangement with quantum wire boss 4.
The process conditions of etching quantum line groove 3 are: reacting gas Cl
2Flow be 5sccm, pressure is 1Pa, power is 180W.
The 3rd step, identical with the step 3 of embodiment 1;
The 4th step, identical with the step 4 of embodiment 1;
The 5th step, identical with the step 5 of embodiment 1;
The 6th step, identical with the step 6 of embodiment 1;
The 7th step, identical with the step 7 of embodiment 1;
The 8th step, identical with the step 8 of embodiment 1;
The 9th step, identical with the step 9 of embodiment 1.
Embodiment 5, and making substrate 1 is carborundum, and resilient coating 2 is GaN, and barrier layer 5 is AlGaN, and passivation layer 9 is SiN, and protective layer 10 is SiO
2, quantum wire groove 3 degree of depth are 40nm, and width is 50nm, and quantum wire boss 4 width are 50nm, and quantum wire groove 3 is a dimensional electron gas GaN based hemts of periodic arrangement with quantum wire boss 4.
The first step is identical with the step 1 of embodiment 2;
Second step makes needed quantum wire figure by lithography at resilient coating 2, and etches some quantum wire grooves 3 spaced apart from each other at resilient coating 2, obtains some quantum wire boss 4.
At first, be coated with electric lithography glue at resilient coating 2, adopt electron beam lithography to go out needed quantum wire figure;
Then, adopting the inductively coupled plasma lithographic method is 1.5Pa at pressure, and power is 400W, reacting gas Cl
2Flow be under the process conditions of 20sccm, etching some degree of depth spaced apart from each other at resilient coating 2 is that 40nm, width are the quantum wire groove 3 of 50nm, obtaining some width is the quantum wire boss 4 of 50nm, and quantum wire groove 3 is periodic arrangement with quantum wire boss 4.
The 3rd step, identical with the step 3 of embodiment 2;
The 4th step, identical with the step 4 of embodiment 2;
The 5th step, identical with the step 5 of embodiment 2;
The 6th step, identical with the step 6 of embodiment 2;
The 7th step, identical with the step 7 of embodiment 2;
The 8th step, identical with the step 8 of embodiment 2;
The 9th step, identical with the step 9 of embodiment 2.
Embodiment 6, and making substrate 1 is silicon, and resilient coating 2 is GaN, and barrier layer 5 is AlGaN, and passivation layer 9 is SiO
2, protective layer 10 is SiN, and quantum wire groove 3 degree of depth are 70nm, and width is 100nm, and quantum wire boss 4 width are 100nm, and quantum wire groove 3 is a dimensional electron gas GaN based hemts of periodic arrangement with quantum wire boss 4.
The A step, identical with the steps A of embodiment 3;
The B step makes needed quantum wire figure by lithography at resilient coating 2, and etches some quantum wire grooves 3 spaced apart from each other at resilient coating 2, obtains some quantum wire boss 4.
B1) be coated with electric lithography glue at resilient coating 2, adopt electron beam lithography to go out needed quantum wire figure;
B2) use the inductively coupled plasma lithographic method to adopt Cl
2It is that 70nm, width are the quantum wire groove 3 of 100nm that reacting gas etches some degree of depth spaced apart from each other at resilient coating 2, and obtaining some width is the quantum wire boss 4 of 100nm, and quantum wire groove 3 is periodic arrangement with quantum wire boss 4.Wherein the process conditions of etching quantum line groove 3 are: reacting gas Cl
2Flow be 30sccm, pressure is 3Pa, power is 600W.
The C step, identical with the step C of embodiment 3;
The D step, identical with the step D of embodiment 3;
The E step, identical with the step e of embodiment 3;
The F step, identical with the step F of embodiment 3;
The G step, identical with the step G of embodiment 3;
The H step, identical with the step H of embodiment 3;
The I step, identical with the step I of embodiment 3.
In the above-described embodiment, the method for epitaxial buffer layer 2 and growth barrier layer 5 adopts metal organic chemical vapor deposition or molecular beam epitaxy or hydride gas-phase epitaxy; The method of depositing metal adopts electron beam evaporation technique or sputtering technology; The method of etching table top and grid groove adopts reactive ion etching method or inductively coupled plasma lithographic method; Passivation layer 9 and protective layer 10 adopt SiO
2Or SiN or Al
2O
3Or Sc
2O
3Or HfO
2Or TiO
2Or other dielectric materials; The method of deposit passivation layer 9 and protective layer 10 adopts chemical vapor deposition or evaporation or atomic layer deposition or sputter or molecular beam epitaxy.
More than describing only is several instantiation of the present invention, does not consist of any limitation of the invention.Obviously for those skilled in the art; after having understood content of the present invention and principle; all may be in the situation that does not deviate from principle of the present invention, structure; carry out various corrections and change on form and the details, but these are based on correction of the present invention with change still within claim protection range of the present invention.
Claims (10)
1. a dimensional electron gas GaN HEMT of a diauxic growth, its structure comprises substrate (1), resilient coating (2), barrier layer (5), passivation layer (9) and protective layer (10) from bottom to top; Two ends on the barrier layer (3) are respectively source electrode (7) and drain electrode (8), passivation layer (9) be positioned at source electrode (7) and drain (8) between barrier layer (5) on, this passivation layer has the grid groove on (9), is provided with grid (6) in the grid groove, it is characterized in that:
Described resilient coating (2) adopts the GaN semi-conducting material, the quantum wire groove (3) that to be etched with some evenly distributed width on this resilient coating (2) be nanometer scale, obtaining some width is the quantum wire boss (4) of nanometer scale, and quantum wire groove (3) is periodic arrangement with quantum wire boss (4), forms a dimensional electron gas under quantum wire groove (3) and quantum wire boss (4) in the heterojunction;
Described barrier layer (5) adopts the AlGaN semi-conducting material.
2. a dimensional electron gas GaN HEMT according to claim 1 is characterized in that the width of quantum wire groove (3) is 10nm～100nm, and the width of quantum wire boss (4) is 10nm～100nm.
3. the preparation method of a dimensional electron gas GaN HEMT of a diauxic growth may further comprise the steps:
(1) epitaxial thickness is the GaN semi-conducting material of 1～5 μ m on substrate, as resilient coating;
(2) be coated with electric lithography glue at resilient coating, adopt electron beam lithography to go out needed quantum wire figure, then at the resilient coating quantum wire groove that to etch some width spaced apart from each other be nanometer scale, obtaining some width is the quantum wire boss of nanometer scale, wherein the width of quantum wire groove is 10nm～100nm, the width of quantum wire boss is 10nm～100nm, and quantum wire groove and quantum wire boss are periodic arrangement;
(3) regrowth thickness is the AlGaN semi-conducting material of 10～50nm on the resilient coating after the etching, and as barrier layer, wherein the Al component of AlGaN material is 15%～30%;
(4) on barrier layer, make mask for the first time, carry out source electrode and drain electrode photoetching, and at the two ends of barrier layer depositing metal, make respectively source electrode and drain electrode;
(5) make mask for the second time on barrier layer, carry out table top photoetching and mesa etch, the two-dimensional electron gas conducting channel is carved fully broken to realize the isolation to device, wherein the mesa etch degree of depth is 100nm～300nm, and the table top spacing is 3～9 μ m;
(6) on the top of source electrode and drain electrode and the passivation layer that is 0.05～0.7 μ m of other the regional deposition thickness on the barrier layer;
(7) make mask at passivation layer, etching grid groove, and in the grid groove depositing metal, make grid;
(8) be the protective layer of 0.1～2.0 μ m at the top of grid and passivation layer deposition thickness;
(9) at passivation layer and protective layer interconnect perforate photoetching and etching and evaporation interconnecting metal.
4. the preparation method of a dimensional electron gas GaN HEMT according to claim 3 is characterized in that substrate adopts Sapphire Substrate or silicon carbide substrates or silicon substrate material.
5. the preparation method of a dimensional electron gas GaN HEMT according to claim 3, it is characterized in that (2) step is described at the resilient coating quantum wire groove that to etch some width spaced apart from each other be nanometer scale, adopts reactive ion etching method or inductively coupled plasma lithographic method to carry out.
6. the preparation method of a dimensional electron gas GaN HEMT according to claim 5, it is characterized in that adopting reactive ion etching method or inductively coupled plasma lithographic method at the resilient coating quantum wire groove that to etch some width spaced apart from each other be nanometer scale, adopt Cl
2Reacting gas or BCl
3Reacting gas carries out.
7. the preparation method of a dimensional electron gas GaN HEMT according to claim 6 is characterized in that adopting the process conditions of reactive ion etching method etching quantum line groove to be: reacting gas Cl
2Flow be 3～15sccm, pressure is 5～10mT, power is 80～200W.
8. the preparation method of a dimensional electron gas GaN HEMT according to claim 6 is characterized in that adopting the process conditions of inductively coupled plasma lithographic method etching quantum line groove to be: reacting gas Cl
2Flow be 5～30sccm, pressure is 1～3Pa, power is 180～600W.
9. the preparation method of a dimensional electron gas GaN HEMT according to claim 3, it is characterized in that in described (4) step at the metal of barrier layer two ends deposit, adopt the Ti/Al/Ni/Au metallic combination, wherein the thickness of Ti is 0.01～0.05 μ m, the thickness of Al is 0.05～0.3 μ m, the thickness of Ni is 0.03～0.2 μ m, and the thickness of Au is 0.02～0.15 μ m.
10. the preparation method of a dimensional electron gas GaN HEMT according to claim 3, the metal that it is characterized in that deposit in the grid groove in described (7) step, adopt the Ni/Au/Ni metallic combination, wherein the thickness of ground floor Ni is 0.01～0.2 μ m, the thickness of Au is 0.08～0.5 μ m, and the thickness of second layer Ni is 0.01～0.2 μ m.
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| CN109309130A (en) * | 2017-07-26 | 2019-02-05 | 新唐科技股份有限公司 | Heterojunction schottky diode element |
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| CN107180867A (en) * | 2017-06-14 | 2017-09-19 | 中国科学技术大学 | A kind of semiconductor Quantum Device and preparation method thereof |
| CN107180867B (en) * | 2017-06-14 | 2023-08-29 | 中国科学技术大学 | Semiconductor quantum device and preparation method thereof |
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