CN103367404A - Thin film transistor - Google Patents
Thin film transistor Download PDFInfo
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- CN103367404A CN103367404A CN2012100954970A CN201210095497A CN103367404A CN 103367404 A CN103367404 A CN 103367404A CN 2012100954970 A CN2012100954970 A CN 2012100954970A CN 201210095497 A CN201210095497 A CN 201210095497A CN 103367404 A CN103367404 A CN 103367404A
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- Prior art keywords
- film transistor
- layer
- thin
- source electrode
- drain electrode
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Abstract
The invention relates to a thin film transistor which comprises a substrate, an active layer, a grid, a source electrode and a drain electrode, wherein the active layer is arranged on the substrate and comprises a channel layer, a source and a drain, and the source and the drain are located at two opposite sides of the channel layer respectively; the grid is located above or below the channel layer; the grid and the channel layer are provided with a grid insulating layer therebetween; the source electrode and the drain electrode are correspondingly arranged at the source and the drain respectively; and an N-type group III nitride conductive layer whose carrier concentration is higher than that of the active layer is arranged between the source and the source electrode and between the drain and the drain electrode. Contact resistance between the source and the source electrode and between the drain and the drain electrode can be effectively reduced by the N-type group III nitride conductive layer.
Description
Technical field
The present invention relates to a kind of thin-film transistor.
Background technology
At present, thin-film transistor is widely applied among liquid crystal display because have low-voltage, quick, the aperture opening ratio advantages of higher of reaction.Thin-film transistor generally comprises the parts such as grid, drain electrode, source electrode and channel layer, and its voltage by the control grid changes the conductivity of channel layer, makes the state that forms conducting or cut-off between source electrode and the drain electrode.
The common active layer that forms of drain electrode, source electrode and channel layer, this active layer adopts the oxide semiconductor material formations such as indium oxide gallium zinc (IGZO) usually, and its carrier concentration is generally at 1x10
15~ 1x10
18Cm
-3Because the carrier concentration of active layer is low, therefore when forming source electrode and drain electrode, between source electrode and the source electrode and the contact resistance between drain electrode and the drain electrode can be higher, therefore can improve the driving voltage of thin-film transistor, reduce thin-film transistor to the reaction speed of signal.
Summary of the invention
In view of this, being necessary to provide a kind of can reduce between source electrode and the source electrode and the thin-film transistor of the contact resistance between drain electrode and the drain electrode.
A kind of thin-film transistor comprises substrate, active layer, grid, source electrode and drain electrode.Described active layer is arranged on the substrate, source electrode and drain electrode that it comprises channel layer and lays respectively at these relative both sides of channel layer.Described grid is positioned at top or the below of channel layer, is provided with gate insulator between grid and the channel layer.Described source electrode and drain electrode respectively correspondence are arranged in source electrode and the drain electrode.Also be provided with the N-type III group-III nitride conductive layer that carrier concentration is higher than active layer between source electrode and the source electrode and between drain electrode and the drain electrode.
Above-mentioned thin-film transistor is by between source electrode and the source electrode and the N-type III group-III nitride conductive layer that is provided with a high carrier concentration between drain electrode and the drain electrode, can effectively reduce between source electrode and the source electrode and the contact resistance between drain electrode and the drain electrode, the driving voltage of thin-film transistor is reduced, improve the reaction speed to signal.
Description of drawings
Fig. 1 is the thin-film transistor structure schematic diagram in the first embodiment of the invention.
Fig. 2 is the thin-film transistor structure schematic diagram in the second embodiment of the invention.
Fig. 3 is the structural representation after thin-film transistor shown in Figure 2 adds etch stop layer.
The main element symbol description
| Thin- |
100、200 |
| |
110、210 |
| |
120、220 |
| |
130、230 |
| N-type III group-III nitride |
140、240 |
| |
150、250 |
| |
160、260260 |
| |
270 |
| |
121、221 |
| |
122、222 |
| |
123、223 |
| |
131、231 |
Following embodiment further specifies the present invention in connection with above-mentioned accompanying drawing.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in further detail.
See also Fig. 1, a kind of thin-film transistor 100 that first embodiment of the invention provides comprises substrate 110, is arranged on active layer 120, grid 130, N-type III group-III nitride conductive layer 140, source electrode 150 and drain electrode 160 on the described substrate 110.
The making material of described substrate 110 is selected from glass, quartz, silicon, Merlon, polymethyl methacrylate or metal forming.
Described active layer 120 is arranged on the surface of substrate 110, source electrode 122 and drain electrode 123 that it comprises channel layer 121 and lays respectively at the relative both sides of channel layer 121.Described active layer 120 adopts oxide semiconductor material to make.Described oxide semiconductor material comprises indium oxide gallium zinc (IGZO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium oxide zinc (GZO), tin indium oxide (ITO), gallium oxide tin (GTO), aluminium oxide tin (ATO), titanium oxide (TiOx) or tin oxide (ZnO).In the present embodiment, active layer 120 adopts indium oxide gallium zinc (IGZO) material to make.
Described grid 130 is arranged on the top of channel layer 121, is formed with gate insulator 131 between itself and the channel layer 121.Whether thin-film transistor 100 forms conductive channel at channel layer 121 by apply different voltage at grid 130 with control when work, thus conducting or the cut-off of control thin-film transistor 100.In general, for the thin-film transistor 100 of enhancement mode, when not applying voltage on the grid 130, do not form conductive channel on the channel layer 121, thin-film transistor 100 is in cut-off state; When grid 130 applies a certain size voltage, will form owing to the effect of electric field conductive channel in the channel layer 121 to connect source electrode 122 and drain electrode 123, this moment, thin-film transistor 100 was in conducting state.Concerning the thin-film transistor 100 of depletion type, when not applying voltage on the grid 130, be formed with conductive channel on the channel layer 121, thin-film transistor 100 is in conducting state; When grid 130 applies a certain size voltage, the conductive channel on the channel layer 121 will disappear owing to the effect of electric field, and this moment, thin-film transistor 100 was in cut-off state.In the present embodiment, the making material of grid 130 comprises gold, silver, aluminium, copper, chromium, titanium, molybdenum or its alloy.The making material of gate insulator 131 comprises the oxide S iO of silicon
x, the nitride SiN of silicon
xOr the nitrogen oxide SiON of silicon
x, or the insulating material of other high-k, such as Ta
2O
5Or HfO
2
Described N-type III group-III nitride conductive layer 140 covers respectively on the surface of source electrode 122 and drain electrode 123 and the local upper surface that covers gate insulator 131 that extends, and its carrier concentration is higher than the carrier concentration of active layer 120.In the present embodiment, the carrier concentration of N-type III group-III nitride conductive layer 140 is higher than 1x10
18Cm
-3This N-type III group-III nitride conductive layer 140 can be armorphous (amorphous), polymorphic (poly-crystal), monocrystalline type (single crystal).In the present embodiment, N-type III group-III nitride conductive layer 140 is a highly doped N-type III nitride semiconductor layer, and its chemical formula is Al
xIn
yGa
(1-x-y)N, 0＜=x＜=1,0＜=y＜=1 wherein, this N-type III nitride semiconductor layer is doped with silicon, and its doping content is greater than 5x10
17Cm
-3
Described source electrode 150 and drain electrode 160 be respectively on the surface of the corresponding N-type III group-III nitride conductive layer 140 that covers source electrode 122 and drain electrode 123, respectively by N-type III group-III nitride conductive layer 140 and source electrode 122 with drain and 123 be electrically connected.Source electrode 150 is used for being connected with extraneous power supply with drain electrode 160, for thin-film transistor 100 normal operations provide corresponding driving voltage.The making material of source electrode 150 and drain electrode 160 is selected from copper, aluminium, nickel, magnesium, chromium, titanium, molybdenum, tungsten and alloy thereof.
In the thin-film transistor 100 of present embodiment, since between source electrode 122 and the source electrode 150 and drain 123 and drain electrode 160 between have a N-type III group-III nitride conductive layer 140, and N-type III group-III nitride conductive layer 140 has a carrier concentration that is higher than active layer 120, therefore can effectively reduce between source electrode 122 and the source electrode 150 and drain 123 and drain electrode 160 between ohmic contact resistance, the driving voltage of thin-film transistor 100 is reduced, improve the reaction speed to signal.
In addition, active layer 120 in the present embodiment adopts indium oxide gallium zinc (IGZO) material to make, and indium oxide gallium zinc is comparatively responsive on the impact of external environment condition, 140 of N-type III group-III nitride conductive layers of the present invention adopt highly doped N-type III nitride semiconductor layer, its energy rank are high, activity stabilized, to the resistance high (for example hot and humid) of adverse circumstances, therefore N-type III group-III nitride conductive layer 140 is covered on the active layer 120, can effectively stop the impact of external environment condition.
See also Fig. 2, the thin-film transistor 200 of second embodiment of the invention comprises substrate 210, active layer 220, grid 230, N-type III group-III nitride conductive layer 240, source electrode 250 and drain electrode 260.Source electrode 222 and drain electrode 223 that active layer 220 comprises channel layer 221 and lays respectively at the relative both sides of channel layer 221, N-type III group-III nitride conductive layer 240 cover respectively surface and the local upper surface that covers channel layer 221 that extends of source electrode 222 and drain electrode 223.Source electrode 250 and drain electrode 260 cover respectively the surface of N-type III group-III nitride conductive layer 240.Different from the first execution mode is that described grid 230 is the belows that arrange on the substrate 210 and be positioned at channel layer 221.Described thin-film transistor 200 further comprises gate insulator 231, and this gate insulator 231 is arranged between grid 230 and the channel layer 221 and extends to source electrode 222 and the bottom of drain electrode 223.
See also Fig. 3, described thin-film transistor 200 can further include etch stop layer 270, and this etch stop layer 270 is arranged on the relatively upper surface away from gate insulator 231 of channel layer 221.The both sides of this etch stop layer 270 are by N-type III group-III nitride conductive layer 240 local coverings.This etch stop layer 270 adopts insulating material to make, and can be selected from the oxide (SiO of silicon
x), the nitride (SiN of silicon
x), the nitrogen oxide (SiON of silicon
x).In the present embodiment, etch stop layer 270 adopts SiO
2Material is made, thereby it can prevent that extraneous dust or aqueous vapor etc. from entering that the electric conductivity to channel layer 221 impacts in the channel layer 221.
Compared to prior art, thin-film transistor of the present invention is by between source electrode and the source electrode and the N-type III group-III nitride conductive layer that is provided with a high carrier concentration between drain electrode and the drain electrode, can effectively reduce between source electrode and the source electrode and the contact resistance between drain electrode and the drain electrode, the driving voltage of thin-film transistor is reduced, improve the reaction speed to signal.
Be understandable that, for the person of ordinary skill of the art, can make change and the distortion that other various pictures are answered by technical conceive according to the present invention, and all these change the protection range that all should belong to claim of the present invention with distortion.
Claims (10)
1. thin-film transistor, comprise substrate, active layer, grid, source electrode and drain electrode, described active layer is arranged on the substrate, source electrode and drain electrode that it comprises channel layer and lays respectively at these relative both sides of channel layer, described grid is positioned at top or the below of channel layer, be provided with gate insulator between grid and the channel layer, described source electrode and drain electrode respectively correspondence are arranged in source electrode and the drain electrode, it is characterized in that: also be provided with the N-type III group-III nitride conductive layer that carrier concentration is higher than active layer between source electrode and the source electrode and between drain electrode and the drain electrode.
2. thin-film transistor as claimed in claim 1, it is characterized in that: the carrier concentration of described N-type III group-III nitride conductive layer is higher than 1x10
18Cm
-3
3. thin-film transistor as claimed in claim 1, it is characterized in that: described N-type III group-III nitride conductive layer is comprised of N-type III group-III nitride, and chemical formula is Al
xIn
yGa
(1-x-y)N, wherein 0＜=x＜=1,0＜=y＜=1.
4. thin-film transistor as claimed in claim 3, it is characterized in that: described N-type III nitride semiconductor layer is doped with silicon, and its doping content is greater than 5x10
17Cm
-3
5. thin-film transistor as claimed in claim 1 is characterized in that: described active layer adopt IGZO, IZO, AZO, GZO, ITO, GTO, ATO, TiOx and ZnO one of them.
6. thin-film transistor as claimed in claim 1, it is characterized in that: the making material of described grid is selected from gold, silver, aluminium, copper, chromium, titanium, molybdenum or its alloy.
7. thin-film transistor as claimed in claim 1, it is characterized in that: the making material of source electrode and drain electrode is selected from copper, aluminium, nickel, magnesium, chromium, titanium, molybdenum, tungsten and alloy thereof.
8. thin-film transistor as claimed in claim 1, it is characterized in that: described thin-film transistor also comprises an etch stop layer, this etch stop layer is arranged on the surface of channel layer.
9. thin-film transistor as claimed in claim 8 is characterized in that: described etch stop layer is arranged on the relatively upper surface away from gate insulator of channel layer, and the both sides of described etch stop layer are covered by conductive layer is local.
10. thin-film transistor as claimed in claim 8 is characterized in that: described etch stop layer employing SiO
2Material is made, thereby prevents that extraneous dust or aqueous vapor from entering that the electric conductivity to channel layer impacts in the channel layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012100954970A CN103367404A (en) | 2012-04-02 | 2012-04-02 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012100954970A CN103367404A (en) | 2012-04-02 | 2012-04-02 | Thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103367404A true CN103367404A (en) | 2013-10-23 |
Family
ID=49368392
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012100954970A Pending CN103367404A (en) | 2012-04-02 | 2012-04-02 | Thin film transistor |
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| Country | Link |
|---|---|
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023226179A1 (en) * | 2022-05-26 | 2023-11-30 | 长鑫存储技术有限公司 | Transistor and preparation method therefor, and memory |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080237598A1 (en) * | 2007-03-27 | 2008-10-02 | Masaya Nakayama | Thin film field effect transistor and display |
| CN101527318A (en) * | 2008-03-07 | 2009-09-09 | 三星电子株式会社 | Transistor and method of manufacturing the same |
| CN101587924A (en) * | 2008-05-21 | 2009-11-25 | 先进开发光电股份有限公司 | Semiconductor element for emitting radiation and method for reducing operation voltage of same |
-
2012
- 2012-04-02 CN CN2012100954970A patent/CN103367404A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080237598A1 (en) * | 2007-03-27 | 2008-10-02 | Masaya Nakayama | Thin film field effect transistor and display |
| CN101527318A (en) * | 2008-03-07 | 2009-09-09 | 三星电子株式会社 | Transistor and method of manufacturing the same |
| CN101587924A (en) * | 2008-05-21 | 2009-11-25 | 先进开发光电股份有限公司 | Semiconductor element for emitting radiation and method for reducing operation voltage of same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023226179A1 (en) * | 2022-05-26 | 2023-11-30 | 长鑫存储技术有限公司 | Transistor and preparation method therefor, and memory |
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Application publication date: 20131023 |