CN103367141A - Manufacturing method for MOS capacitor and MOS capacitor - Google Patents
Manufacturing method for MOS capacitor and MOS capacitor Download PDFInfo
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- CN103367141A CN103367141A CN2012101017570A CN201210101757A CN103367141A CN 103367141 A CN103367141 A CN 103367141A CN 2012101017570 A CN2012101017570 A CN 2012101017570A CN 201210101757 A CN201210101757 A CN 201210101757A CN 103367141 A CN103367141 A CN 103367141A
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Abstract
The invention provides a manufacturing method for an MOS capacitor and an MOS capacitor. The manufacturing method includes: providing a substrate including a plurality of areas; mixing oxyphilic dopants of different concentrations and/or kinds in the plurality of areas respectively; forming oxide layers on the plurality of areas; and forming metal layers and contact blocks on the oxide layers in order. Through forming the areas with the oxyphilic dopants of different concentrations and/or kinds in the same substrate, a plurality of MOS capacitors with different work functions are formed on the same substrate so that waste of a large quantity of wafers is prevented when a work function test is carried out and thus cost is reduced.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of manufacture method of mos capacitance device and mos capacitance device.
Background technology
Along with constantly dwindling of dimensions of semiconductor devices, the high-dielectric constant metal grid utmost point (High K-value Metal Gate, HKMG) technology has almost become the indispensable technology of the following technique of 45nm.For the HKMG device, work function (Work Function, WF) test is a kind of very important analysis means.In order to test the work function of HKMG device, usually can make first mos capacitance device (MOS Capacitor, MOSCAP) to utilize the mos capacitance device to obtain capacitance-voltage (C-V) curve, then obtain work function by capacitance-voltage curve.
The mos capacitance device is the simple Devices with sandwich structure, and Fig. 1 is the generalized section of existing mos capacitance device.As shown in Figure 1, be formed with dielectric layer 101 in Semiconductor substrate 100, be formed with metal level 102 at dielectric layer 101, be formed with contact block 103 at metal level 102.When carrying out the capacitance-voltage curve test, load Dc bias at the two poles of the earth of mos capacitance device and utilize simultaneously an AC signal to measure.Can calculate flat band voltage (Flat Band Voltage, Vfb) by the capacitance-voltage curve that records, then obtain Vfb-EOT (equivalent oxide thickness) curve, from the Vfb-EOT curve EOT is extrapolated to equal zero and namely can obtain work function.
Yet because the restriction of existing technique, the dielectric layer 101 of the mos capacitance device on each wafer can only have a kind of predetermined thickness, therefore in order to obtain the Vfb-EOT curve, usually needs to make a series of mos capacitance device wafer.And, in the development phase of HKMG device, need to test various metal materials, therefore need to make dielectric layer 101 corresponding to the various thickness of this metal material for every kind of metal material, so that it has different work functions.So just need to make a large amount of mos capacitance device wafers and use for analyzing, therefore can cause the waste of a large amount of wafers.
Therefore, need a kind of manufacture method and mos capacitance device of mos capacitance device, to solve problems of the prior art.
Summary of the invention
Introduced the concept of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
In order to solve problems of the prior art, the present invention proposes a kind of manufacture method of mos capacitance device, comprising: substrate is provided, and described substrate comprises a plurality of zones; The oxytropism dopant of variable concentrations and/or the kind of in a plurality of described zones, mixing respectively; Form oxide skin(coating) in a plurality of described zones; And on described oxide skin(coating), form successively metal level and contact block.
Preferably, described oxytropism dopant comprises phosphorus or arsenic.
Preferably, the technique that adopts of described doping is ion implantation technology.
Preferably, the implantation dosage of described ion implantation technology is greater than zero and less than or equal to 2 * 10
15/ cm
2
Preferably, the injection length of described ion implantation technology is 10-100 second.
Preferably, the thickness of described oxide skin(coating) is the 10-30 dust.
Preferably, the method that forms described oxide is the rapid thermal oxidation method.
Preferably, the reaction temperature of described rapid thermal oxidation method is 600-1200 degree centigrade.
Preferably, the reaction time of described rapid thermal oxidation method is 5-60 second.
The present invention also provides a kind of mos capacitance device, and described mos capacitance device is to adopt aforesaid manufacture method to form.
Method of the present invention is by forming the zone of the oxytropism dopant with variable concentrations and/or kind in same substrate, can form a plurality of mos capacitance devices with different work functions at same substrate, therefore when carrying out the work function test, can avoid the waste of a large amount of wafers, and then reduce cost.
Description of drawings
Following accompanying drawing of the present invention is used for understanding the present invention at this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Fig. 1 is the generalized section of existing mos capacitance device;
Fig. 2 is the flow chart of making the mos capacitance device according to one embodiment of the present invention; And
Fig. 3 is the generalized section according to the mos capacitance device of one embodiment of the present invention making.
Embodiment
Next, in connection with accompanying drawing the present invention is described more intactly, shown in the drawings of embodiments of the invention.But the present invention can be with multi-form enforcement, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, it is thorough and complete to provide these embodiment to expose, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, for clear, size and the relative size in floor and district may be exaggerated.Same reference numerals represents identical element from start to finish.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or when layer, its can be directly on other element or layer, with it adjacent, connect or be coupled to other element or layer, perhaps can have between two parties element or layer.On the contrary, when element be called as " directly exist ... on ", when " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer, then do not have between two parties element or layer.
A kind of manufacture method of mos capacitance device.Fig. 2 is the flow chart of making the mos capacitance device according to one embodiment of the present invention.
Execution in step 201 provides substrate, and this substrate comprises a plurality of zones.
As example, substrate can be at least a in the following material of mentioning: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), the insulator on silicon, silicon-on-insulator (SOI), the insulator.Substrate comprises a plurality of zones, and described a plurality of zones are respectively applied to form the mos capacitance device, only forms a mos capacitance device on each zone.The size that these are regional and quantity can be carried out self-defined according to the quantity of the effective area of substrate, mos capacitance device to be formed and size etc. by the producer.
Execution in step 202, the oxytropism dopant of variable concentrations and/or the kind of in a plurality of zones, mixing respectively.
The oxytropism dopant of variable concentrations and/or the kind of in above-mentioned each zone, mixing respectively, it is the concentration difference of the oxytropism dopant that mixes in each zone, perhaps the kind of oxytropism dopant is different, and perhaps the concentration of oxytropism dopant is all different with kind.Oxytropism dopant by doping variable concentrations and/or kind in different zones can make zones different on the substrate have different oxyphie characteristics, in order to can have different work functions during such as the follow-up formation oxide skin(coating) that hereinafter will describe.
Can adopt the oxytropism dopant of kinds of processes doping variable concentrations and/or kind in the zones of different of substrate.According to one embodiment of the present invention, the technique that adopts of mixing is ion implantation technology, adopt this kind method can control easily by control implantation dosage and injection length and be convenient to doping content, and also can change easily dopant species by changing the target source.Particularly, when adopting ion implantation technology to mix, oxytropism dopant for doping variable concentrations and/or kind in different zones, can cooperate photoetching process to use together, namely in the time need to mixing to the first area in a plurality of zones, can form the first photoresist layer that only exposes the first area at substrate; Then carry out ion implantation technology; Remove at last the first photoresist layer.When the second area in a plurality of zones is mixed, can form the second photoresist layer that only exposes second area at substrate; Then carry out ion implantation technology; Remove at last the second photoresist layer.The like, until doping is all finished in all zones on the substrate.
Compare with form oxide skin(coating) in unadulterated zone, oxide skin(coating) can have higher growth rate when forming oxide skin(coating) in the zone that is doped with the oxytropism dopant.Oxytropism dopant with this specific character comprises phosphorus or arsenic etc.
Further, the implantation dosage of ion implantation technology is greater than zero and less than or equal to 2 * 10
15/ cm
2, with the injection of avoiding high dose to the substrate surface injury.Consider that from aspects such as time efficiencies preferably, the injection length of ion implantation technology can be 10-100 second.According to the predetermined concentration in the zone of mixing, suitably select in the implantation dosage that can provide in the above and the scope of injection length, technological parameter reasonably to be set satisfying doping content and reach under the prerequisite of predetermined concentration.
Execution in step 203 forms oxide skin(coating) (being the dielectric layer of mos capacitance device) in a plurality of zones.
All form oxide skin(coating) on the zones of different of substrate, because the concentration of the oxytropism dopant that mixes in the zones of different and/or kind are different, therefore, the growth rate of the oxide skin(coating) on the zones of different is different, and then makes it have different work functions.Preferably, the thickness of oxide skin(coating) can be the 10-30 dust, to guarantee the validity of oxide skin(coating) in the mos capacitance device.Oxide skin(coating) can adopt several different methods to grow, and preferably, the method that forms oxide is the rapid thermal oxidation method.By adopting the rapid thermal oxidation method to come grown oxide layer, the oxytropism dopant is larger on the impact of the growth rate of oxide skin(coating), and then is easier to form in different zones the oxide skin(coating) of different-thickness.
Oxide skin(coating) well known to a person skilled in the art oxide skin(coating) or composite oxide layer typically.The exemplary embodiment of oxide skin(coating) includes but not limited to: alumina layer, tantalum oxide layers, titanium oxide layer, zirconia layer, yttrium oxide layer, gadolinium oxide layer, lanthana layer, silicon oxide layer, lanthana aluminium lamination, hafnium oxide layer and the formed composite bed of above-mentioned various material layers.
As example, the reaction temperature of rapid thermal oxidation method is 600-1200 degree centigrade.As example, the reaction time of rapid thermal oxidation method is 5-60 second.
Execution in step 204 forms successively metal level and contacts block on oxide skin(coating).
As example, the material of metal level can comprise the metals such as titanium, zirconium, hafnium, niobium or tantalum, perhaps the nitride of above-mentioned metal or nitrogen oxide etc.As example, the material of contact block layer can be made by the material with less contact resistance, for example nickel or nisiloy material layer.Can adopt well known in the artly for metal level and the formation method that contacts block layer, therefore such as chemical vapour deposition technique, atomic layer deposition method etc. no longer described in detail.
Method of the present invention is by forming the zone of the oxytropism dopant with variable concentrations and/or kind in same substrate, can form a plurality of mos capacitance devices with different work functions at same substrate, therefore when carrying out the work function test, can avoid the waste of a large amount of wafers, and then reduce cost.
In addition, the present invention also provides a kind of mos capacitance device.Fig. 3 is the generalized section according to the mos capacitance device of one embodiment of the present invention making.The mos capacitance device is to adopt said method to form.Particularly, the mos capacitance device comprises substrate 300, has different zones in substrate 300, for example regional A, regional B and regional C.Quantity and the position in zone only are exemplary shown in Fig. 3, therefore should not be construed as limitation of the present invention.Be doped with respectively the oxytropism dopant of variable concentrations at regional A, regional B and regional C.On regional A, regional B and regional C, all be formed with oxide skin(coating) 301, be formed with metal level 302 at oxide skin(coating) 301, be formed with contact block layer 303 at metal level 302.Oxide skin(coating) 301, metal level 302 and the material that contacts block layer 303 can be above-mentioned cited material, certainly can realize the separately material of function for other.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just is used for for example and the purpose of explanation, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (10)
1. the manufacture method of a mos capacitance device is characterized in that, comprising:
Substrate is provided, and described substrate comprises a plurality of zones;
The oxytropism dopant of variable concentrations and/or the kind of in a plurality of described zones, mixing respectively;
Form oxide skin(coating) in a plurality of described zones; And
On described oxide skin(coating), form successively metal level and contact block.
2. manufacture method according to claim 1 is characterized in that, described oxytropism dopant comprises phosphorus or arsenic.
3. manufacture method according to claim 1 is characterized in that, the technique that described doping is adopted is ion implantation technology.
4. manufacture method according to claim 3 is characterized in that, the implantation dosage of described ion implantation technology is greater than zero and less than or equal to 2 * 10
15/ cm
2
5. manufacture method according to claim 3 is characterized in that, the injection length of described ion implantation technology is 10-100 second.
6. manufacture method according to claim 1 is characterized in that, the thickness of described oxide skin(coating) is the 10-30 dust.
7. manufacture method according to claim 1 is characterized in that, the method that forms described oxide is the rapid thermal oxidation method.
8. manufacture method according to claim 7 is characterized in that, the reaction temperature of described rapid thermal oxidation method is 600-1200 degree centigrade.
9. manufacture method according to claim 7 is characterized in that, the reaction time of described rapid thermal oxidation method is 5-60 second.
10. a mos capacitance device is characterized in that, described mos capacitance device is to adopt such as the described manufacture method of any one among the claim 1-9 to form.
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| CN201210101757.0A CN103367141B (en) | 2012-04-09 | 2012-04-09 | Work function method of testing |
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| CN201210101757.0A CN103367141B (en) | 2012-04-09 | 2012-04-09 | Work function method of testing |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108010903A (en) * | 2016-10-28 | 2018-05-08 | 格芯公司 | Reduce the MOS capacitance structure of capacitance variations |
| WO2019116152A1 (en) * | 2017-12-15 | 2019-06-20 | International Business Machines Corporation | Fabrication of logic devices and power devices on the same substrate |
Citations (4)
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| US6091109A (en) * | 1998-05-11 | 2000-07-18 | Nec Corporation | Semiconductor device having different gate oxide thicknesses by implanting halogens in one region and nitrogen in the second region |
| US6555484B1 (en) * | 1997-06-19 | 2003-04-29 | Cypress Semiconductor Corp. | Method for controlling the oxidation of implanted silicon |
| US20050221556A1 (en) * | 2004-04-06 | 2005-10-06 | Toshiro Futatsugi | Method of manufacturing semiconductor device |
| CN102117774A (en) * | 2009-12-30 | 2011-07-06 | 台湾积体电路制造股份有限公司 | Method for fabricating an integrated circuit device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5329024B2 (en) * | 2006-06-27 | 2013-10-30 | 国立大学法人東北大学 | Semiconductor device |
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2012
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6555484B1 (en) * | 1997-06-19 | 2003-04-29 | Cypress Semiconductor Corp. | Method for controlling the oxidation of implanted silicon |
| US6091109A (en) * | 1998-05-11 | 2000-07-18 | Nec Corporation | Semiconductor device having different gate oxide thicknesses by implanting halogens in one region and nitrogen in the second region |
| US20050221556A1 (en) * | 2004-04-06 | 2005-10-06 | Toshiro Futatsugi | Method of manufacturing semiconductor device |
| CN102117774A (en) * | 2009-12-30 | 2011-07-06 | 台湾积体电路制造股份有限公司 | Method for fabricating an integrated circuit device |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108010903A (en) * | 2016-10-28 | 2018-05-08 | 格芯公司 | Reduce the MOS capacitance structure of capacitance variations |
| CN108010903B (en) * | 2016-10-28 | 2022-04-15 | 格芯(美国)集成电路科技有限公司 | MOS capacitor structure for reducing capacitance change |
| WO2019116152A1 (en) * | 2017-12-15 | 2019-06-20 | International Business Machines Corporation | Fabrication of logic devices and power devices on the same substrate |
| US10685886B2 (en) | 2017-12-15 | 2020-06-16 | International Business Machines Corporation | Fabrication of logic devices and power devices on the same substrate |
| CN111433905A (en) * | 2017-12-15 | 2020-07-17 | 国际商业机器公司 | Logic device and power device fabricated on the same substrate |
| US11244869B2 (en) | 2017-12-15 | 2022-02-08 | International Business Machines Corporation | Fabrication of logic devices and power devices on the same substrate |
| CN111433905B (en) * | 2017-12-15 | 2023-12-22 | 国际商业机器公司 | Manufacturing logic devices and power devices on the same substrate |
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| CN103367141B (en) | 2016-06-01 |
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