CN103366809B - Non-volatile memory device, storage system and its programmed method - Google Patents

Non-volatile memory device, storage system and its programmed method Download PDF

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Publication number
CN103366809B
CN103366809B CN201310114199.6A CN201310114199A CN103366809B CN 103366809 B CN103366809 B CN 103366809B CN 201310114199 A CN201310114199 A CN 201310114199A CN 103366809 B CN103366809 B CN 103366809B
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address
selection line
string selection
string
sequence
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CN103366809A (en
Inventor
郭东勋
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G11C16/3495—Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/076—Error or fault detection not based on redundancy by exceeding limits by exceeding a count or rate limit, e.g. word- or bit count limit
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)

Abstract

The invention discloses a kind of non-volatile memory device, storage system and the method programmed to non-volatile memory device, the non-volatile memory device is included in the unit string being upwardly formed perpendicular to the side of substrate and by going here and there selection line unit come select storage unit.The programmed method includes：Detection is by the loss average information of selection memory block；The selecting sequence to the string selection line by selection memory block is determined according to the loss average information；And it is write data into according to determining selecting sequence described by selection memory block.

Description

Non-volatile memory device, storage system and its programmed method
Cross reference to related applications
The South Korea patent application No.10-2012- submitted in Korean Intellectual Property Office this application claims on April 3rd, 2012 The full content of the South Korea patent application is incorporated herein by 0034496 priority by reference herein.
Technical field
The inventive concepts described herein is related to semiconductor storage, is filled more specifically to non-volatile memories It sets, the programmed method of storage system and non-volatile memory device.
Background technology
Semiconductor storage can be volatibility and non-volatile.The semiconductor storage of volatibility can be with High-speed read-write operation is carried out, but its content stored can be lost when power is off.Non-volatile semiconductor storage is Make that its content stored can also be preserved when power is off.Non-volatile semiconductor storage can be used for store no matter Whether be powered the content that must all preserve.
Non-volatile semiconductor storage may include mask ROM (MROM), programming ROM (PROM), erasable programmable ROM (EPROM), electrically erasable ROM (EEPROM) etc..
Flash memory device can represent a kind of Nonvolatile semiconductor memory device.Flash memory device can be widely used as letter Cease household electrical appliances (for example, computer, mobile phone, PDA, digital camera, video camera, recorder, MP3 player, Hand held PC, game machine, Facsimile machine, scanner, printer etc.) sound and image data storage media.
Recently, it has been developed that there is the semiconductor storage of the storage unit stacked in three dimensions to improve half The integrated level of conductor storage device.
Invention content
The exemplary embodiment of present inventive concept provides a kind of method programmed to non-volatile memory device, described non- Volatile storage is included in the unit string being upwardly formed perpendicular to the side of substrate, and the programmed method includes：Detection is selected Select the loss average information of memory block；The string selection line by selection memory block is determined according to the loss average information Selecting sequence；And it is write data into according to determining selecting sequence described by selection memory block.
The exemplary embodiment of present inventive concept additionally provides a kind of storage system, and the storage system includes non-volatile Storage device, the non-volatile memory device include the memory block being connect with a plurality of string selection line.The storage system can be with Including Memory Controller, Memory Controller construction in order to control the non-volatile memory device in programming operation Select at least one in a plurality of string selection line.It can be changed according to the loss average information of the memory block described more The selecting sequence of item string selection line.
The exemplary embodiment of present inventive concept additionally provides a kind of non-volatile memory device, the non-volatile memories Device includes the cell array for having multiple memory blocks, and each memory block is connect with a plurality of string selection line.It is described non-volatile Storage device may include：Page buffer, the page buffer are connect with the bit line of the cell array；Decoder, institute Decoder is stated to connect with the cell array by a plurality of string selection line；And address remapper, described address weight New mappings device be configured to according to loss average information come remap input address with to the decoder offer remap after Address.The described address device that remaps is configured to the input address that remaps in the following way：According to the loss Average information is adjusted to by the selecting sequence of a plurality of string selection line of selection memory block.
Description of the drawings
By following description with reference to the accompanying drawings it will be clear that above-mentioned and additional advantages and features, wherein unless otherwise saying It is bright, otherwise all the same reference numbers in the drawings refer to identical components, and in the accompanying drawings：
Fig. 1 is the block diagram for the storage system for schematically showing one embodiment according to present inventive concept.
Fig. 2 is the block diagram for the non-volatile memory device for schematically showing one embodiment according to present inventive concept.
Fig. 3 is the perspective view for showing a memory block in Fig. 2.
Fig. 4 is the sectional view intercepted along the I-I' lines of the vertical nand unit string shown in Fig. 3.
Fig. 5 is the perspective view according to the vertical non-volatile memory of another embodiment of present inventive concept.
Fig. 6 is the sectional view along the II-II' lines interception in Fig. 5.
Fig. 7 is the selection structure for the non-volatile memory device for schematically showing one embodiment according to present inventive concept Circuit diagram.
Fig. 8 A to Fig. 8 D are the diagrams for the selecting sequence for showing the string selection line according to one embodiment of present inventive concept.
Fig. 9 is the flow chart for schematically showing the programmed method executed in storage system shown in Fig. 1.
Figure 10 A to Figure 10 H are to show to provide write instruction and address related with selected memory block from Memory Controller Method sequence diagram.
Figure 11 is the block diagram for the storage system for schematically showing another embodiment according to present inventive concept.
Figure 12 A and Figure 12 B are to schematically show to be filled according to the non-volatile memories of another embodiment of present inventive concept The block diagram set.
Figure 13 is the flow chart for the programmed method for schematically showing non-volatile memory device shown in Figure 12.
Figure 14 is the address tune for describing the address remapper of non-volatile memory device shown in Figure 12 A and Figure 12 B The table of whole operation.
Figure 15 is the diagram for the effect for showing present inventive concept.
Figure 16 is to show to include the block diagram according to the user equipment of the solid state drive of one embodiment of present inventive concept.
Figure 17 is the block diagram for the storage system for showing another embodiment according to present inventive concept.
Figure 18 is the block diagram for the data storage device for showing another embodiment according to present inventive concept.
Figure 19 is to show to include the block diagram according to the computer system of the flash memory device of one embodiment of present inventive concept.
Specific implementation mode
Each embodiment will be described in detail by referring to the drawings.However, present inventive concept can be come in fact in the form of a variety of different It applies, and should not be construed as limited to illustrated each embodiment.On the contrary, it is in order to which the disclosure is thorough to provide these examples With range that is comprehensive, and conveying to those skilled in the art present inventive concept comprehensively.Thus, one about present inventive concept A little embodiments do not describe known technique, component and technology.Unless otherwise stated, identical in the accompanying drawings and the description Reference numeral always shows identical component, thus will not be repeated again explanation.In the accompanying drawings, each layer can for the sake of clarity be amplified With the size and relative size in region.
Although it should be understood that can different portions be described using term " first ", " second ", " third " etc. herein Part, component, regions, layers, and/or portions, but these components, component, regions, layers, and/or portions should not be by these term institutes Limitation.These terms are only used to distinguish a component, component, region, layer or part and another region, layer or part. Thus, the first component described below, component, region, layer or part can also be referred to as second component, component, region, layer or Part, without departing from the introduction of present inventive concept.
For convenience, herein can with use space relative terms, such as " ... under ", " ... below ", " following ", " ... it is following ", " ... top ", " above " etc., to describe a component as shown in drawings or spy Sign and another（Or it is multiple）The relationship of component or feature.It should be understood that other than orientation shown in attached drawing, these Spatially relative term, which also aims to, includes the different direction of device in use or operation.For example, if the device in attached drawing is overturn, Then be described as be in other component or feature " following " or " under " component will be positioned at " top " of other component or feature.Cause This, exemplary term " ... below " and " ... it is following " may include being located above and being located below two orientation.Device Part can also have other orientation（Rotation is turn 90 degrees or at other orientation）, spatial relative descriptor used herein should be by It is interpreted accordingly.In addition, it is to be understood that when a layer be referred to as two layers " between " when, can be the two layers Between only layer, or there may also be one or more middle layers.
Term used herein will limit structure of the present invention just for the sake of describing the purpose of each specific embodiment Think.As used in this, singulative " one ", "one" and "the" are intended to also include plural form, unless context Other explanations are clearly made.It is to be further understood that when term " include " and or " include " used herein, specify The feature, integer, step, operation, the presence of component and/or component, but presence or additional one or more is not precluded Other features, integer, step, operation, component, component and/or combination thereof.As used in this, term " and/ Or " include the arbitrary of relevant item listed by one or more and all combinations.Moreover, term " exemplary " be intended to indicate that example or Explanation.
It is to be further understood that when a component or layer be referred to as other component or layer " on ", " being connected to " or " coupling Be connected to " other component or layer or therewith " adjacent " when, one component or layer can directly on other component or layer, Can be directly connected to or be coupled to other component or layer either directly it is adjacent thereto or there may also be intermediate member or in Interbed.In contrast, when a component be referred to as directly other component or layer " on ", directly " being connected to " or direct " coupling Be connected to " other component or layer or directly therewith " adjacent " when, intermediate member or middle layer is not present.
Unless otherwise defined, otherwise all terms used herein above（Including technical and scientific term）With with root The identical meanings being generally understood according to present inventive concept those of ordinary skill in the art.It is to be further understood that such as existing Term defined in common dictionary should be interpreted as having with its in the situation and/or this specification of related field it is consistent Meaning, without should be explained according to the meaning of idealization or too formal（Unless being clearly defined herein）.
Fig. 1 is the block diagram for the storage system for schematically showing one embodiment according to present inventive concept.With reference to figure 1, deposit Storage system 100 may include Memory Controller 110 and non-volatile memory device（NVM）120.Storage system 100 can be with base The selecting sequence of the string selection line of non-volatile memory device 120 is adjusted in loss average information.
Memory Controller 110 can control non-volatile memory device in response to the write request from external equipment 120.Memory Controller 110 can be write in response to the write request from host to the offer of non-volatile memory device 120 Enter to instruct CMD and the address AD D' for select storage unit.Memory Controller 110 can be selected by going here and there selection line unit Storage unit is selected to store data in selected memory block.
Memory block may include in the multiple unit strings being upwardly formed perpendicular to the side of substrate.It is included in perpendicular to substrate The memory block for the multiple unit strings being just upwardly formed can be connect with a plurality of string selection line.It can be selected by a plurality of string selection line Select multiple unit strings.When a string selection line in a plurality of string selection line is selected, this selected string selection line is shared Unit string can be selected.Storage unit in selected cell string can be programmed.
Memory Controller 110 can be according to the selecting unit string in selected memory block that puts in order.In addition, storage Device controller 110 can be deposited according to reverse sequence, the zigzag sequence etc. that put in order selected based on loss average information Store up selecting unit string in block.
Memory Controller 110 may include the average manager 10 of loss and address remapper 20.The average pipe of loss Reason device 10 can store, update and/or manage the average letter of loss related with all memory blocks of non-volatile memory device 120 Breath.For example, averagely manager 10 can be by such as flash translation layer (FTL) for loss（FTL）Etc firmware formed.
Address remapper 20 can again be built based on the loss average information provided from the average manager 10 of loss The selecting sequence of the vertical string selection line by selection memory block.For example, the erasing that loss average information may include memory block counts. When the erasing of memory block is counted less than reference value, address remapper 20 can export putting in order according to string selection line And the address AD D selected.When the erasing of memory block, which counts, is more than reference value, address remapper 20 can be exported for changing The address AD D' for becoming the selecting sequence of string selection line and establishing.
Non-volatile memory device 120 can be vertical non-volatile storage device, wherein being formed by unit string raceway groove With substrate transverse.Non-volatile memory device 120 can be storage device, and wherein memory block can be at least two string selection lines Connection.Non-volatile memory device 120 can be formed by the nand flash memory as storage medium.However, present inventive concept is unlimited In this.For example, non-volatile memory device 120 can be by PRAM, MRAM, ReRAM, FRAM or difference as storage medium The combination of type of storage is formed.
As described above, the storage system 100 of present inventive concept can be based on averagely being believed by the loss of selection memory block It ceases to change by the selecting sequence of the storage unit of selection memory block.For example, being counted less than ginseng when by the erasing of selection memory block When examining value, it can select to be selected the storage unit of memory block according to putting in order for string selection line.When by selection memory block Erasing count when being more than reference value, can select to be selected the storage of memory block according to the reversed arrangement sequence of string selection line Unit.In this way it is possible to keep the deterioration of the storage unit of the memory block in non-volatile memory device 120 balanced.? That is, it is possible to extend the service life of non-volatile memory device 120 or improve the reliability of data.
The management of flash memory device can be carried out so that loss average isostatic by storing module unit.However, working as memory block Selecting sequence fix when, store storage unit in the block and can be potentially encountered different voltage stress.It is vertical including being formed to have The NAND flash memories of the unit string of straight structure can be potentially encountered the above problem, and in some cases, which can be very serious.Work as word When line stacks, the storage unit in same layer can share a wordline.Although storage unit and non-selected string selection line Connection, but can be applied in storage unit via the high programming voltage that wordline is supplied.What this may reduce storage unit can By property.Among these storage units of memory block, the above problem can significantly appear with later by selected string select The storage unit of line connection.By changing the selecting sequence of string selection line based on loss average information, can disperse to be applied to Stress in the storage unit of memory block.This aspect will be more fully described in conjunction with Figure 15.
As described herein, the selecting sequence of string selection line can be changed according to loss average information.However, structure of the present invention Think without being limited thereto.For example, the selecting sequence of string selection line can be according to various data and loss average information（For example, erasing It counts）And change.
Fig. 2 is the block diagram for the non-volatile memory device for schematically showing one embodiment according to present inventive concept.Ginseng Fig. 2 is examined, non-volatile memory device 120 may include memory cell array 121, decoder 122, page buffer 123 and control Logic 124 processed.
Memory cell array 121 can pass through line 125（May include wordline or selection line SSL and GSL）With decoder 122 connections.Memory cell array 121 can be connect by bit line BLs with page buffer 123.Memory cell array 121 can be with Including multiple memory block BLK1 to BLKz, each memory block may include multiple NAND cell strings.It can be selected by a plurality of string Line selects multiple NAND cell strings.
In memory cell array 121, each NAND cell string can have the raceway groove formed in the vertical direction, a plurality of Wordline can stack in the vertical direction.The storage device that memory cell array 110 is wherein formed as to above-mentioned string structure can be with It is referred to as vertical non-volatile storage device or three dimensional nonvolatile storage device.Wherein in the horizontal direction or on vertical direction The storage unit for forming the storage device of unit string is used as multilevel-cell.
Decoder 122 can in response to by Memory Controller 110 adjustment after address AD D' by storage unit battle array Any one memory block is selected in the memory block BLK1 to BLKz of row 121.Decoder 120 can be according to the address AD D' after adjustment To activate by the string selection line of selection memory block.It, can be according to by Memory Controller 110 using the address AD D' after adjustment According to the loss average information of memory block（For example, erasing counts）Sequence after adjustment selects string selection line.
Decoder 122 can select a wordline in by the wordline of selection memory block.Decoder 122 can be to being selected The wordline of memory block provides word line voltage.In programming operation, decoder 122 can be respectively by program voltage Vpgm and verification electricity Pressure Vvfy is transferred to selected wordline, and non-selected wordline will be transferred to by voltage Vpass.Decoder 122 can be with Selection signal is provided to select memory block, sub-block etc. to selection line SSL and GSL.
Page buffer 123 can be used as write driver or sense amplifier according to operation mode.In programming operation When, page buffer 123 can provide electric with by the corresponding bit line of programmed data to the bit line of memory cell array 121 Pressure.In read operation, page buffer 123 can read via bit line and be stored in by the data in select storage unit.Page Face buffer 123 can latch read-out data to output this to external equipment.
Control logic 124 can control decoder 122 and page buffer in response to the instruction CMD from external equipment 123.Control logic 124 can control decoder 122 and page buffer 123 with to positioned at the address AD D' by adjusting after and Input data in the storage unit of selection is programmed.
After the non-volatile memory device 120 of present inventive concept can be in response to the adjustment from Memory Controller 110 Address AD D' and in selected memory block select storage unit.Using the address AD D' after adjustment, can be counted in erasing The selecting sequence of switching string selection line when number is more than reference value.It, can balanced or drop by the selecting sequence of switching string selection line The low stress being applied in the storage unit of memory block.
Fig. 3 is the perspective view for showing a memory block in Fig. 2.Fig. 4 is the vertical nand unit shown along line in Fig. 3 The sectional view of the I-I' lines interception of string.With reference to figure 3, memory block BLKi may include having three-dimensional（3D）Or the unit of vertical structure String.Memory block BLKi may include the structure extended along multiple directions x, y and z.Referring now to Fig. 3 and Fig. 4.
Substrate 111 can be provided to form memory block BLKi.For example, substrate 111 can be formed by p traps, note within the p-well Enter group V element（For example, boron）.Alternatively, substrate 111 can be provided in the pocket shape in n traps（pocket）P traps.? Hereinafter, it is assumed that substrate 111 is p traps.However, substrate 111 is not limited to p traps.
Multiple doped regions 311 to 314 extended along the directions x can be set on substrate 111.For example, multiple doped regions 311 to 314 can be formed by the N-shaped conductor different from substrate 111.In the following, it is assumed that first to fourth doped region 311 to 314 be N-shaped.However, first to fourth doped region 311 to 314 is not limited to N-shaped.
It can be along the directions z on the part between the first doped region 311 and the second doped region 312 of substrate 111 The multiple insulating materials 112 extended along the directions y are sequentially set.Insulating materials 112 can be formed as along between the directions z Every separately.In the exemplary embodiment, insulating materials 112 may include the insulating materials of such as silica etc.
It can be along the directions y on the part between the first doped region 311 and the second doped region 312 of substrate 111 More columns 113 are sequentially set, to penetrate the multiple insulating materials 112 along the directions z.For example, column 113 can pass through absolutely Edge material 112 is contacted with substrate 111.Column 113 can be formed simultaneously being mixed with third positioned at the second doped region 312 in substrate 111 On part between miscellaneous area 313 and on the part between third doped region 313 and the 4th doped region 314 of substrate 111.
In the exemplary embodiment, each column 113 can be formed of a variety of materials.For example, the surface of each column 113 Layer 114 may include first kind silicon materials.For example, the superficial layer 114 of each column 113 may include identical as substrate 111 The silicon materials of type.In the following, it is assumed that the superficial layer 114 of each column 113 includes p-type silicon.However, each column 113 Superficial layer 114 is not limited to p-type silicon.
The internal layer 115 of each column 113 can be formed by insulating materials.For example, the internal layer 115 of each column 113 can be with Include the insulating materials of such as silica etc.For example, the internal layer 115 of each column 113 may include air gap.
It can be along insulating materials 112, column 113 and substrate 111 between the first doped region 311 and the second doped region 312 Exposed surface be arranged insulating film 116.In the exemplary embodiment, in the sudden and violent of the last one insulating materials 112 along the directions z Reveal surface（Towards the directions z）The insulating film 116 of upper setting can be removed.
It, can on the exposed surface of insulating film 116 in region between the first doped region 311 and the second doped region 312 The first conductive material 211 to 291 is arranged.For example, can be arranged in substrate along the first conductive material 211 that the directions y extend Between 111 and the adjacent insulating material 112 of the substrate 111.More specifically, the first conductive material 211 extended in y-direction It can be arranged between the insulating film 116 of the lower surface of the adjacent insulating material 112 in substrate 111 and the substrate 111.
The upper table in the specific insulating materials of insulating materials 112 can be arranged in the first conductive material extended along the directions y The insulating film 116 in face and be arranged in the specific insulating materials top insulating materials lower surface insulating film 116 between.Showing In example property embodiment, the first conductive material 211 to 291 may include metal material.In the exemplary embodiment, the first conduction material Material 211 to 291 may include the conductive material of such as polysilicon etc.
Region between the second doped region 312 and third doped region 313 can be arranged and the first doped region 311 and second Identical structure on doped region 312.For example, the region between the second doped region 312 and third doped region 313 can be provided with Multiple insulating materials 112 for extending in y-direction, along the directions y sequence arrangement to penetrate insulating materials 112 along the directions z More columns 113, the insulating film 116 that is arranged on the exposed surface of more columns 113 and multiple insulating materials 112 and along y Multiple first conductive materials 212 to 292 that direction extends.
Region between third doped region 313 and the 4th doped region 314 can be arranged and the first doped region 311 and second Identical structure on doped region 312.For example, the region between third doped region 313 and the 4th doped region 314 can be provided with Multiple insulating materials 112 for extending in y-direction, along the directions y sequence arrangement to penetrate insulating materials 112 along the directions z More columns 113, the insulating film 116 that is arranged on the exposed surface of more columns 113 and multiple insulating materials 112 and along y Multiple first conductive materials 213 to 293 that direction extends.
Drain electrode 320 can be respectively set on column 113.These drain electrodes 320 can be Second Type silicon materials.These drain electrodes 320 can be n-type silicon material.In the following, it is assumed that these drain electrodes 320 include n-type silicon material.However, drain electrode 320 is not limited to wrap Include n-type silicon material.The width of each drain electrode 320 is more wider than the width of corresponding column 113.Each drain electrode 320 is with pad The mode of piece is arranged on the upper surface of corresponding column 113.
With reference to figure 4, unit string may include multiple storage units, these storage units are formed in the column week being connect with bit line It encloses.It is assumed for convenience of description that unit string includes 7 storage units.
Column 113 can be formed between the first doped region 311 and the second doped region 312 multiple exhausted to be penetrated along the directions z Edge material 112.Column 113 can be contacted via insulating materials 112 with substrate 111.Column 113 may include raceway groove film 114 and inside Material 115.
Raceway groove film 114 may include the semi-conducting material with the first conduction type（For example, silicon）.For example, raceway groove film 114 It may include conduction type semi-conducting material identical with substrate 111（For example, silicon）.In the following, it is assumed that raceway groove film 114 includes P-type silicon.However, present inventive concept is without being limited thereto.For example, raceway groove film 114 may include that there is the intrinsic of non-conductive characteristic partly to lead Body.
Internal material 115 may include insulating materials.For example, internal material 115 may include such as silica etc Insulating materials.For example, internal material 115 may include air gap.
Insulating materials 112 and column between the first doped region 311 and the second doped region 312 can be arranged in insulating film 116 On 113 exposed surface.Conductive material（For example, 211 to 291,212 to 292 and 213 to 293）It can be arranged and be mixed adjacent On the exposed surface of insulating film 116 between miscellaneous area 311 and doped region 312.
Conductive material（For example, 211 to 291,212 to 292 and 213 to 293）It can be mixed by being located at insulating materials 112 Wordline notch in miscellaneous area 311 and 312（word line cut）It separates.In the exemplary embodiment, conductive material（For example, 211 to 291,212 to 292 and 213 to 293）It may include conductive metal material.Conductive material may include such as polycrystalline The non-metallic conducting material of silicon etc.
Drain electrode 320 can be formed on column 113.In the exemplary embodiment, drain electrode 320 may include having second to pass The semi-conducting material of conductivity type（For example, silicon）.For example, drain electrode 320 may include n-type semiconductor（For example, silicon）.Below In, it is assumed that drain electrode 320 includes n-type silicon.However, present inventive concept is without being limited thereto.In the exemplary embodiment, drain electrode 320 can be with Extend to the top of the raceway groove film 114 of column 113.
Can the bit line BL extended in the x direction be set in drain electrode 320（Such as 331,332 and 333）.Bit line BL can To be connect with drain electrode 320.It in the exemplary embodiment, can be by contacting plug（It is not shown）Make drain electrode 320 and bit line BL phases It connects.In the exemplary embodiment, bit line BL may include conductive metal material.In the exemplary embodiment, bit line BL can To include the non-metallic conducting material of such as polysilicon etc.
Fig. 5 is the perspective view according to the vertical non-volatile memory of another embodiment of present inventive concept.Fig. 6 is edge The cross-sectional view of the line II-II' interceptions in Fig. 5.
With reference to figure 5 and Fig. 6, the wordline WL extended along the directions y<4>,WL<5>,WL<6>And WL<7>It can be along the side z To being sequentially positioned on substrate 111.It can be along the directions z by wordline WL<4>,WL<5>,WL<6>And WL<7>It is spaced apart.It can Sequentially to arrange the first upper prop UP1 to penetrate wordline WL along the directions y<4>,WL<5>,WL<6>And WL<7>.Herein, Wordline WL<4>,WL<5>,WL<6>And WL<7>It can be referred to as wordline.
The wordline WL extended along the directions y<0>,WL<1>,WL<2>And WL<3>It can be sequentially positioned at along the directions z On substrate 111.It can be along the directions z by wordline WL<0>, WL<1>,WL<2>And WL<3>It is spaced apart.It can be suitable along the directions y Arrange to sequence the first lower prop DP1 to penetrate wordline WL along the directions z<0>,WL<1>,WL<2>And WL<3>.It can be along the directions y Sequentially arrange the second lower prop DP2 to penetrate wordline WL along the directions z<0>, WL<1>,WL<2>And WL<3>.In exemplary reality It applies in example, the first lower prop DP1 and the second lower prop DP2 can be parallelly arranged along the directions z.Herein, wordline WL<0>,WL< 1>, WL<2>And WL<3>It can be referred to as lower wordline.
The wordline WL extended along the directions y<4>,WL<5>,WL<6>And WL<7>It can be sequentially positioned at along the directions z On substrate 111.It can be along the directions z by wordline WL<4>, WL<5>,WL<6>And WL<7>It is spaced apart.It can be suitable along the directions y Arrange to sequence the second upper prop UP2 to penetrate wordline WL along the directions z<4>,WL<5>,WL<6>And WL<7>.
The common source polar curve CSL extended in y-direction can be set on the first lower prop DP1 and the second lower prop DP2.Showing In example property embodiment, common source polar curve CSL can be n-type silicon.In the exemplary embodiment, in common source polar curve CSL by metal Such as in the case that the nonpolarity conductive material of polysilicon etc is formed, in common source polar curve CSL and the first lower prop DP1 And second can be additionally provided in n-type source between lower prop DP2.In the exemplary embodiment, common source polar curve CSL can pass through Contact plug is connect with the first lower prop DP1 and the second lower prop DP2 respectively.
Drain electrode 320 can be respectively set on the first upper prop UP1 and the second upper prop UP2.In the exemplary embodiment, it drains 320 can be n-type silicon.The multiple bit lines BL extended along the directions x<1>To BL<3>It can be sequentially positioned at leakage in y-direction On pole 320.In the exemplary embodiment, bit line BL<1>To BL<3>It can be connect with drain electrode 320 by contacting plug.
Each column in first upper prop UP1 and the second upper prop UP2 may include superficial layer 116 " and internal layer 114 ".First Each column in lower prop DP1 and the second lower prop DP2 may include superficial layer 116 " and internal layer 114 ".First upper prop UP1 and Two upper prop UP2 and the superficial layer 116 " of the first lower prop DP1 and the second lower prop DP2 can respectively include blocking insulating film, charge Storage films and tunnel insulator film.
First upper prop UP1 and the second upper prop UP2 and each internal layer 114 " of the first lower prop DP1 and the second lower prop DP2 can To be p-type silicon.First upper prop UP1 and the second upper prop UP2 and the internal layer 114 " of the first lower prop DP1 and the second lower prop DP2 can be with As main body.
First upper prop UP1 can be connect by the first pipe joint PC1 with the first lower prop DP1.In the exemplary embodiment, The superficial layer 116 " of first upper prop UP1 can be connect by the first pipe joint PC1 with the superficial layer of the first lower prop DP1.First The superficial layer of pipe joint PC1 can be formed by the identical material of superficial layer 116 " with column UP1 and DP1.
In the exemplary embodiment, the internal layer 114 " of the first upper prop UP1 can by the internal layer of the first pipe joint PC1 with The internal layer of first lower prop DP1 connects.The internal layer of first pipe joint PC1 can be by identical as the internal layer 114 " of column UP1 and DP1 Material formed.
That is, the first upper prop UP1 and wordline WL<4>,WL<5>,WL<6>And WL<7>The first top can be formed String, and the first lower prop DP1 and wordline WL<0>,WL<1>,WL<2>And WL<3>The first lower part string can be formed.First top String can be connect by the first pipe joint PC1 with the first bottom series.Drain 320 and bit line BL<1>To BL<3>It can be with One or more ends connection of one top string.One or more ends that common source polar curve CSL can go here and there with the first lower part connect It connects.That is, the first top string and the first lower part string can be formed in bit line BL<1>To BL<3>With common source polar curve CSL it Between multiple strings for connecting.
Equally, the second upper prop UP2 and wordline WL<4>,WL<5>,WL<6>And WL<7>The second top string can be formed, And the second lower prop DP2 and wordline WL<0>,WL<1>,WL<2>And WL<3>The second lower part string can be formed.Second top string can To be connect with the second bottom series by the second pipe joint PC2.Drain 320 and bit line BL<1>To BL<3>Can on second One or more ends connection of portion's string.One or more ends that common source polar curve CSL can go here and there with the second lower part are connect.? That is the second top string and the second lower part string can be formed in bit line BL<1>To BL<3>Connect between common source polar curve CSL The multiple strings connect.
In the exemplary embodiment, the first and second pipelines contact grid（It is not shown）It can be respectively intended in the first pipeline The main body of connector PC1 and the second pipe joint PC2（That is, internal layer 114 "）Upper formation raceway groove.For example, the first and second pipelines contact Grid can be separately positioned on the surface of the first pipe joint PC1 and the second pipe joint PC2.
Adjacent lower prop DP1 and DP2 can be with shared word line WL<0>,WL<1>,WL<2>And WL<3>.However, when increase with When the adjacent upper props of upper prop UP1 and UP2, adjacent upper prop can be configured to shared word line WL<4>,WL<5>,WL<6>And WL< 7>。
Using the vertical non-volatile storage device described with reference to figure 3 to Fig. 6, memory block may include multiple unit strings, Each unit string selects line options by least two strings.Although however, be formed in the storage unit of same layer with it is not selected The connection of string selection line, but these storage units can be exposed to program voltage.
Fig. 7 is the selection structure for the non-volatile memory device for schematically showing one embodiment according to present inventive concept Circuit diagram.With reference to figure 7, memory block may include multiple unit strings.Memory block can with for selecting the more of multiple unit strings Item string selection line SSL<0>To SSL<2>Connection.
One or more memory blocks can be selected by activating the block selection signal BLKWL of memory block to be selected.Block selects Select path transistor 122a and 122b that signal BLKWL can be switched on or switched off in decoder 122.Selection signal SS<0>To SS< 2>String selection line SSL can be sent to passage path transistor 122a<0>To SSL<2>.Drive signal S<0>To S<7>It can lead to It crosses path transistor 122b and is sent to circuit WL<0>To WL<7>And GSL.
As selection signal SS<0>When being activated, with string selection line SSL<0>The unit string of connection can be with bit line BL<0>Extremely BL<2>It is electrically connected.As offer drive signal S<0>To S<7>When can be to sub-block SB<0>In storage unit programming.When Selection signal SS<1>When being activated, with string selection line SSL<1>The unit string of connection can be with bit line BL<0>To BL<2>Respectively Electrical connection.As offer drive signal S<0>To S<7>When can be to sub-block SB<1>In storage unit programming.As selection signal SS <2>When being activated, with string selection line SSL<2>The unit string of connection can be with bit line BL<0>To BL<2>It is electrically connected.When carrying For drive signal S<0>To S<7>When can be to sub-block SB<2>In storage unit programming.
Using present inventive concept, selection signal SS can be changed according to the loss average information of selected memory block<0 >To SS<2>Activation sequence.In such a case, it is possible to significantly decrease due to string selection line fixation selecting sequence and Store the voltage stress caused by particular memory location in the block.This will be described more fully below.
Fig. 8 A to Fig. 8 D are the diagrams for the selecting sequence for showing the string selection line according to one embodiment of present inventive concept.
Fig. 8 A show the SSL that puts in order according to string selection line<0>To SSL<7>To be sequentially selected the feelings of storage unit Condition.It can select and go here and there selection line SSL in selected memory block<0>The storage unit of connection.For example, working as supply voltage Vcc is applied to string selection line SSL<0>And ground voltage（For example, 0V）It is applied to string selection line SSL<1>To SSL<7>When, It can select and go here and there selection line SSL<0>The storage unit of connection.It can be by being sequentially applied to wordline WL<0>To WL<7>'s Program voltage carrys out the storage unit programming to selected cell string.
When power source voltage Vcc is applied to string selection line SSL<1>And ground voltage（For example, 0V）It is applied to string selection line SSL<0>And SSL<2>To SSL<7>When, it can select and go here and there selection line SSL<1>The storage unit of connection.Sequence can be passed through Ground is applied to wordline WL<0>To WL<7>Program voltage come to the programming of the storage unit of selected cell string.Can according to The same or analogous mode of mode described above is sequentially selected remaining string selection line SSL<2>To SSL<7>.
The selecting sequence of string selection line in Fig. 8 A can be as the default value of general non-volatile memory device.Namely It says, when erasing is counted less than reference value, Memory Controller 110 can generate address AD D to select as shown in Figure 8 A String selection line.
The case where Fig. 8 B show the reverse sequence according to sequence shown in Fig. 8 A to select string selection line.That is, in quilt In the memory block of selection, it can select first and string selection line SSL<7>The storage unit of connection.When power source voltage Vcc applies To string selection line SSL<7>And ground voltage（For example, 0V）It is applied to string selection line SSL<0>To SSL<6>When, it can select With string selection line SSL<7>The storage unit of connection.It can be by being sequentially applied to wordline WL<0>To WL<7>Program voltage Carry out the storage unit programming to selected cell string.
When power source voltage Vcc is applied to string selection line SSL<6>And ground voltage（For example, 0V）It is applied to string selection line SSL<0>To SSL<5>And SSL<7>When, it can select and go here and there selection line SSL<6>The storage unit of connection.Sequence can be passed through Ground is applied to wordline WL<0>To WL<7>Program voltage come to the programming of the storage unit of selected cell string.Can according to The same or analogous mode of mode described above is sequentially selected remaining string selection line SSL<0>To SSL<5>.
Fig. 8 C are shown from center outward come the case where selecting string selection line.It as shown in Figure 8 C, can be according to first choice Mode ME1 or the second selection mode ME2 selects string selection line SSL<0>To SSL<7>.
The ME1 in the way of first choice can be selected and string selection line SSL first<3>Connection by selection memory block Storage unit.Then, string selection line SSL can be sequentially selected<2>, string selection line SSL<1>With string selection line SSL<0>.With 1. the arrow indicated shows the selection sequence.It is then possible to selection and string selection line SSL first<4>Connection is deposited by selection Store up the storage unit of block.Then, string selection line SSL can be sequentially selected<5>, string selection line SSL<6>With string selection line SSL< 7>.The selection sequence is shown with the arrow 2. indicated.
Using the second selection mode ME2, can select first and string selection line SSL<4>Connection by selection memory block Storage unit.Then, string selection line SSL can be sequentially selected<5>, string selection line SSL<6>With string selection line SSL<7>.With 1. the arrow indicated shows the selection sequence.It is then possible to selection and string selection line SSL first<3>Connection is deposited by selection Store up the storage unit of block.Then, string selection line SSL can be sequentially selected<2>, string selection line SSL<1>With string selection line SSL< 0>.The selection sequence is shown with the arrow 2. indicated.
Fig. 8 D show to select another situation of string selection line outward from center.It, can be according to first as shown in Fig. 8 D Z zag manners Zig1 or the 2nd z zag manners Zig2 selects string selection line SSL<0>To SSL<7>.
Using the first z zag manner Zig1, can select first and string selection line SSL<3>Connection by selection memory block Storage unit.Then, string selection line SSL can be sequentially selected<4>, string selection line SSL<2>, string selection line SSL<5>With String selection line SSL<1>.It is then possible to be sequentially selected string selection line SSL<6>, string selection line SSL<0>With string selection line SSL <7>。
Using the 2nd z zag manner Zig2, can select first and string selection line SSL<4>Connection by selection memory block Storage unit.Then, string selection line SSL can be sequentially selected<3>, string selection line SSL<5>, string selection line SSL<2>With String selection line SSL<6>.It is then possible to be sequentially selected string selection line SSL<1>, string selection line SSL<7>With string selection line SSL <0>。
It is exemplary in the above-mentioned selecting sequence for storing string selection line in the block.It can be based on by the damage of selection memory block Average information is consumed to adjust address, to select string selection line according to different selecting sequences.
Fig. 9 is the flow chart for schematically showing the programmed method executed in storage system shown in Fig. 1.With reference to figure 9, When programming operation, Memory Controller 110 can be selected based on string is reconfigured by the loss average information WLCNT of selection memory block Select the address of line.In the following, will be counted according to erasing to describe loss average information WLCNT.
In operation sl 10, if host asks write operation, it can provide to Memory Controller 110 and be asked with write-in Seek corresponding logical address.In general, flash translation layer (FTL) can be passed through（FTL）The logical address provided from host is mapped to object Manage address.Using mapping address ADD, the string selection line of memory block can be sequentially selected according to putting in order.
In operation s 120, Memory Controller 110 can be detected by the loss average information of selection memory block（For example, Erasing counts）.In the exemplary embodiment, the manager 10 that can be averaged from the loss of Memory Controller 110 offer is selected The loss average information of memory block（For example, erasing counts）.
In operating S130, Memory Controller 110 can by be lost average information WLCNT value compared with reference value, And it can obtain method according to comparison result.When the value of loss average information WLCNT is less than reference value 1K（1024）When, the party Method carries out operation S140.When the value of loss average information WLCNT is greater than or equal to reference value 1K（1024）And it is less than reference value 2K（2048）When, this method carries out operation S150.When the value of loss average information WLCNT is greater than or equal to reference value 2K （2048）When, this method carries out operation S160.As described herein, memory block can be divided into according to loss average information WLCNT Three groups.However, present inventive concept is without being limited thereto.For example, can according to loss average information WLCNT by memory block be divided into two groups or Four groups of person or more group.
In operating S140, the value that Memory Controller 110 can keep and be lost average information WLCNT is more than or waits In 0 and be less than 1K（1024）The associated string selection line address of memory block, with default value.Memory Controller 110 Address remapper 20 can establish string selection line address so that according to SSL<0>To SSL<7>Put in order（For example, Ascending order）To select to be selected the string selection line of memory block.If default value is configured such that the selecting sequence of string selection line is abided by It follows and puts in order, then address remapper 20 can bypass string selection line address corresponding with default value.
In operating S150, Memory Controller 110 can reconfigure and be lost average information WLCNT value be more than or The associated string selection line address of memory block equal to 1K and less than 2K.The address remapper 20 of Memory Controller 110 String selection line address can be established so that according to different from SSL<0>To SSL<7>Put in order to select to be selected memory block String selection line.For example, address remapper 20 can adjust string selection line address so that shown in Fig. 8 C and Fig. 8 D Sequence one of come select string selection line.
In operating S160, the value that Memory Controller 110 can adjust and be lost average information WLCNT is more than or waits In the associated string selection line address of the memory block of 2K so that according to the reverse sequence to put in order（For example, descending）To select to go here and there Selection line.For example, the address remapper 20 of Memory Controller 110 can adjust string selection line address so that according to SSL<0>To SSL<7>The reverse sequence SSL for putting in order opposite<7>To SSL<0>To select to be selected the string of memory block to select Select line.
In operating S140, S150 and S160, the address after adjustment（Including the string selection line address after adjustment）It can claim For secondary physical address.Compared with secondary physical address, the physical address generated by FTL is properly termed as primary physical address.Figure ADD in 1 remap device 20 can by its own mapping table or map according to shown in step S140, S150 and S160 Primary physical address conversion is secondary physical address by rule.If the device that remaps has bypassed primary physical address, Secondary physical address is identical as primary address.
In another embodiment of present inventive concept, FTL may include the device that remaps.FTL, which can be received, to be come independently The logical address of machine and physical address is generated, after which can reflect the adjustment for selecting string selection line address Sequentially.
In operating S170, Memory Controller 110 can be according to bypass or after adjustment string selection line address in quilt The memory block of selection programs data.
As described above, Memory Controller 110 can selectively be adjusted according to loss average information WLCNT String selection line address.Therefore, non-volatile memory device 120 need not adjust string selection line address or including supporting string selection The function of line address adjustment.
Figure 10 A to Figure 10 H are to show to provide write instruction and address related with selected memory block from Memory Controller Method sequence diagram.Memory Controller 110（As shown in Figure 1）It can be according to by the loss average information of selection memory block WLCTN determines the output sequence of string selection line address.Memory Controller 110 can based on identified sequence come to it is non-easily The property lost storage device 120 provides the address for select storage unit.Herein, the variation of row and column address can be ignored With the change over order of description string selection line address.Can not show to be provided a multiple number of times in write instruction sequence with string selection line The related row and column address in address.However, the position of string selection line address be not limited to the present embodiment or it is disclosed herein other Embodiment.String selection line address can be designated as a part for column address, row address or block address.The arrangement of address sequence with And the definition of address sequence itself can be different according to the cell array structure of non-volatile memory device 120.Before programming Data transmission size can be according to architecture（For example, the page buffer of non-volatile memory device 120, address buffer The size of device and instruction latch）And it is different.The size of data transmission can be as unit of one or more pages.
With reference to figure 10A, Memory Controller 110 can provide quilt according to putting in order to non-volatile memory device 120 Select the string selection line address of memory block.Memory Controller 110 can provide write-in to non-volatile memory device 120 and refer to Enable sequence.When the status signal R/B of non-volatile memory device 120 is in ready state（For example, high state）When, memory control Device 110 processed can provide the input/output terminal of non-volatile memory device 120 to write instruction sequence 80h-ADD0-Din-10h I/Oi.Non-volatile memory device 120 can be in response to indicating the input ' 10h ' that programming confirms and by the shape of status signal R/B State is switched to busy condition（For example, low state）.Non-volatile memory device 120 can be deposited corresponding with address AD D0 Storage area domain programs input data Din.
As shown in Figure 10 A, address AD D0 may include column address CA, row address RA, block address BA and string selection line address SSL<0>.It shows by selection string selection line SSL<0>On an instruction sequence.It will be appreciated, however, that continuous provide and phase The row answered and corresponding wordline（For example, WL<0>To WL<7>）Related write instruction sequence.For ease of description, in sequence of instructions String selection line SSL is only representatively shown in row<0>,SSL<1>And SSL<2>The case where.Address AD D1 may include column address CA, row address RA, block address BA and string selection line address SSL<1>.Address AD D2 may include column address CA, row address RA, block Address BA and string selection line address SSL<2>.
It as described above, can be according to putting in order（SSL<0>To SSL<7>）It is sequentially selected by selection memory block String selection line.
With reference to figure 10B, during the unit of selected string programs last data, in non-volatile memory device 120 Status signal R/B be in busy condition（For example, low state）When, Memory Controller 110 can be filled to non-volatile memories 120 offer program instructions, columns and rows address, block address, string selection line address and/or serial data are provided.Data transfer depends on In the capacity of the page buffer of non-volatile memory device 120.By storing next instruction, next address and/or next number According to, if non-volatile memory device can prepare next programming operation during the unit Series Code journey to currently selecting, So non-volatile memory device 120 can save programming time.
With reference to figure 10C, Memory Controller 110 can be filled according to the reverse sequence to put in order to non-volatile memories String selection line address of 120 offers by selection memory block is provided.
Address AD D0 may include column address CA, row address RA, block address BA and string selection line address SSL<7>.Address ADD1 may include column address CA, row address RA, block address BA and string selection line address SSL<6>.Address AD D2 may include Column address CA, row address RA, block address BA and string selection line address SSL<5>.It as described above, can be according to putting in order Reverse sequence（SSL<7>To SSL<0>）To be sequentially selected by the string selection line of selection memory block.
With reference to figure 10D, write instruction sequence corresponding with the first choice mode ME1 in Fig. 8 C is shown.Memory Controller 110 can be provided from center to edge by the string selection line address of selection memory block.With corresponding row or corresponding word Line（For example, WL<0>To WL<7>）Related write instruction sequence follows write instruction sequence corresponding with string selection line.
Address AD D0 may include string selection line address SSL<3>, address AD D1 may include string selection line address SSL<2 >, address AD D2 may include string selection line address SSL<1>, address AD D3 may include string selection line address SSL<0>.Then, Address AD D4 may include string selection line address SSL<4>, address AD D5 may include string selection line address SSL<5>, address ADD6 may include string selection line address SSL<6>, address AD D7 may include string selection line address SSL<7>.
Partly change this sequentially with the second selection mode ME2 in application drawing 8C.
With reference to figure 10E, write instruction sequence corresponding with the first z zag manners Zig1 in Fig. 8 D is shown.Storage Device controller 110 can be according to the first z zag manners Zig1 to put in order or the 2nd z zag manners about string selection line Zig2 is provided by the string selection line address of selection memory block.With corresponding row or corresponding wordline（For example, WL<0>To WL<7 >）Related write instruction sequence follows write instruction sequence corresponding with string selection line.
Address AD D0 may include string selection line address SSL<3>, address AD D1 may include string selection line address SSL<4 >, address AD D2 may include string selection line address SSL<2>, address AD D3 may include string selection line address SSL<5>.Then, Although being not shown in the accompanying drawings, address AD D4 may include string selection line address SSL<1>, address AD D5 may include String selection line address SSL<6>, address AD D6 may include string selection line address SSL<0>, address AD D7 may include string selection Line address SSL<7>.
With reference to figure 10F, Memory Controller 110 can be according to other sequences according to the other embodiment of present inventive concept To provide by the string selection line address of selection memory block to non-volatile memory device 120.
Address AD D may include column address CA, row address RA, block address BA.String selection line address SSL can be designated as Column address CA, row address RA or block address BA.It can be transmitted after address is transmitted and go here and there the corresponding numbers of selection line address SSL According to transmission Din.Memory Controller 110 can provide write instruction sequence to non-volatile memory device 120.When non-volatile The status signal R/B of storage device 120 is in ready state（For example, high state）When, Memory Controller 110 can be to write-in Instruction sequence 80h-ADD0-Din0-10h provides the input/output terminal I/Oi of non-volatile memory device 120.It is non-volatile to deposit The state of status signal R/B can be switched to busy shape by storage device 120 in response to indicating the input ' 10h ' that programming confirms State（For example, low state）.Non-volatile memory device 120 can be in storage region corresponding with address AD D0 to input data Din is programmed.
With reference to figure 10G, Memory Controller 110 can be according to other sequences according to the other embodiment of present inventive concept To provide by the string selection line address of selection memory block to non-volatile memory device 120.
Address AD D may include column address CA, row address RA.String selection line address SSL can be designated as column address CA Or row address RA.It can be transmitted after address is transmitted and go here and there the corresponding data transmission Din of selection line address SSL.Memory Controller 110 can provide write instruction 80h to non-volatile memory device 120（Page write instruction）Or 85h（Random writing Instruction）.Random writing instructs the part that can only transmit the address transmitted according to page write instruction.Random writing（Relatively It is written in the page）The remaining address not transmitted assume that identical for address those of is written with the page.In other words, at random Write instruction can send the unique address for determining down a string of selection line addresses.When the shape of non-volatile memory device 120 State signal R/B is in ready state（For example, high state）When, Memory Controller 110 can be to write instruction sequence 80h- ADD0-Din0-10h provides the input/output terminal I/Oi of non-volatile memory device 120.Non-volatile memory device 120 can be with The state of status signal R/B is switched to busy condition in response to indicating the input ' 10h ' that programming confirms（For example, low shape State）.Non-volatile memory device 120 can program input data Din0 in storage region corresponding with address AD D0.? After address AD D0 programs Din0, non-volatile memory device 120 can keep row address RA0, RA1 identical with RA2, and Next instruction 85h（Random writing）Column address related with the string selection line address of selection can only be changed.
However, random writing（85h）Address format can according to the architecture of non-volatile memory device 120 and Variation.Random writing instruction with address AD D1（85h）Can change be stored in non-volatile memory device 120 the page it is slow Rush the page data in device.By send random writing instruction, Memory Controller 110 can change string selection line address and The all or part of page data being stored in the page buffer of non-volatile memory device 120.
With reference to figure 10H, Memory Controller 110 can send 85h（Random writing instructs）And 10h（Confirm instruction）It Forward direction non-volatile memory device 120 provides 80h（Page write instruction）And 10h（Confirm instruction）.In address AD D0 to Din0 After programming, non-volatile memory device 120 can keep row address RA0, RA1, RA2 identical, and next instruction 85h（With Machine is written）Column address related with string selection line address is determined can only be changed.But random writing（85h）Address format It can be changed according to the architecture of non-volatile memory device 120.
The address of 110 transmission is filled from nonvolatile memory control and data before transmission can be according to non-volatile memories The loss average information WLCNT of the memory block of device 120 is arranged.For example, with reference to figure 10H, according to determining string selection line The loss average information of location sequence, can transfer address ADD7 first and its corresponding data Din7, and address AD D6 and its corresponding Data Din6 can be transmitted then.
With reference to figure 1, remapped this document describes the address by Memory Controller 110 to change the choosing of string selection line Select the technology of sequence.In such a case, it is possible to which it is similar non-volatile that the programmed method of present inventive concept is applied to other Storage device.
Figure 11 is the block diagram for the storage system for schematically showing another embodiment according to present inventive concept.Reference chart 11, storage system 400 may include Memory Controller 410 and non-volatile memory device 420.Herein, memory control Device 410 processed can be based on loss average information and provide specific write instruction CMD to non-volatile memory device 420.For example, storage Device controller 410 can provide the write instruction CMD for including loss average information to non-volatile memory device 420.For example, writing It can be that SET_FEATURE is instructed with configuring non-volatile storage device 420 to enter to instruct CMD.It can be instructed in SET_FEATURE Immediately or shortly after that transmitting configuration information later（For example, average or selection line address sequence variation is lost）.It is non-volatile Storage device 420 can reconfigure string selection line address in response to write instruction CMD and loss average information.
Memory Controller 410 may include the average manager 415 of loss, be configured to managing non-volatile storage device The loss average information of 420 all memory blocks.When asking write operation from external equipment, Memory Controller 410 can be with The write instruction CMD for including loss average information WLCNT is provided to non-volatile memory device 420.
Non-volatile memory device 420 can in response to comprising loss average information WLCNT write instruction CMD and again Mapping string selection line address.Non-volatile memory device 420 may include address remapper 425, be configured to adjustment string Selection line address.Address remapper 425 can be re-established based on the loss average information WLCNT included in instruction By the selecting sequence of the string selection line of selection memory block.By address remapper 425, non-volatile memory device 420 can To select string selection line according to the reverse sequence or z fonts sequence that put in order, put in order.
As described above, the storage system 400 of present inventive concept may include Memory Controller 410, be configured to Write instruction is provided to loss average information WLCNT.Non-volatile memory device 420 can be based on the damage for being provided with write instruction Average information WLCNT is consumed to adjust by the selecting sequence of the string selection line in selection memory block.
Figure 12 A and Figure 12 B are to schematically show to be filled according to the non-volatile memories of another embodiment of present inventive concept Set 420 block diagram.With reference to figure 12A and Figure 12 B, non-volatile memory device 420 may include memory cell array 421A or 421B, decoder 422, page buffer 423, control logic 424 and address remapper 425.Constituent element 421A or The construction of 421B to 423 can be identical as the construction of element shown in Fig. 1, thus omits their description.
Control logic 424 can control page buffer 423 and address weight in response to the instruction CMD from external equipment New mappings device 425.Control logic 424 can provide the loss being included in instruction CMD to address remapper 425 and averagely believe Cease WLCNT.Address remapper 425 can reconfigure the string choosing of input address ADD based on loss average information WLCNT Select line address.Decoder 422 can be provided to the address AD D' of the sequence of adjustment string selection line by being reconfigured.Pass through Address remapper 425 can select to be selected according to the reverse sequence or z fonts sequence that put in order, put in order The string selection line of memory block.
Non-volatile memory device 420 can based on the loss average information WLCNT provided from Memory Controller 410 come Adjustment string selection line address.When loss average counter（For example, erasing counts）String selection line can be switched when more than reference value Selecting sequence.By the selecting sequence of switching string selection line, the stress being applied in the storage unit of memory block can be reduced.
The loss average information WLCNT of memory block in non-volatile memory device 420 can be stored in non-volatile In the virtual region of the storage address page, which will not be used for storing user data.When being programmed to user data, Loss average information can be stored in virtual region by Memory Controller.Virtual region may be embodied in non-volatile memories In all pages of device 421A or in the memory block of non-volatile memory device 421B.Average information is lost can be non-easy The power supply of the property lost storage system 400 is stored in before disconnecting in non-volatile memory device 420, and in non-volatile memories system System 400 is read when powering on from non-volatile memory device 420.When loss average information is stored in non-volatile memories dress When in setting 420, in order to make loss average counter have better reliability, can be lost average counter important position replicate and Encryption.
Figure 13 is the flow chart for schematically showing the programmed method of non-volatile memory device shown in Figure 12 A and Figure 12 B. With reference to figure 13, non-volatile memory device 420 can be based on the loss average information included in instruction come string choosing of remapping Select line address.
In operating S210, it includes loss that non-volatile memory device 420, which can be received from Memory Controller 410, The write instruction CMD of average information WLCNT.Memory Controller 410 can detect damage corresponding with selected memory block Consumption average information simultaneously encodes to be included in write instruction it.Control logic 424 can decode write instruction to extract damage Consume average information WLCNT.Loss average information WLCNT can be provided to address remapper 425 by control logic 424.
In operating S220, address remapper 425 can be obtained from loss average information WLCNT and be deposited by selection Store up the group information of block.Input address ADD can be reconfigured for adjusting by address remapper 425 according to the group information Address AD D' after whole.
In operating S230, address remapper 425 can carry out the branch of operating procedure, with according to the average letter of loss WLCNT is ceased to determine by the selecting sequence of the string selection line of selection memory block.When the value of loss average information WLCNT is greater than or equal to Reference value 0 and be less than reference value 1K（1024）When, this method carries out operation S240.When the value of loss average information WLCNT is big In or equal to reference value 1K（1024）And it is less than reference value 2K（2048）When, this method carries out operation S250.When loss is average The value of information WLCNT is greater than or equal to reference value 2K（2048）When, this method carries out operation S260.It herein, can basis Memory block is divided into three groups by loss average information WLCNT.However, present inventive concept is without being limited thereto.For example, can be flat according to loss Memory block is divided into two groups or four groups or more groups by equal information WLCNT.
In operating S240, address remapper 425 can keep and be lost average information WLCNT value be more than or Equal to 0 and it is less than 1K（1024）The associated string selection line address of memory block, with default value.Address remapper 425 can establish string selection line address so that according to SSL<0>To SSL<7>Put in order（For example, ascending order）To select to be chosen Select the string selection line of memory block.It puts in order if default value is configured such that the selecting sequence of string selection line follows, The location device 425 that remaps can bypass string selection line address corresponding with default value.
In operating S250, the value that address remapper 425 can reconfigure and be lost average information WLCNT is more than Or the associated string selection line address of memory block equal to 1K and less than 2K.Address remapper 425 can establish string selection Line address so that according to different from SSL<0>To SSL<7>Put in order to select to be selected the string selection line of memory block.Example Such as, address remapper 425 can adjust string selection line address so that according to one of sequence shown in Fig. 8 C and Fig. 8 D come Selection string selection line.
In operating S260, address remapper 425 can adjust and be lost average information WLCNT value be more than or String selection line address associated equal to the memory block of 2K so that according to the reverse sequence to put in order（For example, descending）To select String selection line.For example, address remapper 425 can adjust string selection line address so that according to SSL<0>To SSL<7> The reverse sequence SSL for putting in order opposite<7>To SSL<0>To select to be selected the string selection line of memory block.
In operating S270, control logic 424 can be in memory block corresponding with the address AD D' after adjustment to data Programming.That is, passing through address remapper 425, it may be considered that loss average information WLCNT is to according to string selection line The storage unit programming of the memory block of location selection.
As described above, Memory Controller 410 can be provided to non-volatile memory device 420, and there is write-in to refer to The loss average information WLCNT of order.Non-volatile memory device 420 can be reconfigured based on loss average information WLCNT By the string selection line address of selection memory block.
Figure 14 is the address tune for describing the address remapper of non-volatile memory device shown in Figure 12 A and Figure 12 B The table of whole operation.With reference to figure 14, input string selection line address can be according to loss average information WLCNT in that same order Or the sequence after changing is remapped.
If being greater than or equal to 0 by the value of the loss average information WLCNT of selection memory block and being less than 1K（1024）, then Address remapper 425 can export address AD D' after adjustment identical with input value.That is, working as input address ADD String selection line address correspond to SSL<3>When, address remapper 425 can export identical string selection line address SSL <3>。
If being greater than or equal to 1K by the value of the loss average information WLCNT of selection memory block and being less than 2K, address The device 425 that remaps can adjust input address so that select string selection line according to z zag manners.For example, string selection line Location SSL<0>,SSL<1>,SSL<2>And SSL<3>It can be respectively mapped to string selection line address SSL<3>,SSL<4>,SSL<2> And SSL<5>.In addition, string selection line address SSL<4>,SSL<5>,SSL<6>And SSL<7>It can be respectively mapped to string selection line Address SSL<1>,SSL<6>,SSL<0>And SSL<7>.
Address remapper 425 can adjust string selection line address, averagely to believe by the loss of selection memory block The value of breath WLCNT is selected when being greater than or equal to 2K according to the reverse sequence to put in order.For example, string selection line address SSL< 0>,SSL<1>,SSL<2>And SSL<3>It can be respectively mapped to string selection line address SSL<7>,SSL<6>,SSL<5>And SSL <4>.In addition, string selection line address SSL<4>,SSL<5>,SSL<6>And SSL<7>It can be respectively mapped to string selection line address SSL<3>,SSL<2>,SSL<1>And SSL<0>.
Figure 15 is the diagram for the effect for showing present inventive concept.It is suitable in the selection of the string selection line of memory block with reference to figure 15 In the case of sequence is fixed, the threshold voltage distribution of the storage unit formed according to programming progress is shown.According to programming progress, show Each string selection line SSL is gone out to share<0>To SSL<7>Storage unit threshold voltage distribution.
Before programming, with string selection line SSL<0>All storage units of connection are included in threshold voltage distribution 500 In.In the 2 data programming of selected storage unit pair, can be formed threshold voltage distribution 510 indicated by the solid line, 520,530 and 540.Due to word line stacks structure, with string selection line SSL<0>The storage unit of connection is applied in stress, Zhi Daoyu String selection line SSL<1>To SSL<7>Until the storage unit of connection is programmed.In completion pair and string selection line SSL<7>Connection After the programming of storage unit, threshold voltage distribution 510', 520', 530' and 540' as shown by dashed lines can be formed.
Before programming, with string selection line SSL<1>All storage units of connection are included in threshold voltage distribution 500 In.When completing programming operation, threshold voltage distribution 511,521,531 and 541 indicated by the solid line can be formed.Due to wordline Stacked structure, with string selection line SSL<1>The storage unit of connection is applied in stress, until with string selection line SSL<2>To SSL< 7>Until the storage unit of connection is programmed.In completion pair and string selection line SSL<7>After the programming of the storage unit of connection, Threshold voltage distribution 511', 521', 531' and 541' as shown by dashed lines can be formed.
Before programming, with string selection line SSL<6>All storage units of connection are included in threshold voltage distribution 500 In.When completing programming operation, threshold voltage distribution 516,526,536 and 546 indicated by the solid line can be formed.Due to wordline Stacked structure, with string selection line SSL<6>The storage unit of connection is applied in stress, until with string selection line SSL<7>Connection Until storage unit is programmed.In completion pair and string selection line SSL<7>After the programming of the storage unit of connection, it can be formed Threshold voltage as shown by dashed lines is distributed 516', 526', 536' and 546'.Here, with string selection line SSL<6>Connection is deposited Among storage unit, with erase status storage unit can with string selection line SSL<0>When the storage unit of connection is programmed Time point is applied in stress.For this purpose, distribution 516' corresponding with erase status E0 can be by extra wide.In this case, Stress can be extraly applied in storage unit, thus accelerate the deterioration of oxidation film.
Specifically, before programming, with string selection line SSL<7>All storage units of connection are included in threshold value electricity In pressure distribution 500.With string selection line SSL<7>Before the storage unit of connection is programmed, it can be formed as shown in dotted line 517' Threshold voltage distribution.517 are distributed according to threshold voltage, due to superposition among storage unit corresponding with erase status E0 Stress and can exist threshold voltage distribution higher than 0V storage unit.In completion pair and string selection line SSL<7>The storage of connection After the programming of unit, threshold voltage distribution 517', 527', 537' and 547' as shown by dashed lines can be formed.
Here, threshold voltage corresponding with the erase status E0 distribution 517' of storage unit may be grasped in digital independent As when generate mistake.Because with string selection line SSL<7>The storage unit of connection applies stress with being applied, so storage unit Oxidation film can relatively rapidly deteriorate.
The selecting sequence of string selection line can be changed by using loss average information to solve the above problems.Utilize this hair Bright design can the balanced deterioration for storing storage unit in the block.Increase although erasing counts, is generated because of voltage stress The deterioration of storage storage unit in the block become evenly.Therefore, compared with the case where voltage stress is concentrated, it can improve and deposit The reliability of storage unit.
Figure 16 is to show to include the block diagram according to the user equipment of the solid state drive of one embodiment of present inventive concept. With reference to figure 16, user equipment 1000 may include host 1100 and solid state drive（Hereinafter referred to as SSD）1200.SSD1200 can To include SSD controller 1210, buffer storage 1220 and non-volatile memory device 1230.
SSD controller 1210 can provide physical connection between host 1100 and SSD1200.SSD controller 1210 can So that interface has SSD1200 corresponding with the bus form of host 1100.Specifically, SSD controller 1210 can be right Instruction from host 1100 is decoded.SSD controller 1210 can access non-volatile memory device according to decoding result 1230.The bus form of host 1100 may include USB（Universal Serial Bus）,SCSI（Small Computer System Interface）,PCI express, ATA,PATA（Parallel ATA）,SATA（Serial ATA）,SAS （Serial Attached SCSI）Deng.
Buffer storage 1220 can temporarily store write-in data from host 1100 or from non-volatile memories The data that device 1230 is read.If there is the data in non-volatile memory device 1230 host 1100 read requests In be buffered, then buffer storage 1220 can support directly to host 1100 provide be buffered data caching function. In general, the bus form of host 1100（For example, SATA or SAS）Data transfer rate can be higher than SSD1200 memory channel Speed.That is, if the interface rate of host 1100 is very fast, can be deposited by providing the buffering of big storage volume Reservoir 1220 reduces as much as possible because speed difference causes reduced performance.
Buffer storage 1220 can be formed by synchronous dram, with to as the SSD1200 for assisting mass storage Enough bufferings are provided.However, buffer storage 1220 is not limited to disclosure herein.
Non-volatile memory device 1230 may be used as the storage medium of SSD1200.For example, non-volatile memory device 1230 can be formed by the vertical nand flash memory device with big storage volume.Non-volatile memory device 1230 can be by multiple Storage device is formed.In this case, storage device can be connect by channel unit with SSD controller 1210.As storage Medium is deposited, non-volatile memory device 1230 can be formed by nand flash memory.However, non-volatile memory device 1230 is not limited to Nand flash memory device.For example, the storage medium of SSD1200 can be by formation such as PRAM, MRAM, ReRAM, FRAM, NOR flash memories. In addition, present inventive concept can be applied to the storage system that different type storage device uses together.Non-volatile memories fill The construction for setting 1230 can be essentially identical with the construction described in Fig. 1.
SSD controller 1210 can adjust the string selection line of non-volatile memory device 1230 based on loss average information Selecting sequence.By means of which, the service life of SSD1200 can be extended and improve the reliability of data.
Figure 17 is the block diagram for the storage system for showing another embodiment according to present inventive concept.With reference to figure 17, storage System 2000 may include nonvolatile memory 2100 and Memory Controller 2200.
The construction of nonvolatile memory 2100 can be essentially identical with construction shown in Fig. 1 or Figure 11, so omitting it Description.
Memory Controller 2200 is it is so structured that control nonvolatile memory 2100.SRAM 2230 may be used as The working storage of CPU2210.Host interface 2220 may include the data exchange association for the host being connect with storage system 2000 View.ECC Block 2240 is it is so structured that detection and correction are included in from the mistake in the data that nonvolatile memory 2100 is read. Memory interface 2260 can be with 2100 interfaces of nonvolatile memory according to one embodiment of present inventive concept. CPU2210 can execute the whole control operation of the data exchange for Memory Controller 2200.Although not having in fig. 17 It shows, but storage system 2000 can also include ROM of the storage for the coded data with host interfaces.
Memory Controller 2200 can by such as USB, MMC, PCI-E, SAS, SATA, PATA, SCSI, ESDI, One of interface protocols such as IDE and external equipment（For example, host）Communication.
Memory Controller 2200 can adjust the string choosing of non-volatile memory device 2100 based on loss average information Select the selecting sequence of line.By means of which, the service life of storage system 2000 can be extended and improve the reliability of data.
In the exemplary embodiment, storage system 2000 may be used as computer, portable computer, super mobile PC （UMPC）, it is work station, net book, PDA, online flat board computer, radio telephone, mobile phone, smart phone, e-book, portable Formula multimedia player（PMP）, digital camera, digital audio recorder/player, digital photograph/video recorder/broadcasting Device, portable game machine, navigation system, black box, 3 dimension TVs, can send and receive information in the wireless context device, Form one of various electronic devices of one of various electronic devices of home network, composition computer network, composition telecommunication One of the various electronic devices of one of various electronic devices of network, RFID or composition computer system.
Figure 18 is the block diagram for the data storage device for showing another embodiment according to present inventive concept.With reference to figure 18, Data storage device 3000 may include flash memory 3100 and flash controller 3200.Flash controller 3200 can be in response to from number Flash memory 3100 is controlled according to 3000 externally input control signal of storage device.
The construction of flash memory 3100 can be essentially identical with the construction with reference to described in figure 1 or Figure 11.Flash controller 3200 can To adjust the selecting sequence of the string selection line of flash memory 3100 based on loss average information.By means of which, it can extend and deposit The service life of storage system 3000 and the reliability for improving data.
Data storage device 3000 can be memory card device, SSD devices, multimedia memory card device, SD devices, memory Bar device, HDD device, hybrid drive device or USB flash memory devices.For example, data storage device 3000 can meet to use Family equipment（For example, digital camera, personal computer etc.）The card using standard.
Figure 19 is to show to include the block diagram according to the computer system of the flash memory device of one embodiment of present inventive concept. With reference to figure 19, computer system 4000 may include flash memory device 4100, Memory Controller 4200, modem 4300 （For example, baseband communication chipset）, microprocessor 4500 and user interface 4600.Element 4200,4300,4500 and 4600 can To be electrically connected to bus 4400.
The construction of flash memory device 4100 and Memory Controller 4200 can be basic with the construction with reference to described in figure 1 or Figure 11 It is identical.Memory Controller 4200 can be suitable come the selection for adjusting the string selection line of flash memory device 4100 based on loss average information Sequence.By means of which, the service life of computer system 4000 can be extended and improve the reliability of data.
If computer system 4000 is mobile device, computer system 4000 can also include the battery for its power supply 4700.Although being not shown in Figure 19, computer system 4000 can also include application program chipset, camera diagram As processor（CIS）, mobile DRAM etc..Memory Controller 4200 and flash memory device 4100 can be formed to be deposited using non-volatile Reservoir stores solid state drive/solid-state disk of data（SSD）.
The encapsulation of non-volatile memory device or Memory Controller can be selected from following different types of packaged type example Such as：Laminate packaging（PoP）, ball grid array（BGA）, chip size packages（CSP）, plastics formula leaded chip carrier（PLCC）, modeling Expect dual-inline package（PDI2P）, wafer assemblies chip（Die in Waffle Pack）, wafer format chip（Die in Wafer Form）, chip on board（COB）, ceramic dual in-line package（CERDIP）, plastics metric system quad flat package （MQFP）, slim quad flat package（TQFP）, the encapsulation of small outline integrated circuit（SOIC）, reduce outline packages（SSOP）, it is thin Type small-sized package（TSOP）, system in package（SIP）, multi-chip package（MCP）, wafer grade manufacture encapsulation（WFP）, wafer grade Handle laminate packaging（WSP）Deng.
Although describing present inventive concept by reference to exemplary embodiment, in the spirit and model for not departing from the present invention In the case of enclosing, those skilled in the art obviously can carry out variations and modifications.It will thus be appreciated that above-described embodiment It is not limiting, but it is illustrative.

Claims (36)

1. a kind of method to non-volatile memory device programming, the non-volatile memory device is included in perpendicular to substrate The unit string being just upwardly formed, the method includes：
Detection is by the loss average information of selection memory block；
The selecting sequence to multiple string selection lines by selection memory block is determined according to the loss average information；And
It is write data into according to identified selecting sequence described by selection memory block.
2. according to the method described in claim 1, further including the change pair when the value of the loss average information is more than reference value The selecting sequence of the multiple string selection line.
3. according to the method described in claim 2, wherein, the selecting sequence includes：
First sequence, wherein selecting the multiple string selection line according to the multiple putting in order for string selection line；
Second sequence, wherein selecting the multiple string to select according to the reverse sequence of the multiple string selection line to put in order Line；And
Third sequence, wherein selecting the multiple string selection line to edge from center.
4. according to the method described in claim 1, wherein, the loss average information includes the erasing by selection memory block It counts.
5. a kind of storage system, including：
Non-volatile memory device comprising the memory block being connect with a plurality of string selection line；And
Memory Controller, construction in order to control the non-volatile memory device to select in a plurality of string selection line extremely It is one few,
Wherein, the Memory Controller is configured to be changed to a plurality of string according to the loss average information of the memory block The selecting sequence of selection line.
6. storage system according to claim 5, wherein the Memory Controller is configured to non-volatile deposit to described Storage device provides string selection line address corresponding with the selecting sequence.
7. storage system according to claim 6, wherein when the value of the loss average information is more than reference value, institute Memory Controller is stated to be configured to provide for not carrying out the string selection line of selection according to a plurality of the putting in order for string selection line Location.
8. storage system according to claim 6, wherein when the value of the loss average information is more than reference value, institute Memory Controller is stated to be configured to provide for carrying out selection string choosing according to the reverse sequence of a plurality of string selection line to put in order Select line address.
9. storage system according to claim 6, wherein when the value of the loss average information is less than reference value, institute The string that Memory Controller is configured to provide for sequentially carrying out selection according to a plurality of the putting in order for selection line of string is stated to select Select line address.
10. storage system according to claim 6, wherein the Memory Controller includes：
The average manager of loss, is configured to provide for the loss average information of the memory block；And
Address remapper is configured to adjust the string selection line address according to the loss average information.
11. storage system according to claim 5, wherein the Memory Controller is configured to described non-volatile Storage device provides the write instruction for including the loss average information.
12. storage system according to claim 11, wherein the non-volatile memory device is configured to write based on described Enter instruction come the string selection line address of remapping.
13. storage system according to claim 11, wherein said write instruction is configured to according to the average letter of the loss It ceases and changes.
14. storage system according to claim 11, wherein the memory block include formed in the vertical direction it is multiple Unit string.
15. a kind of non-volatile memory device, including：
Cell array comprising multiple memory blocks, each memory block are connect with a plurality of string selection line；
Page buffer is connect with the bit line of the cell array；
Decoder is connect by a plurality of string selection line with the cell array；And
Address remapper is configured to according to loss average information come the input address and to the decoder of remapping Address after remapping is provided,
Wherein, the described address device that remaps is configured to the input address that remaps in the following way：According to the damage Average information is consumed to adjust to by the selecting sequence of a plurality of string selection line of selection memory block.
16. a kind of method that the non-volatile memory device with more string storage units is programmed, the method includes：
Generate the first address, first address is writing data into a memory block of the non-volatile memory device；
Corresponding to the loss average information of memory block described in first address detected；
The second address is generated, with suitable to the selection of the string selection line of the memory block to adjust according to the loss average information Sequence；And
Data are written with the second address of the memory block.
17. further including according to the method for claim 16, receiving the logical address from host so that data are written.
18. according to the method for claim 17, further include the logical address is mapped to by flash translation layer (FTL) it is described First address.
19. according to the method for claim 16, further include by remap device will first address of cache to described in Second address.
20. further including according to the method for claim 16, increasing the average letter of the loss when erasing is by selection memory block Count value in breath.
21. further including according to the method for claim 16, changing when the value of the loss average information is more than reference value To the selecting sequence of the string selection line.
22. according to the method for claim 16, wherein the selecting sequence includes suitable according to the arrangement of the string selection line The reverse sequence of sequence come select it is described string selection line sequence.
23. according to the method for claim 16, wherein the selecting sequence includes selecting the string from center to edge The sequence of selection line.
24. according to the method for claim 16, wherein the selecting sequence includes according to the row about the string selection line Row sequence selects the sequence of the string selection line in z zag manners.
25. further including according to the method for claim 16, that second address is transmitted to institute using page write instruction State non-volatile memory device.
26. further including according to the method for claim 16, instructing second address being transmitted to institute using random writing State non-volatile memory device.
27. according to the method for claim 16, wherein generate second address the step of include：
By the count value of the loss average information compared with reference value；
Comparison result is based at least partially on to determine the selecting sequence to the string selection line of the memory block；And
Determining selecting sequence is based at least partially on to generate second address.
28. according to the method for claim 27, wherein generate second address the step of further include：
The column address part in second address is calculated to adjust the sequence of the string selection line；And
Generate second address for including the column address part.
29. according to the method for claim 27, wherein generate second address the step of further include：
The row address part in second address is calculated to adjust the sequence of the string selection line；And
Generate second address for including the row address part.
30. a kind of storage system, including：
Non-volatile memory device comprising the memory block being connect with a plurality of string selection line；
Memory Controller, construction in order to control the non-volatile memory device to select in a plurality of string selection line extremely It is one few；And
Address mapper is configured to be determined to a plurality of string selection line according to the loss average information of the memory block Selecting sequence.
31. storage system according to claim 30, wherein the Memory Controller is configured in the memory control The loss average information of the memory block is stored in device processed.
32. storage system according to claim 30, wherein the Memory Controller is configured to described non-volatile The loss average information of the memory block is stored in storage device.
33. storage system according to claim 32, wherein the Memory Controller is configured in the memory block The loss average information of the memory block is stored in virtual region.
34. storage system according to claim 32, wherein the Memory Controller is configured to described non-volatile The loss average information of the memory block is stored in other memory blocks of storage device.
35. storage system according to claim 30 further includes flash translation layer (FTL), it is configured to that logical address is made to be mapped to First physical address is to select the memory block.
36. storage system according to claim 35, wherein described address mapper is configured to according to the selecting sequence Generate the second physical address.
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