CN103337232B - Gate drive circuit - Google Patents
Gate drive circuit Download PDFInfo
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- CN103337232B CN103337232B CN201310197752.7A CN201310197752A CN103337232B CN 103337232 B CN103337232 B CN 103337232B CN 201310197752 A CN201310197752 A CN 201310197752A CN 103337232 B CN103337232 B CN 103337232B
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Abstract
The present invention relates to a kind of gate drive circuit, it comprises first input end, the second input end, the 3rd input end, output terminal, the first transistor, transistor seconds, third transistor, mu balanced circuit, electric capacity and pull-down circuit.The first end of the first transistor is coupled to first input end, and the control end of the first transistor is coupled to the second input end; The first end of transistor seconds is coupled to the 3rd input end, and the control end of transistor seconds is coupled to the second end of the first transistor, and the second end of transistor seconds is coupled to output terminal; The first end of third transistor is coupled to output terminal, and the second end of third transistor is coupled to earth terminal; Electric capacity is coupled between the control end of transistor seconds and output terminal; Pull-down circuit is coupled to output terminal and earth terminal.
Description
Technical field
The invention relates to a kind of gate drive circuit structure, and relate to gate drive circuit in a kind of panel especially.
Background technology
Along with the progress of science and technology, the demand of consumer to the resolution of liquid crystal display increases day by day, and is make high-resolution liquid crystal display, and industry gradually adopts the configuration mode of gate in panel (gate-in-panel) circuit.
For example, in the eight grades of circuit structures adopting two-way scanning type, its output signal provided as shown in Figure 1.Can be clear that very much that output signal Gout (n) overlaps to some extent with output signal Gout (n+2) by the 1st figure, specifically, if with reference between output signal Gout (n) and output signal Gout (n+1), the part of 3/4ths is then had to overlap nearly, the picture element that will cause like this glimmers, in addition, the power consumption of circuit also will improve.
As can be seen here, obviously still there is inconvenience and defect, and have much room for improvement in above-mentioned existing mode.In order to solve the problem, association area there's no one who doesn't or isn't seeks solution painstakingly, but does not develop suitable solution yet for a long time.
Summary of the invention
One object of content of the present invention is providing a kind of gate drive circuit, uses and improve output signal overlapping between gate drive circuit level, and the problem causing picture element flicker higher with the power consumption of circuit.
For reaching above-mentioned purpose, one technology aspect of content of the present invention is about a kind of gate drive circuit, this gate drive circuit comprises first input end, the second input end, the 3rd input end, output terminal, the first transistor, transistor seconds, third transistor, mu balanced circuit, electric capacity and pull-down circuit, furthermore, the first transistor comprises first end, control end and the second end, transistor seconds comprises first end, control end and the second end, and third transistor comprises first end, control end and the second end.In operation, first input end is in order to receive the first sweep signal; Second input end is in order to receive the first input signal; 3rd input end is in order to receive first frequency signal.In structure, the first end of the first transistor is electrically coupled to first input end, and the control end of the first transistor is electrically coupled to the second input end; The first end of transistor seconds is electrically coupled to the 3rd input end, and the control end of transistor seconds is electrically coupled to the second end of the first transistor, and the second end of transistor seconds is electrically coupled to output terminal; The first end of third transistor is electrically coupled to output terminal, and the second end of third transistor is electrically coupled to earth terminal; Mu balanced circuit is electrically coupled to the control end of transistor seconds, the control end of third transistor and earth terminal; Electric capacity is electrically coupled between the control end of transistor seconds and output terminal; Pull-down circuit is electrically coupled to output terminal and earth terminal.
According to one embodiment of the invention, aforementioned gate drive circuit more comprises four-input terminal and the 5th input end, and four-input terminal is in order to receive second frequency signal, and the 5th input end is in order to receive the first sweep signal.In addition, aforementioned pull-down circuit comprises the 4th transistor and the 5th transistor, and the 4th transistor comprises first end, control end and the second end, and the 5th transistor comprises first end, control end and the second end.In structure, the first end of the 4th transistor is electrically coupled to output terminal, and the control end of the 4th transistor is electrically coupled to four-input terminal; The first end of the 5th transistor is electrically coupled to the second end of the 4th transistor, and the control end of the 5th transistor is electrically coupled to the 5th input end, and the second end of the 5th transistor is electrically coupled to earth terminal.
According to another embodiment of the present invention, aforementioned gate drive circuit more comprises four-input terminal and the 5th input end, and four-input terminal is in order to receive second frequency signal, and the 5th input end is in order to receive the first sweep signal.In addition, aforementioned pull-down circuit comprises the 4th transistor and the 5th transistor, and the 4th transistor comprises first end, control end and the second end, and the 5th transistor comprises first end, control end and the second end.In structure, the first end of the 4th transistor is electrically coupled to output terminal, and the second end of the 4th transistor is electrically coupled to earth terminal; The first end of the 5th transistor is electrically coupled to four-input terminal, and the control end of the 5th transistor is electrically coupled to the 5th input end, and the second end of the 5th transistor is electrically coupled to the control end of the 4th transistor.
According to yet another embodiment of the invention, aforementioned second frequency signal falls behind first frequency signal four/one-period.
According to further embodiment of this invention, scan period in a forward, the first sweep signal is a logic high calibration signal.
According to another embodiment of the present invention, aforementioned gate drive circuit more comprises the 6th input end, the 7th input end and the 6th transistor, 6th input end is in order to receive the second sweep signal, 7th input end is in order to receive the second input signal, and the 6th transistor comprises first end, control end and the second end.In structure, the first end of the 6th transistor is electrically coupled to the 6th input end, and the control end of the 6th transistor is electrically coupled to the 7th input end, and the second end of the 6th transistor is electrically coupled to the control end of transistor seconds.
According to yet another embodiment of the invention, aforementioned gate drive circuit more comprises the 8th input end and the 9th input end, and the 8th input end is in order to receive the 3rd frequency signal, and the 9th input end is in order to receive the second sweep signal.Aforementioned pull-down circuit comprises the 7th transistor and the 8th transistor, and the 7th transistor comprises first end, control end and the second end, and the 8th transistor comprises first end, control end and the second end.In structure, the first end of the 7th transistor is electrically coupled to output terminal, and the control end of the 7th transistor is electrically coupled to the 8th input end; The first end of the 8th transistor is electrically coupled to the second end of the 7th transistor, and the control end of the 8th transistor is electrically coupled to the 9th input end, and the second end of the 8th transistor is electrically coupled to earth terminal.
According to further embodiment of this invention, aforementioned gate drive circuit more comprises the 8th input end and the 9th input end, and the 8th input end is in order to receive the 3rd frequency signal, and the 9th input end is in order to receive the second sweep signal.Aforementioned pull-down circuit comprises the 7th transistor and the 8th transistor, and the 7th transistor comprises first end, control end and the second end, and the 8th transistor comprises first end, control end and the second end.In structure, the first end of the 7th transistor is electrically coupled to output terminal, and the second end of the 7th transistor is electrically coupled to earth terminal; The first end of the 8th transistor is electrically coupled to the 8th input end, and the control end of the 8th transistor is electrically coupled to the 9th input end, and the second end of the 8th transistor is electrically coupled to the control end of the 7th transistor.
According to another embodiment of the present invention, aforementioned 3rd frequency signal falls behind first frequency signal four/one-period.
According to yet another embodiment of the invention, oppositely scan period in one, the second sweep signal is logic high calibration signal.
Accompanying drawing explanation
For above and other objects of the present invention, feature, advantage and embodiment can be become apparent, being described as follows of institute's accompanying drawings:
Fig. 1 is the operation waveform schematic diagram of the gate drive circuit of a kind of known techniques illustrated according to one embodiment of the invention.
Fig. 2 is the schematic diagram of a kind of gate drive circuit illustrated according to another embodiment of the present invention.
Fig. 3 is the operation waveform schematic diagram of a kind of gate drive circuit illustrated according to yet another embodiment of the invention.
Fig. 4 illustrates a kind of gate drive circuit schematic diagram according to further embodiment of this invention.
Fig. 5 is the operation waveform schematic diagram of a kind of gate drive circuit illustrated according to another embodiment of the present invention.
120: mu balanced circuit
140: pull-down circuit
160: pull-down circuit
240: pull-down circuit
260: pull-down circuit
IN1: first input end
IN2: the second input end
IN3: the three input end
IN4: the four-input terminal
IN5: the five input end
IN6: the six input end
IN7: the seven input end
IN8: the eight input end
IN9: the nine input end
IN10: the ten input end
IN11: the ten one input end
Vfwd: the first sweep signal
Vbwd: the second sweep signal
Gout (n): the first input signal
Gout (n+2): output signal
T1: the first transistor
T2: transistor seconds
T3: third transistor
T4: the four transistor
T5: the five transistor
T6: the six transistor
T7: the seven transistor
T8: the eight transistor
T9: the nine transistor
T10: the ten transistor
C1: the first electric capacity
C2: the second electric capacity
OUT: output terminal
Gout (n+4): the second input signal
CK1O: the three frequency signal
CK2O: first frequency signal
CK1BO: second frequency signal
VGL: ground signalling
P: node
Q: node.
Embodiment
First, please refer to Fig. 1, it is the operation waveform schematic diagram of the gate drive circuit of a kind of known techniques illustrated according to one embodiment of the invention.As shown in the figure, n-th grade in known gate drive circuit overlaps with Gout (n+1) to some extent with the output signal Gout (n) of (n+1)th grade of circuit, its overlapping part accounts for 3/4ths of output signal nearly, if be a chronomere with time t1 to t2, then above-mentioned overlapping part account for three units.The problem of overlapping is outputed signal between gate drive circuit level for solution gate drive circuit, the embodiment of the present invention proposes a kind of circuit structure of innovation, to improving the picture element flicker phenomenon higher with the power consumption of circuit, as shown in Figure 2, it is the schematic diagram illustrating a kind of gate drive circuit according to one embodiment of the invention to this circuit structure.
As shown in Figure 2, the gate drive circuit of the embodiment of the present invention comprises first input end IN1, the second input end IN2, the 3rd input end IN3, output terminal OUT, the first transistor T1, transistor seconds T2, third transistor T3, mu balanced circuit 120, first electric capacity C1 and pull-down circuit 140, furthermore, each self-contained first end of the first transistor T1, transistor seconds T2 and third transistor T3, control end and the second end.
In operation, first input end IN1 is in order to receive the first sweep signal Vfwd; Second input end IN2 is in order to receive the first input signal Gout (n); 3rd input end IN3 is in order to receive first frequency signal CK2O; Output terminal OUT is in order to export an output signal Gout (n+2).
In structure, the first end of the first transistor T1 is electrically coupled to first input end IN1, and the control end of the first transistor T1 is electrically coupled to the second input end IN2; The first end of transistor seconds T2 is electrically coupled to the 3rd input end IN3, and the control end of transistor seconds T2 is electrically coupled to second end of the first transistor T1, and second end of transistor seconds T2 is electrically coupled to output terminal OUT; Mu balanced circuit 120 at least comprises the 11 input end IN11,11 input end IN11 is in order to receive ground signalling, or mu balanced circuit 120 is coupled to earth terminal through the 11 input end IN11, in addition, mu balanced circuit 120 is electrically coupled to the control end of transistor seconds T2 and the control end of third transistor T3; The first end of third transistor T3 is electrically coupled to output terminal OUT, and second end of third transistor T3 is electrically coupled to earth terminal through mu balanced circuit 120; First electric capacity C1 is electrically coupled between the control end of transistor seconds T2 and output terminal OUT; Pull-down circuit 140 is electrically coupled to output terminal OUT and is electrically coupled to earth terminal through mu balanced circuit 120.
In time realizing of the present invention, above-mentioned transistor can be MOS field-effect transistor (metal-oxide-semiconductorfield-effecttransistor, MOSFET), and the first end of above-mentioned transistor be optionally drain or source electrode one of them, second end of above-mentioned transistor can be correspondingly drain or source electrode wherein another, and the control end of above-mentioned transistor can be gate.But the present invention is not limited to this, haveing the knack of this those skilled in the art optionally ought adopt suitable electronic package according to actual demand.
Integrated operation for the gate drive circuit making the embodiment of the present invention is easier to understand, and please with reference to Fig. 2 and Fig. 3, wherein Fig. 3 is the operation waveform schematic diagram of a kind of gate drive circuit illustrated according to yet another embodiment of the invention.First, illustrate that signal is in the situation during forward scans illustratively, now, the first sweep signal Vfwd is high levels signal.At this, for the n-th+2 grades circuit of the gate drive circuit of the embodiment of the present invention, during time t1 to t3, the first input signal Gout (n) that second input end IN2 of the n-th+2 grades circuit is received by the output terminal of front n-th grade of circuit is high levels signal, now, the first transistor T1 opens, and the first sweep signal Vfwd inputted by first input end IN1 carries out pre-charged to the first electric capacity C1, and the voltage of Q point promotes gradually.
When time t3, first input signal Gout (n) is converted to low level signal, the first transistor T1 closes, due to the electric discharge of the first electric capacity C1, transistor seconds T2 is opened, now first frequency signal CK2O is high levels signal, first frequency signal CK2O is provided and gives output terminal OUT, and exports output signal Gout (n+2) by output terminal OUT.
During time t3 to t7,3rd input end IN3 continuous reception first frequency signal CK2O, originally can continue output one by output terminal OUT and output signal Gout (n+2), but, when time t5, one second frequency signal CK1BO is converted to high levels signal, mat makes pull-down circuit 140 open, now, and output terminal OUT ground connection, therefore, output terminal OUT can not export aforementioned output signals Gout (n+2).
Compared to the known techniques shown in Fig. 1, please refer to Fig. 3, the part that overlaps between the output signal Gout (n) of n-th grade and (n+1)th grade circuit in the gate drive circuit of the employing embodiment of the present invention and Gout (n+1) is less, calculate according to the unit being same as the known techniques that the 1st figure is, then above-mentioned overlapping part Jin Zhanyige unit.
Therefore, compared to known techniques, the be improved output signal of known gate drive circuit of the gate drive circuit structure of the embodiment of the present invention overlaps, and causes picture element to glimmer the problem higher with the power consumption of circuit.Furthermore, compared to known techniques, adopt the gate drive circuit structure of the embodiment of the present invention to be able to the quality of improving picture, and saved the power consumption of 2/3rds nearly.
Specifically, please refer to Fig. 2, on a kind of Circnit Layout of the embodiment of the present invention, gate drive circuit more comprises four-input terminal IN4 and the 5th input end IN5.Four-input terminal IN4 is in order to receive second frequency signal CK1BO, and the 5th input end IN5 is in order to receive the first sweep signal Vfwd.Specifically, aforementioned pull-down circuit 140 comprises the 4th transistor T4 and the 5th transistor T5, the 4th transistor T4 and each self-contained first end of the 5th transistor T5, control end and the second end.In structure, the first end of the 4th transistor T4 is electrically coupled to output terminal OUT, and the control end of the 4th transistor T4 is electrically coupled to four-input terminal IN4; The first end of the 5th transistor T5 is electrically coupled to second end of the 4th transistor T4, and the control end of the 5th transistor T5 is electrically coupled to the 5th input end IN5, and second end of the 5th transistor T5 is electrically coupled to earth terminal through mu balanced circuit 120.
In the present embodiment, please with reference to Fig. 2 and Fig. 3.At this, situation during the mode of operation of gate drive circuit scans similar in appearance to above-mentioned forward, first, period is scanned in forward, first sweep signal Vfwd is high levels signal, therefore, 5th transistor T5 is in opening, furthermore, when time t5, the second frequency signal CK1BO inputting four-input terminal IN4 is converted to high levels signal, now, the 4th transistor T4 is unlocked, thus output terminal OUT is through the 4th transistor T4 and the 5th transistor T5 ground connection, therefore, output terminal OUT can not export aforementioned output signals Gout (n+2).In other words, second frequency signal CK1BO falls behind first frequency signal CK2O tetra-/one-period as shown in Figure 3, therefore, output terminal OUT is given to continue after four/one-period as output signal Gout (n+2) when first frequency signal CK2O provides, second frequency signal CK1BO activation and open pull-down circuit 140, thus draw except first frequency signal CK2O, mat makes output terminal OUT can not export aforementioned output signals Gout (n+2), and the output signal actually improving gate in known panel overlaps, cause the problem that picture element flicker is higher with the power consumption of circuit.
In addition, on the another kind of Circnit Layout of the embodiment of the present invention, please refer to Fig. 4, gate drive circuit more comprises pull-down circuit 240, four-input terminal IN4 and the 5th input end IN5, four-input terminal IN4 is in order to receive second frequency signal CK1BO, and the 5th input end IN5 is in order to receive the first sweep signal Vfwd.Specifically, aforementioned pull-down circuit 240 comprises the 4th transistor T4 and the 5th transistor T5, the 4th transistor T4 and each self-contained first end of the 5th transistor T5, control end and the second end.In structure, the first end of the 4th transistor T4 is electrically coupled to output terminal OUT, and second end of the 4th transistor T4 is electrically coupled to earth terminal through mu balanced circuit 120; The first end of the 5th transistor T5 is electrically coupled to four-input terminal IN4, and the control end of the 5th transistor T5 is electrically coupled to the 5th input end IN5, and second end of the 5th transistor T5 is electrically coupled to the control end of the 4th transistor T4.
In the present embodiment, please with reference to Fig. 3 and Fig. 4.At this, situation during the mode of operation of gate drive circuit scans similar in appearance to above-mentioned forward, first, period is scanned in forward, first sweep signal Vfwd is high levels signal, therefore, 5th transistor T5 is in opening, furthermore, when time t5, the second frequency signal CK1BO inputting four-input terminal IN4 is converted to high levels signal, now, 4th transistor T4 is unlocked through the 5th transistor T5, thus output terminal OUT is through the 4th transistor T4 ground connection, therefore, output terminal OUT can not export aforementioned output signals Gout (n+2), in other words, first frequency signal CK2O tetra-/one-period is fallen behind by the 3rd figure known second frequency signal CK1BO, therefore, output terminal OUT is given to continue after four/one-period as output signal Gout (n+2) when first frequency signal CK2O provides, second frequency signal CK1BO activation and open pull-down circuit 240, thus draw except first frequency signal CK2O, mat makes output terminal OUT can not export aforementioned output signals Gout (n+2), and the output signal actually improving gate in known panel overlaps, cause the problem that picture element flicker is higher with the power consumption of circuit.
Then, illustrate that signal is in the situation during oppositely scanning illustratively, please refer to Fig. 2, gate drive circuit more comprises pull-down circuit 160, the 6th input end IN6, the 7th input end IN7 and the 6th transistor T6,6th input end IN6 is in order to receive the second sweep signal Vbwd, 7th input end IN7 is in order to receive the second input signal Gout (n+4), and the 6th transistor T6 comprises first end, control end and the second end.In structure, the first end of the 6th transistor T6 is electrically coupled to the 6th input end IN6, and the control end of the 6th transistor T6 is electrically coupled to the 7th input end IN7, and second end of the 6th transistor T6 is electrically coupled to the control end of transistor seconds T2.
Integrated operation for the gate drive circuit making the embodiment of the present invention is easier to understand, and please with reference to Fig. 2 and Fig. 5, wherein Fig. 5 is the operation waveform schematic diagram of a kind of gate drive circuit illustrated according to yet another embodiment of the invention.First, during signal is in and oppositely scans, the second sweep signal Vbwd is high levels signal.During time t3 to t5, at this, for the n-th+2 grades circuit of gate drive circuit, the second input signal Gout (n+4) that its 7th input end IN7 is received by the output terminal of the n-th+4 grades circuit of gate drive circuit is high levels signal, now, 6th transistor T6 opens, and the second sweep signal Vbwd inputted by the 6th input end IN6 carries out pre-charged to the first electric capacity C1, and the voltage of Q point promotes gradually.
When time t5, second input signal Gout (n+4) is converted to low level signal, 6th transistor T6 closes, due to the electric discharge of the first electric capacity C1, transistor seconds T2 is opened, now first frequency signal CK2O is high levels signal, first frequency signal CK2O is provided and gives output terminal OUT, and exports output signal Gout (n+2) by output terminal OUT.
During time t5 to t9,3rd input end IN3 continuous reception first frequency signal CK2O, originally also can continue output one by output terminal OUT outputs signal Gout (n+2), but, when time t7, one the 3rd frequency signal CK1O is converted to high levels signal, pull-down circuit 160 is opened, now, and output terminal OUT ground connection, therefore, output terminal OUT can not export aforementioned output signals Gout (n+2).
As shown in Figure 5, n-th grade in the gate drive circuit of the embodiment of the present invention is adopted not overlap with Gout (n+2) with the output signal Gout (n) of the n-th+2 grades circuit, therefore, can obviously learn compared to known techniques, the be improved output signal of gate drive circuit of the gate drive circuit structure of the embodiment of the present invention overlaps, and causes picture element to glimmer the problem higher with the power consumption of circuit.
Specifically, please refer to Fig. 2, on a kind of Circnit Layout of the embodiment of the present invention, gate drive circuit more comprises pull-down circuit 160, the 8th input end IN8 and the 9th input end IN9,8th input end IN8 is in order to receive the 3rd frequency signal CK1O, and the 9th input end IN9 is in order to receive the second sweep signal Vbwd.Aforementioned pull-down circuit 160 comprises the 7th transistor T7 and the 8th transistor T8, the 7th transistor T7 and each self-contained first end of the 8th transistor T8, control end and the second end.In structure, the first end of the 7th transistor T7 is electrically coupled to output terminal OUT, and the control end of the 7th transistor T7 is electrically coupled to the 8th input end IN8; The first end of the 8th transistor T8 is electrically coupled to second end of the 7th transistor T7, and the control end of the 8th transistor T8 is electrically coupled to the 9th input end IN9, and second end of the 8th transistor T8 is electrically coupled to earth terminal through mu balanced circuit 120.
In the present embodiment, please with reference to Fig. 2 and Fig. 5.At this, the mode of operation of gate drive circuit similar in appearance to above-mentioned oppositely scan during situation, first, in oppositely scanning period, second sweep signal Vbwd is high levels signal, therefore, 8th transistor T8 is in opening, furthermore, when time t7, the 3rd frequency signal CK1O inputting the 8th input end IN8 is converted to high levels signal, now, 7th transistor T7 is unlocked, thus output terminal OUT is through the 7th transistor T7 and the 8th transistor T8 ground connection, therefore, output terminal can not export aforementioned output signals Gout (n+2), in other words, can find out that the 3rd frequency signal CK1O falls behind first frequency signal CK2O tetra-/one-period by the 5th figure, therefore, output terminal OUT is given to continue after four/one-period as output signal Gout (n+2) when first frequency signal CK2O provides, 3rd frequency signal CK1O activation and open pull-down circuit 160, thus draw except first frequency signal CK2O, mat makes output terminal OUT can not export aforementioned output signals Gout (n+2), and overlapping can be outputed signal between the actual gate drive circuit level improving gate in panel, cause the problem that picture element flicker is higher with the power consumption of circuit.
In addition, on the another kind of Circnit Layout of the embodiment of the present invention, please refer to the 4th figure, gate drive circuit more comprises pull-down circuit 260, the 8th input end IN8 and the 9th input end IN9,8th input end IN8 is in order to receive the 3rd frequency signal CK1O, and the 9th input end IN9 is in order to receive the second sweep signal Vbwd.Aforementioned pull-down circuit 260 comprises the 7th transistor T7 and the 8th transistor T8, the 7th transistor T7 and each self-contained first end of the 8th transistor T8, control end and the second end.In structure, the first end of the 7th transistor T7 is electrically coupled to output terminal OUT, and second end of the 7th transistor T7 is electrically coupled to earth terminal through mu balanced circuit 120; The first end of the 8th transistor T8 is electrically coupled to the 8th input end IN8, and the control end of the 8th transistor T8 is electrically coupled to the 9th input end IN9, and second end of the 8th transistor T8 is electrically coupled to the control end of the 7th transistor T7.
In the present embodiment, please with reference to Fig. 4 and Fig. 5.At this, the mode of operation of gate drive circuit similar in appearance to above-mentioned oppositely scan during situation, first, in oppositely scanning period, second sweep signal Vbwd is high levels signal, therefore, 8th transistor T8 is in opening, furthermore, when time t7, the 3rd frequency signal CK1O inputting the 8th input end IN8 is converted to high levels signal, now, 7th transistor T7 is unlocked through the 8th transistor T8, thus output terminal OUT is through the 7th transistor T7 ground connection, therefore, output terminal OUT can not export aforementioned output signals Gout (n+2).In other words, 3rd frequency signal CK1O falls behind first frequency signal CK2O tetra-/one-period as seen from Figure 5, therefore, output terminal OUT is given to continue after four/one-period as output signal Gout (n+2) when first frequency signal CK2O provides, 3rd frequency signal CK1O activation and open pull-down circuit 260, thus draw except first frequency signal CK2O, mat makes output terminal OUT can not export aforementioned output signals Gout (n+2), and overlapping can be outputed signal between the actual gate drive circuit level improving gate in panel, cause the problem that picture element flicker is higher with the power consumption of circuit.
In addition, mu balanced circuit 120 as shown in Fig. 2 and Fig. 4, it comprises the tenth input end IN10, the 11 input end IN11, the 9th transistor T9, the tenth transistor T10 and the second electric capacity C2, tenth input end IN10 in order to receive first frequency signal CK2O and the 11 input end IN11 in order to receive ground signalling VGL, furthermore, the 9th transistor T9 and each self-contained first end of the tenth transistor T10, control end and the second end.In structure, the first end of the 9th transistor T9 is electrically coupled to the control end of third transistor T3, the control end of the 9th transistor T9 is electrically coupled to the control end of transistor seconds T2, and second end of the 9th transistor T9 is electrically coupled to earth terminal through the 11 input end IN11.In addition, the first end of the tenth transistor T10 is electrically coupled to the control end of transistor seconds T2, the control end of the tenth transistor T10 is electrically coupled to the control end of third transistor T3, and second end of the tenth transistor T10 is electrically coupled to earth terminal through the 11 input end IN11.In addition, the second electric capacity C2 is electrically coupled between the control end of the tenth input end IN10 and third transistor T3.
From the invention described above embodiment, application the present invention has following advantages.The embodiment of the present invention, by providing a kind of gate drive circuit, is used the output signal improving gate in known panel and is overlapped, and the problem causing picture element flicker higher with the power consumption of circuit.Furthermore, compared to known techniques, adopt the gate drive circuit structure of the embodiment of the present invention to be able to the quality of improving picture, and saved the power consumption of 2/3rds nearly.
Claims (12)
1. a gate drive circuit, is characterized in that comprising:
One first input end, in order to receive one first sweep signal;
One second input end, in order to receive one first input signal;
One the 3rd input end, in order to receive a first frequency signal;
One output terminal;
One the first transistor, comprises:
One first end, is electrically coupled to this first input end;
One control end, is electrically coupled to this second input end; And
One second end;
One transistor seconds, comprises:
One first end, is electrically coupled to the 3rd input end;
One control end, is electrically coupled to this second end of this first transistor; And
One second end, is electrically coupled to this output terminal;
One third transistor, comprises:
One first end, is electrically coupled to this output terminal;
One control end; And
One second end, is electrically coupled to an earth terminal;
One mu balanced circuit, this mu balanced circuit at least comprises the 11 input end, 11 input end is in order to receive ground signalling, or mu balanced circuit is coupled to earth terminal through the 11 input end IN11, and this mu balanced circuit is electrically coupled to the control end of transistor seconds and the control end of third transistor; The first end of third transistor is electrically coupled to output terminal, and the second end of third transistor is electrically coupled to earth terminal through mu balanced circuit; First electric capacity is electrically coupled between the control end of transistor seconds and output terminal; Pull-down circuit is electrically coupled to output terminal OUT and is electrically coupled to earth terminal through mu balanced circuit;
More comprise:
One four-input terminal, in order to receive a second frequency signal; And
One the 5th input end, in order to receive this first sweep signal;
Wherein this pull-down circuit comprises:
One the 4th transistor, comprises:
One first end, is electrically coupled to this output terminal;
One control end, is electrically coupled to this four-input terminal; And
One second end; And
One the 5th transistor, comprises:
One first end, is electrically coupled to this second end of the 4th transistor;
One control end, is electrically coupled to the 5th input end; And
One second end, is electrically coupled to this earth terminal;
Wherein this second frequency signal falls behind this first frequency signal four/one-period;
Wherein scan period in a forward, this first sweep signal is a logic high calibration signal.
2. gate drive circuit according to claim 1, is characterized in that more comprising:
One the 6th input end, in order to receive one second sweep signal;
One the 7th input end, in order to receive one second input signal; And
One the 6th transistor, comprises:
One first end, is electrically coupled to the 6th input end;
One control end, is electrically coupled to the 7th input end; And
One second end, is electrically coupled to this control end of this transistor seconds.
3. gate drive circuit according to claim 2, is characterized in that more comprising:
One the 8th input end, in order to receive one the 3rd frequency signal; And
One the 9th input end, in order to receive one second sweep signal;
Wherein this pull-down circuit comprises:
One the 7th transistor, comprises:
One first end, is electrically coupled to this output terminal;
One control end, is electrically coupled to the 8th input end; And
One second end; And
One the 8th transistor, comprises:
One first end, is electrically coupled to this second end of the 7th transistor;
One control end, is electrically coupled to the 9th input end; And
One second end, is electrically coupled to this earth terminal.
4. gate drive circuit according to claim 2, is characterized in that more comprising:
One the 8th input end, in order to receive one the 3rd frequency signal; And
One the 9th input end, in order to receive one second sweep signal;
Wherein this pull-down circuit comprises:
One the 7th transistor, comprises:
One first end, is electrically coupled to this output terminal;
One control end; And
One second end, is electrically coupled to this earth terminal; And
One the 8th transistor, comprises:
One first end, is electrically coupled to the 8th input end;
One control end, is electrically coupled to the 9th input end; And
One second end, is electrically coupled to this control end of the 7th transistor.
5. the gate drive circuit according to claim 3 or 4, is characterized in that: wherein the 3rd frequency signal falls behind this first frequency signal four/one-period.
6. the gate drive circuit according to claim 3 or 4, is characterized in that: wherein oppositely scan period in one, this second sweep signal is logic high calibration signal.
7. a gate drive circuit, is characterized in that comprising:
One first input end, in order to receive one first sweep signal;
One second input end, in order to receive one first input signal;
One the 3rd input end, in order to receive a first frequency signal;
One output terminal;
One the first transistor, comprises:
One first end, is electrically coupled to this first input end;
One control end, is electrically coupled to this second input end; And
One second end;
One transistor seconds, comprises:
One first end, is electrically coupled to the 3rd input end;
One control end, is electrically coupled to this second end of this first transistor; And
One second end, is electrically coupled to this output terminal;
One third transistor, comprises:
One first end, is electrically coupled to this output terminal;
One control end; And
One second end, is electrically coupled to an earth terminal;
One mu balanced circuit, this mu balanced circuit at least comprises the 11 input end, 11 input end is in order to receive ground signalling, or mu balanced circuit is coupled to earth terminal through the 11 input end IN11, and this mu balanced circuit is electrically coupled to the control end of transistor seconds and the control end of third transistor; The first end of third transistor is electrically coupled to output terminal, and the second end of third transistor is electrically coupled to earth terminal through mu balanced circuit; First electric capacity is electrically coupled between the control end of transistor seconds and output terminal; Pull-down circuit is electrically coupled to output terminal OUT and is electrically coupled to earth terminal through mu balanced circuit;
More comprise:
One four-input terminal, in order to receive a second frequency signal; And
One the 5th input end, in order to receive this first sweep signal;
Wherein this pull-down circuit comprises:
One the 4th transistor, comprises:
One first end, is electrically coupled to this output terminal;
One control end; And
One second end, is electrically coupled to this earth terminal; And
One the 5th transistor, comprises:
One first end, is electrically coupled to this four-input terminal;
One control end, is electrically coupled to the 5th input end; And
One second end, is electrically coupled to this control end of the 4th transistor;
Wherein this second frequency signal falls behind this first frequency signal four/one-period;
Wherein scan period in a forward, this first sweep signal is a logic high calibration signal.
8. gate drive circuit according to claim 7, is characterized in that more comprising:
One the 6th input end, in order to receive one second sweep signal;
One the 7th input end, in order to receive one second input signal; And
One the 6th transistor, comprises:
One first end, is electrically coupled to the 6th input end;
One control end, is electrically coupled to the 7th input end; And
One second end, is electrically coupled to this control end of this transistor seconds.
9. gate drive circuit according to claim 8, is characterized in that more comprising:
One the 8th input end, in order to receive one the 3rd frequency signal; And
One the 9th input end, in order to receive one second sweep signal;
Wherein this pull-down circuit comprises:
One the 7th transistor, comprises:
One first end, is electrically coupled to this output terminal;
One control end, is electrically coupled to the 8th input end; And
One second end; And
One the 8th transistor, comprises:
One first end, is electrically coupled to this second end of the 7th transistor;
One control end, is electrically coupled to the 9th input end; And
One second end, is electrically coupled to this earth terminal.
10. gate drive circuit according to claim 8, is characterized in that more comprising:
One the 8th input end, in order to receive one the 3rd frequency signal; And
One the 9th input end, in order to receive one second sweep signal;
Wherein this pull-down circuit comprises:
One the 7th transistor, comprises:
One first end, is electrically coupled to this output terminal;
One control end; And
One second end, is electrically coupled to this earth terminal; And
One the 8th transistor, comprises:
One first end, is electrically coupled to the 8th input end;
One control end, is electrically coupled to the 9th input end; And
One second end, is electrically coupled to this control end of the 7th transistor.
11. gate drive circuits according to claim 9 or 10, is characterized in that: wherein the 3rd frequency signal falls behind this first frequency signal four/one-period.
12. gate drive circuits according to claim 9 or 10, is characterized in that: wherein oppositely scan period in one, this second sweep signal is logic high calibration signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310197752.7A CN103337232B (en) | 2013-05-25 | 2013-05-25 | Gate drive circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310197752.7A CN103337232B (en) | 2013-05-25 | 2013-05-25 | Gate drive circuit |
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| Publication Number | Publication Date |
|---|---|
| CN103337232A CN103337232A (en) | 2013-10-02 |
| CN103337232B true CN103337232B (en) | 2015-11-18 |
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| CN201310197752.7A Expired - Fee Related CN103337232B (en) | 2013-05-25 | 2013-05-25 | Gate drive circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103839510A (en) * | 2014-03-26 | 2014-06-04 | 华映视讯（吴江）有限公司 | Gate driving circuit |
| JP6521794B2 (en) | 2014-09-03 | 2019-05-29 | 株式会社半導体エネルギー研究所 | Semiconductor device and electronic device |
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| Publication number | Publication date |
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| CN103337232A (en) | 2013-10-02 |
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Effective date of registration: 20170808 Address after: 1#, building third, fourth, 6 West Road, Mawei West Road, Mawei District, Fujian, Fuzhou Co-patentee after: Chunghwa Picture Tubes Ltd. Patentee after: CPT DISPLAY TECHNOLOGY (SHENZHEN)CO., LTD. Address before: 350015, Xingye Road, Mawei Science Park, Fujian, Fuzhou 1, China Co-patentee before: Chunghwa Picture Tubes Ltd. Patentee before: Fujian Huaying Display Technology Co., Ltd. |
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Granted publication date: 20151118 Termination date: 20200525 |