CN103336750A

CN103336750A - Addressing and storage unit integral dual-port storage controller

Info

Publication number: CN103336750A
Application number: CN2013102884939A
Authority: CN
Inventors: 蔡启仲; 潘绍明; 李克俭; 孙培燕; 黄仕林; 李刚; 陆伟男
Original assignee: Guangxi University of Science and Technology
Current assignee: Guangxi University of Science and Technology
Priority date: 2013-07-10
Filing date: 2013-07-10
Publication date: 2013-10-02
Anticipated expiration: 2033-07-10
Also published as: CN103336750B

Abstract

An addressing and storage cell integral dual-port storage controller comprises a dual-port RAM storage unit and two independent read-write port controllers. Each read-write port controller comprises a command deposit and address temporary storage control module, a combinational logic circuit module, a pulse distributor, a data transmission control module, an address channel control module and a read-write arbitration circuit module. An FPGA design hard connecting circuit is applied to the storage controller, and the arbitration function of a main/auxiliary selecting mode is adopted by two read-write ports. The access function of an ordinary dual-port storage is achieved. Further, the storage controller of each read-write port reads in commands, addresses or immediate operands needing to be written in and then independently completes immediate operand addressing, direct addressing, indirect addressing, base address addressing and modified address addressing and the reading or the writing of the storage unit or data transmission among storage units according to demands under the control of internal timing sequence pulses, and parallel processing of operations that the integral dual-port storage controller carries out reading operations and writing operations and other instruction sequences are executed by a microprocessor is achieved.

Description

The integrated dual-port memory controller of addressing and storage unit

Technical field

The present invention relates to the integrated dual-port memory controller of a kind of addressing and storage unit, relate in particular to a kind of operation control circuit and sequential control thereof based on the hardwired addressing of FPGA parallel work-flow circuit and the integrated dual-port memory controller of storage unit.

Background technology

Existing dual-ported memory (RAM) is to have fully independently data line of two covers at a storer, address wire and read-write control line, every suit data line, address wire and read-write control line are formed independently reading-writing port, the characteristics of two-port RAM maximum are the data sharings of storage, allow two independently microprocessor system storage unit access asynchronously simultaneously, two reading-writing port are under situation about same address storaging unit not being conducted interviews, each independently reading-writing port have reading of normal memory, write operation function, namely according to the address value of microprocessor internal or outside address bus, directly register or the storage unit of this address are carried out read-write operation, its function is more single; Adding other comparatively complicated addressing modes such as indexed addressing for indirect addressing, plot, also relate to the calculating of address, the processes such as transmission of address date, all is to be finished by microprocessor; Storage unit in dual-ported memory data transmission each other, need transfer realization storage unit data transmission each other in the some registers by microprocessor internal, namely need two transfer instructions can finish the data transmission of the some storage unit in the storer to another storage unit; The addressing process of storer and register, the process of the data transmission each other of the storage unit in the storer will take the instruction time of microprocessor, increase the burden of microprocessor execution of program instructions stream, be unfavorable for improving the speed of execution command sequence.

Summary of the invention

The object of the present invention is to provide a kind of characteristics based on the FPGA parallel processing, use the hard control circuit that connects of FPGA design, and addressing and the integrated dual-port memory controller of storage unit of sequential control circuit composition, the controller of a reading-writing port of the integrated dual-port memory controller of this addressing and storage unit is chosen by system, read in order from system bus, what the address maybe needed to write counts immediately, under the control of the time sequential pulse of internal pulses divider, independently finish the addressing of order defined, the operating function of address computation and read-write, can realize storage unit data transmission each other, in the process of the write operation order of execute store, do not need microprocessor that addressing process and write operation are carried out any processing again; In the process of carrying out the read operation order, under inner time sequential pulse effect, independently finish the addressing of storage unit, system requires addressing and the integrated dual-port memory controller of storage unit sent according to sequential reads (RD) signal, the data of this storage unit are sent to the data bus of system, fully used the parallel processing function of FPGA, realize the parallel processing of read write command operation and system program implementation, to solve the above-mentioned technical matters that above-mentioned prior art exists.

The technical scheme that solves the problems of the technologies described above is: the integrated dual-port memory controller of a kind of addressing and storage unit, comprise two-port RAM storage unit and two fully independently reading-writing port A and reading-writing port B, the basic structure of described two-port RAM storage unit is identical with common double port ram storer; It is characterized in that: be provided with as indirect addressing and plot in the described two-port RAM storage unit and add the storage unit R that indexed addressing is used ₀-R ₃₁The addressing of described reading-writing port A and reading-writing port B is identical with circuit structure with the integrated sequential control method of storage unit, the steering logic that is master/slave selection is opposite, namely working as master/slave selection line is " 0 ", and reading-writing port A is master port, and reading-writing port B is from the control port; When master/slave selection line is " 1 ", then reading-writing port A is that reading-writing port B is master port from the control port;

The control circuit of described reading-writing port A comprises command register and the temporary control module a in address, combinational logic circuit module a, pulsqe distributor a, Data Transmission Controlling module a, address tunnel control module a and read-write arbitration circuit module a realize the control function of the reading-writing port A of described two-port RAM storage unit;

The control circuit of described reading-writing port B comprises command register and the temporary control module b in address, combinational logic circuit module b, pulsqe distributor b, Data Transmission Controlling module b, address tunnel control module b and read-write arbitration circuit module b realize the control function of the reading-writing port B of described two-port RAM storage unit;

Control module a is kept in described two-port RAM storage unit and command register and address, Data Transmission Controlling module a, address tunnel control module a, read-write arbitration circuit module a, control module b is kept in command register and address, Data Transmission Controlling module b, address tunnel control module b, read-write arbitration circuit module b connects;

The temporary control module a in described command register and address also with combinational logic circuit module a, pulsqe distributor a, Data Transmission Controlling module a, address tunnel control module a connects;

Described combinational logic circuit module a also with pulsqe distributor a, Data Transmission Controlling module a, address tunnel control module a connects;

Described pulsqe distributor a also with Data Transmission Controlling module a, address tunnel control module a, read-write arbitration circuit module a connects;

Described Data Transmission Controlling module a also with address tunnel control module a, read-write arbitration circuit module a connects;

Described address tunnel control module a also is connected with read-write arbitration circuit module b;

Described read-write arbitration circuit module a also with read-write arbitration circuit module b, address tunnel control module b connects;

The temporary control module a in described command register and address is when CS_1 is " 0 ", under the effect of the WR_1 of system signal, store instruction codes and decoding, the address value of indirect memory addressing and plot+indexed addressing memory unit address value, side-play amount and directly address is also exported; If also have the address value of the 2nd directly address, then under the effect of second WR_1 signal of system, store the address value of the 2nd directly address and exported; Send WR1_1 or WR2_1 pulse signal as the starting impulse signal of pulsqe distributor a work; When carrying out normal memory read-write function command, reset pulse divider a;

When the temporary control module a in described command register and address was reset, all order output terminals were " 1 "; For the data transfer command between two storage unit in the order that writes data or the two-port RAM storage unit, after the command parameter of this order write described command register and the temporary control module a in address, CS_1 was by " 0 " → " 1 ";

The input end of described combinational logic circuit module a is connected with 11 order output terminals of command register and the temporary control module a in address, and also the pulse output end with pulsqe distributor a is connected; The output terminal of described combinational logic circuit module a is the logical combination of these input signals, comprising: with logic output and or logic output, described and logic output have by with door X IV～with 6 and a gate output terminal that the X IX constitutes; The output of described or logic have by or door X III～or door XXX IV 22 or gate output terminal constituting;

Described pulsqe distributor a is as inner sequence timer, output pulse 1. _ 1, pulse 2. _ 1, pulse 3. _ 1, pulse 4. _ 1, pulse 5. _ 1, pulse 6. _ 1, pulse 7. _ 1 and pulse 8. _ 1 be combinational logic circuit module a, Data Transmission Controlling module a, the address tunnel control module a provide the time sequential pulse signal; Described pulsqe distributor a is also to the temporary control module a output of command register and address reset signal;

Described Data Transmission Controlling module a is at the WR2_1 signal of addressing function control _ 1 signal, RD_1, WR_1, the temporary control module a output of command register and address, pulsqe distributor a(IV) Shu Chu time sequential pulse, and under combinational logic circuit module a and the effect logic output valve, realize the DB_11 of two-port RAM storage unit and the Data Transmission Controlling of DB_1 bus; And also under a's or the logic output valve the effect of the time sequential pulse of pulsqe distributor a output and combinational logic circuit module, according to performed order output RD_12 and WR_12 signal;

Described address tunnel control module a is under the effect of the time sequential pulse of the output logic value of combinational logic circuit module a and pulsqe distributor a output, according to the address value of the temporary control module a output of command register and address and performed instruction and the order AB_11 transport address value to the two-port RAM storage unit;

Described read-write arbitration circuit module a is according to master/slave selection signal, if master/slave selection signal is " 0 ", reading-writing port A is master port, and reading-writing port B is from the control port; The output RD_12 of described Data Transmission Controlling module a output and the WR_12 signal RD_11 and the WR_11 signal input part that are transferred to described two-port RAM storage unit then;

If master/slave selection signal is " 1 ", then reading-writing port A is that reading-writing port B is master port from the control port; The RD_22 of described Data Transmission Controlling module b output and the WR_22 signal RD_21 and the WR_21 signal input part that are transferred to described two-port RAM storage unit then;

For the RD_12 signal of described Data Transmission Controlling module a output, whether equate whether WR_21 is " 0 " according to the AB_11 of described two-port RAM storage unit and the fiducial value of AB_21, whether arbitration RD_12 signal can be transferred to RD_11; If master port WR_21 is " 0 ", the value of AB_11 and AB_21 equates that described read-write arbitration circuit module a blocks RD_12.Signal makes RD_11 keep one state, if this moment, the RD_12 signal was " 0 ", sends look-at-me;

For the WR_12 signal of described Data Transmission Controlling module a output, whether equate according to the AB_11 of described two-port RAM storage unit and the fiducial value of AB_21 whether WR_21 or RD_21 are whether " 0 " arbitration WR_12 signal can be transferred to WR_11; If master port WR_21 or RD_21 are " 0 ", the value of AB_11 and AB_21 equates that described read-write arbitration circuit module a blocks the WR_12 signal, makes WR_11 keep one state, if this moment, WR_12 was " 0 ", sends look-at-me.

Its further technical scheme is: the temporary control module a in described command register and address comprises+1 counter, command register I, command decoder I, address register I, address register II, not gate I, not gate II and with the door I; The RESET input of described+1 counter is connected with the output terminal of not gate I, Enable Pin is connected with the CS_1 signal wire, counting end is connected with the WR_1 signal wire, CS_1 is " 0 ", the RESET input is " 1 ", and under the effect of WR_1 pulse signal ,+1 counter carries out+1 operation, first+1 operation output WR1_1, it is worth from " 1 " → " 0 "; Second WR_1 count pulse makes WR1_1 from " 0 " → " 1 "; WR2_1 is from " 1 " → " 0 "; If CS_1 is " 1 " ,+1 counter is reset, and WR1_1 and WR2_1 are one state; The WR1_1 pulse output end of+1 counter is connected with pulsqe distributor a with the write signal input end of command register I, address register I, and the WR2_1 pulse output end is connected with write signal input end, pulsqe distributor a and the Data Transmission Controlling module a of address register II;

The Enable Pin of described command register I is connected with the CS_1 signal wire; Reset terminal is connected with pulsqe distributor a; Data input pin is connected with DB_1; Command code (the D of described command register I ₃₁-D ₂₆) output terminal is connected with the command information input end of command decoder I; The R of the indirect addressing storage unit of described command register I output _i_ 1(D ₂₅-D ₂₁) and R _j_ 1(D ₂₀-D ₁₆) address value, side-play amount sft_1 (D ₁₅~ D ₀) be connected with address tunnel control module a as the OPADD signal; When the command register I is reset, the command code output terminal all is " 1 ";

The order output terminal of described command decoder I is connected with combinational logic circuit module a; 11 command decoder values of command decoder I output when carrying out any order, have only this order output terminal to be " 0 ", and other order output terminal is " 1 "; When the command code output terminal of command register I all is " 1 "; The all order output terminals of command decoder I are " 1 ";

The input end of described address register I is connected with AB_1, and output terminal is connected with address tunnel control module a;

The input end of described address register II is connected with AB_1, and output terminal is connected with address tunnel control module a;

The input end of not gate I is connected with the CS_1 signal wire;

The input end of not gate II is connected with pulsqe distributor a; Output terminal be connected with an input end of door I;

Be connected with the CS_1 signal wire with another input end of door I; Output terminal is connected with the CS_11 signal input part of two-port RAM storage unit; When the CS_1 signal is " 0 ", the input end of not gate II is " 1 " or during for " 0 ", or the CS_1 of system signal is " 1 ", and when the input end of not gate II was " 1 ", the CS_11 signal input part of two-port RAM storage unit was " 0 ".

Its further technical scheme is: described pulsqe distributor a comprise the pulse producer I, with the door II or the door I or the door II and with the door III;

The RESET input of described pulse producer I is connected with output terminal with the door II; The starting impulse signal input part is connected with output terminal with the door III; Clock pulse input terminal is connected with the system clock line, pulse 9. _ 1 output terminal be connected with an input end of door II; Pulse 1. _ 1, pulse 2. _ 1, pulse 3. _ 1, pulse 4. _ 1, pulse 5. _ 1, pulse 6. _ 1, pulse 7. _ 1, pulse 8. _ 1 output terminal be connected with combinational logic circuit module a; Pulse 1. _ 1, pulse 2. _ 1, pulse 4. _ 1 output terminal also be connected with address tunnel control module a; Pulse 2. _ 1 output terminal also is connected with Data Transmission Controlling module a;

Is connected with addressing function control _ 1 with read-write arbitration circuit module a respectively with two input ends of door II, other three input ends also respectively and or door XXX III or an XXX IV or an X III be connected;

Or the door I two input ends respectively with WR1_1 be connected with door X VII, output terminal be connected with an input end of door III;

Or the door II two input ends respectively with WR2_1 be connected with door X VI, output terminal be connected with an input end of door III;

The enabling signal input end of described pulse producer I is changed to " 0 " by " 1 ", and the RESET input is when being " 1 ", the work of starting impulse generator I.

Its further technical scheme is: described Data Transmission Controlling module a comprise data working storage triple gate group a, 32 triple gate group I a, 32 triple gate group II a or door III or door IV or door V or door VI or door VII or door VIII, with a door IV, with the door V and with the door VI;

The data input pin of described data working storage triple gate group a is connected with DB_1; Data write pulse input end with or the door III output terminal be connected; Output gating input end and or the output terminal of a V be connected; Data output end is connected with the DB_11 end of two-port RAM storage unit;

The data input pin of 32 triple gate group I a is connected with DB_1; Output gating input end and or the output terminal of a VI be connected; Data output end is connected with the DB_11 end of two-port RAM storage unit;

The data input pin of 32 triple gate group II a is connected with the DB_11 of two-port RAM storage unit end; Output gating input end is connected with output terminal with the door IV; Data output end is connected with DB_1;

Or two input ends of door III respectively with the WR2_1 pulse output end of+1 counter be connected with door X VII;

Or two input ends of door IV respectively with door X VII, be connected with an X VI; Output terminal with or the door V an input end be connected;

Or the door V another input end be connected with door X VII;

Or two input ends of door VI are connected with WR_1 with addressing function control _ 1 respectively; Output terminal also with an input end of door V is connected;

Or two input ends of door VII are connected with system RD_1 line with addressing function control _ 1 respectively; Output terminal be connected with an input end of door IV;

Or three input ends of door VIII respectively with RD_1, with X IV be connected with door X VI; Output terminal be connected with an input end of door IV;

Also with an input end of door VI be connected with the output terminal of door IV;

With other four input ends of door V also respectively with or door X IX or door X VIII or door X VII with or a door X VI be connected; Output terminal WR_12 is connected with read-write arbitration circuit module a;

With other three input ends of door VI also respectively with pulse 2. _ 1 or door X V with or a door X IV be connected; Output terminal RD_12 is connected with read-write arbitration circuit module a.

Its further technical scheme is: described address tunnel control module a comprise 5 alternative selector switch a, 32 three select a selector switch I a, 32 alternative selector switch I a, address arithmetic device I a, 32 alternative selector switch II a, address output latch I a, address output latch II a, address output latch III a, 32 four select a selector switch a, with a door VII, with a door VIII, with a door IX, with the door X and with the door XI;

The R of described 5 alternative selector switch a _iThe R of _ 1 address input end and command register I _i_ 1 address output end connects; R _jThe R of _ 1 address input end and command register I _j_ 1 address output end connects; The gating control input end with or the door XX be connected; Output terminal is connected with low 5 of the input end of 32 alternative selector switch I a;

32 three are selected the input end of a selector switch I a to be connected with the DB_11 end of two-port RAM storage unit; An input end is connected with the address value output terminal of address register I; An input end is connected with the address value output terminal of address register II; Gating end is connected with output terminal with the door VII; Gating end with or a door XX III be connected; Output terminal is connected with the input end of 32 alternative selector switch I a;

High 27 of the input end of 32 alternative selector switch I a are connected with " 0 "; The gating end is connected with output terminal with the door VIII; Address output end is connected with the input end of address arithmetic device I a and the input end of 32 alternative selector switch II a;

Another side-play amount sft_1 input end of address arithmetic device I a is connected with the sft_1 output terminal of command register I; Address arithmetic output terminal as a result is connected with the input end of 32 alternative selector switch II a;

The gating input end of 32 alternative selector switch II a is connected with the output terminal with the door IX; Address output end is connected with the address input end of address output latch III a with address output latch I a, address output latch II a;

The latch pulse input end of address output latch I a is connected with the output terminal with the door X; Output terminal selects the input end of a selector switch a to be connected with 32 four;

2. _ 1 the latch pulse input end of address output latch II a is connected with pulse; Output terminal selects the input end of a selector switch a to be connected with 32 four;

4. _ 1 the latch pulse input end of address output latch III a is connected with pulse; Output terminal selects the input end of a selector switch a to be connected with 32 four;

32 four are selected the input end of a selector switch a also to be connected with AB_1; A gating end is connected with addressing function control _ 1; Gating end is connected with output terminal with the door XI; Gating end with or the output terminal of door XX XII be connected; Output terminal is connected with AB_11 input end, the read-write arbitration circuit module b of two-port RAM storage unit;

With two input ends of door VII respectively with or door XX XI or a door X XII be connected;

With two input ends of door VIII respectively with or door XX IV or a door XX V be connected;

With two input ends of door IX respectively with or door XX VI or a door XX VII be connected;

With three input ends of door X respectively with pulse 1. _ 1 or door XX VIII with or a door XX IX be connected;

With three input ends of door XI respectively with door X V or door XXX with or a door XX XI be connected.

Its further technical scheme is: described read-write arbitration circuit module a comprise address comparator, with door an XII, rejection gate I, rejection gate II or door IX or door X, not gate III, not gate IV or door XI or door XII and with door X III;

Two address input ends of described address comparator are connected with the AB_11 output terminal of address tunnel control module a and the AB_21 output terminal of address tunnel control module b respectively, Enable Pin is connected with system master/slave selection line, an input end of output terminal and rejection gate I, an input end of rejection gate II connects;

Be connected with the WR_21 of read-write arbitration circuit module b and the output terminal of RD_21 respectively with two input ends of door XII, an input end of output terminal and rejection gate I is connected;

The output terminal of rejection gate I and or an input end of door IX, the input end of not gate IV connects;

Another input end of rejection gate II is connected with the WR_21 output terminal of read-write arbitration circuit module b, output terminal and or an input end of door X, the input end connection of not gate III;

Or the door IX another input end be connected with the WR_12 output terminal of Data Transmission Controlling module a, output terminal is connected with the WR_11 input end of two-port RAM storage unit;

Or the door X another input end be connected with the RD_12 output terminal of Data Transmission Controlling module a, output terminal is connected with the RD_11 input end of two-port RAM storage unit;

The output terminal of not gate III with or the door XI an input end be connected;

The output terminal of not gate IV with or the door XII an input end be connected;

Or the door XI another input end be connected with the RD_12 output terminal of Data Transmission Controlling module a, output terminal be connected with an input end of door X III;

Or the door XII another input end be connected with the WR_12 output terminal of Data Transmission Controlling module a, output terminal be connected with an input end of door X III;

With the output terminal of door X III and pulsqe distributor a with the door II OneIndividual input end connects, and output look-at-me _ 1.

Because adopt above structure, the integrated dual-port memory controller of the present invention's addressing and storage unit has following beneficial effect:

One, can realize addressing, address arithmetic and the read-write operation function of two reading-writing port of autonomous control store:

Among the present invention, a reading-writing port or two reading-writing port of the integrated dual-port memory controller of addressing and storage unit are chosen by system, under the effect of the WR_1 of system or WR_2 signal, order, address and the number immediately that need write are write the temporary control modules of the command register of a reading-writing port or two reading-writing port and addresses, pulsqe distributor is activated, and the integrated dual-port memory controller of addressing and storage unit is independently finished addressing, address arithmetic and read-write operation under the time sequential pulse effect of the pulsqe distributor of a reading-writing port or two reading-writing port; For the data transfer command between the order that writes data or two storage unit, after the command parameter of this order writes the temporary control module of command register and address, CS_1 by " 0 " → " 1 " (referring to Figure 10, Figure 11); Realize that integrated memory controller carries out the parallel work-flow that the addressing operation of this class order, data transmission and ablation process and microprocessor are carried out other instruction sequence processes; In the sense data process, under inner time sequential pulse effect, independently finish the addressing of storage unit, system sends integrated memory controller according to the sequential requirement and reads (RD) signal, the data of this storage unit are sent to the data bus of system, fully used the parallel processing function of FPGA.

Two, also remain with the read-write operation function of general dual-ported memory:

Among the present invention, still the read-write operation function that keeps general dual-ported memory, a reading-writing port or two reading-writing port of being integrated dual-port memory controller are chosen some storage unit respectively, under the pulse action of the RD_1 of system or RD_2, WR_1 or WR_2, the memory cell data of choosing is transferred to system data bus separately, or the data of data bus write selected respectively storage unit separately.

Three, can realize dual port memory unit data transmission each other efficiently:

Among the present invention, indirect addressing register and base register in the two-port RAM storage unit, have been designed, data channel control and address tunnel controller, under the control of inner time sequential pulse, there is multiple addressing mode to realize that the data of a storage unit write another storage unit, system only needs the write-once operational order, having simplified needs data to be written are read the some registers that are written in the microprocessor from a storage unit, read the operating process that writes another storage unit by system data bus from this register then, microprocessor need carry out the operation of read command operation and a write order to dual port memory unit in this case.

Four, systemic price ratio height:

The present invention is core with the hard connection control circuit of FPGA, make up the integrated dual-port memory controller of a kind of addressing and storage unit, two reading-writing port have adopted the inside arbitrated logic control of master/slave selection mode, master port and from the control port same storage unit is write, or master port is write a storage unit, when from the control port same storage unit being carried out read operation, will block from the write or read signal of control port, and send look-at-me; Also has the storage unit as indirect addressing and plot+index usefulness in the dual-ported memory, common storage unit is also arranged, read-write capability with common double port store, the function that also has multiple indirect addressing mode, can realize the function of dual-ported memory internal storage unit data transmission each other, its address arithmetic and addressing process are controlled by inner time sequential pulse, can improve the speed of microprocessor execution command sequence, have high cost performance.

Below in conjunction with drawings and Examples the present invention's addressing and the technical characterictic of the integrated dual-port memory controller of storage unit are further described.

Description of drawings

Fig. 1: the pinouts of the addressing of the integrated dual-port memory controller of the present invention's addressing and storage unit and the integrated dual-port memory controller of storage unit;

Fig. 2: the storage unit of the integrated dual-port memory controller of the present invention's addressing and storage unit is distributed synoptic diagram;

Fig. 3: the system construction drawing of the integrated dual-port memory controller of the present invention's addressing and storage unit;

Fig. 4: the circuit connection diagram of the temporary control module a in the command register of the integrated dual-port memory controller of the present invention's addressing and storage unit and address;

Fig. 5: the circuit connection diagram of the pulsqe distributor a of the integrated dual-port memory controller of the present invention's addressing and storage unit;

Fig. 6: the circuit connection diagram of the Data Transmission Controlling module a of the integrated dual-port memory controller of the present invention's addressing and storage unit;

Fig. 7: the circuit connection diagram of the address tunnel control module a of the integrated dual-port memory controller of the present invention's addressing and storage unit;

Fig. 8: the circuit connection diagram of the read-write arbitration circuit module a of the integrated dual-port memory controller of the present invention's addressing and storage unit;

Fig. 9: the combinational logic circuit module input and output pin figure of the integrated dual-port memory controller of the present invention's addressing and storage unit;

Figure 10: the execution MOV @R of the integrated dual-port memory controller of the present invention's addressing and storage unit _i， @R _jThe sequential chart of+sft order;

Figure 11: the execution MOV M of the integrated dual-port memory controller of the present invention's addressing and storage unit _i, M _jThe sequential chart of order.

Among the figure:

I-two-port RAM storage unit, A-port A, B-port B;

Control module a is kept in II-command register and address, III-combinational logic circuit module a, IV-pulsqe distributor a; V-Data Transmission Controlling module a, VI-address tunnel control module a; VII-read-write arbitration circuit module a;

Control module b is kept in VIII-command register and address, IX-combinational logic circuit module b, X-pulsqe distributor b; XI-Data Transmission Controlling module b, XII-address tunnel control module b; X III-read-write arbitration circuit module b;

1-+1 counter, 2-command register I, 3-command decoder I, 4-address register I, 5-address register II, 6-not gate I, 7-not gate II, 8-with the door I;

9-pulse producer I a, 10-with a door II, 11-or door I, 12-or door II, 13-with III;

14-data working storage triple gate group a, 15-32 triple gate group I a, 16-32 triple gate group II a, 17-or the door III, 18-or the door IV, 19-or the door V, 20-or the door VI, 21-or the door VII, 22-or door VIII, 23-with a door IV, 24-with V, 25-with a VI;

26-4 alternative selector switch a, 27-32 three are selected a selector switch I a, 28-32 alternative selector switch I a, 29-address arithmetic device I a, 30-32 alternative selector switch II a, 31-address output latch I a, 32-address output latch II a, 33-address output latch III a, 34-32 four are selected a selector switch a, 35-with the door VII, 36-with the door VIII, 37-with a door IX, 38-with a door X, 39-with XI;

40-address comparator, 41-with a door XII, 42-rejection gate I, 43-rejection gate II, 44-or door IX, 45-or door X, 46-not gate III, 47-not gate IV, 48-or door XI, 49-or door XII, 50-with an X III;

The XT-gating, the input of SCMSR-latch pulse.

Abbreviation in the literary composition

FPGA-Field Programmable Gate Array, field programmable gate array;

WR-Write, write signal, RD-Read, read signal; CS-Chip Selection, chip selection signal;

AB-Address Bus, address bus; DB-Data Bus, data bus;

RAM-Random access memory, storer; Sft-Shift, side-play amount.

Embodiment

The integrated dual-port memory controller of a kind of addressing and storage unit, as shown in Figure 3, the integrated dual-port memory controller of this addressing and storage unit comprises two-port RAM storage unit I and two fully independently reading-writing port A and reading-writing port B;

The basic structure of described two-port RAM storage unit I is identical with common double port ram storer; Be provided with as indirect addressing and plot in the two-port RAM storage unit I and add the storage unit R that indexed addressing is used ₀-R ₃₁

The addressing of described reading-writing port A and reading-writing port B is identical with circuit structure with the integrated sequential control method of storage unit, the steering logic that is master/slave selection is opposite, namely working as master/slave selection line is " 0 ", and reading-writing port A is master port, and reading-writing port B is from the control port; When master/slave selection line is " 1 ", then reading-writing port A is that reading-writing port B is master port from the control port;

Described reading-writing port A comprises the temporary control module a II of command register and address, combinational logic circuit module a III, pulsqe distributor a IV, Data Transmission Controlling module a V, address tunnel control module a VI and read-write arbitration circuit module a VII realize the control function of the reading-writing port A of described two-port RAM storage unit I;

Described reading-writing port B comprises the temporary control module b VIII of command register and address, combinational logic circuit module b IX, pulsqe distributor b X, Data Transmission Controlling module b XI, address tunnel control module b XII and read-write arbitration circuit module b X III realize the control function of the reading-writing port B of described two-port RAM storage unit I;

Control module a II is kept in described two-port RAM storage unit I and command register and address, Data Transmission Controlling module a V, address tunnel control module a VI, read-write arbitration circuit module a VII, control module b VIII is kept in command register and address, Data Transmission Controlling module b XI, address tunnel control module b XII, read-write arbitration circuit module b X III connects;

The temporary control module a II in described command register and address also with combinational logic circuit module a III, pulsqe distributor a IV, Data Transmission Controlling module a V, address tunnel control module a VI connects;

Described combinational logic circuit module a III also with pulsqe distributor a IV, Data Transmission Controlling module a V, address tunnel control module a VI connects;

Described pulsqe distributor a IV also with Data Transmission Controlling module a V, address tunnel control module a VI, read-write arbitration circuit module a VII connects;

Described Data Transmission Controlling module a V also with address tunnel control module a VI, read-write arbitration circuit module a VII connects;

Described address tunnel control module a VI also is connected with read-write arbitration circuit module b X III;

Described read-write arbitration circuit module a VII also with read-write arbitration circuit module b X III, address tunnel control module b XII connects;

The temporary control module a II in described command register and address is when CS_1 is " 0 ", under the effect of the WR_1 of system signal, store instruction codes and decoding, the address value of indirect memory addressing and plot+indexed addressing memory unit address value, side-play amount and directly address is also exported; If also have the address value of the 2nd directly address, then under the effect of second WR_1 signal of system, store the address value of the 2nd directly address and exported; Send WR1_1 or WR2_1 pulse signal as the starting impulse signal of pulsqe distributor a IV work; When carrying out normal memory read-write function command, reset pulse divider a IV; When the temporary control module a II in described command register and address was reset, all order output terminals were " 1 "; For the data transfer command between two storage unit in the order that writes data or the two-port RAM storage unit I, after the command parameter of this order writes the temporary control module a II of described command register and address, CS_1 by " 0 " → " 1 " (referring to Figure 10, Figure 11);

The input end of described combinational logic circuit module a III is connected with 11 order output terminals of the temporary control module a II of command register and address, and also the pulse output end with pulsqe distributor a IV is connected; The output terminal of described combinational logic circuit module a III is the logical combination of these input signals, comprising: with logic output and or logic output, described and logic output have by with door X IV～with 6 and a gate output terminal that the X IX constitutes; The output of described or logic have by or door X III～or door XXX IV 22 or gate output terminal (referring to Fig. 8, subordinate list one, subordinate list three and subordinate list four) constituting;

Described pulsqe distributor a IV is as inner sequence timer, output pulse 1. _ 1, pulse 2. _ 1, pulse 3. _ 1, pulse 4. _ 1, pulse 5. _ 1, pulse 6. _ 1, pulse 7. _ 1 and pulse 8. _ 1, for combinational logic circuit module a III, Data Transmission Controlling module a V and address tunnel control module a VI provide the time sequential pulse signal; Described pulsqe distributor a IV is also to the temporary control module a II output of command register and address reset signal;

Described Data Transmission Controlling module a V is at the WR2_1 signal of the temporary control module a II output of addressing function control _ 1 signal, RD_1, WR_1 and command register and address, the time sequential pulse of pulsqe distributor a IV output, and combinational logic circuit module a III with the effect logic output valve under, realize the DB_11 of two-port RAM storage unit I and the Data Transmission Controlling of DB_1 bus; And also under the time sequential pulse and combinational logic circuit module a effect III or the logic output valve of the output of pulsqe distributor a IV, according to performed order output RD_12 and WR_12 signal;

Described address tunnel control module a VI is under the effect of the time sequential pulse of the output logic value of combinational logic circuit module a III and the output of pulsqe distributor a IV, according to the address value of the temporary control module a II output of command register and address and performed instruction and the order AB_11 transport address value to two-port RAM storage unit I;

Described read-write arbitration circuit module a VII is according to master/slave selection signal, if master/slave selection signal is " 0 ", reading-writing port A is master port, and reading-writing port B is from the control port; The output RD_12 of described Data Transmission Controlling module a V output and the WR_12 signal RD_11 and the WR_11 signal input part that are transferred to described two-port RAM storage unit I then;

If master/slave selection signal is " 1 ", then reading-writing port A is that reading-writing port B is master port from the control port; The RD_22 of described Data Transmission Controlling module b XI output and the WR_22 signal RD_21 and the WR_21 signal input part that are transferred to described two-port RAM storage unit I then;

For the RD_12 signal of described Data Transmission Controlling module a V output, whether equate whether WR_21 is " 0 " according to the AB_11 of described two-port RAM storage unit I and the fiducial value of AB_21, whether arbitration RD_12 signal can be transferred to RD_11; If master port WR_21 is " 0 ", the value of AB_11 and AB_21 equates that described read-write arbitration circuit module a VII is blocked the RD_12 signal, makes RD_11 keep one state, if this moment, the RD_12 signal was " 0 ", sends look-at-me;

For the WR_12 signal of described Data Transmission Controlling module a V output, whether equate according to the AB_11 of described two-port RAM storage unit I and the fiducial value of AB_21 whether WR_21 or RD_21 are whether " 0 " arbitration WR_12 signal can be transferred to WR_11; If master port WR_21 or RD_21 are " 0 ", the value of AB_11 and AB_21 equates that described read-write arbitration circuit module a VII is blocked the WR_12 signal, makes WR_11 keep one state, if this moment, WR_12 was " 0 ", sends look-at-me.

As shown in Figure 4, the temporary control module a II in described command register and address comprise+1 counter 1, command register I 2, command decoder I 3, address register I 4, address register II 5, not gate I 6, not gate II 7 and with door I 8; The RESET input of described+1 counter 1 is connected with the output terminal of not gate I 6, Enable Pin is connected with the CS_1 signal wire, counting end is connected with the WR_1 signal wire, CS_1 is " 0 ", the RESET input is " 1 ", and under the effect of WR_1 pulse signal ,+1 counter 1 carries out+1 operation, first+1 operation output WR1_1, it is worth from " 1 " → " 0 "; Second WR_1 count pulse makes WR1_1 from " 0 " → " 1 "; WR2_1 is from " 1 " → " 0 "; If CS_1 is " 1 " ,+1 counter 1 is reset, and WR1_1 and WR2_1 are one state; The WR1_1 pulse output end of+1 counter 1 is connected with pulsqe distributor a IV with the write signal input end of command register I 2, address register I 4, and the WR2_1 pulse output end is connected with write signal input end, pulsqe distributor a IV and the Data Transmission Controlling module a V of address register II 5;

The Enable Pin of described command register I 2 is connected with the CS_1 signal wire; Reset terminal is connected with pulsqe distributor a IV; Data input pin is connected with DB_1; Command code (the D of described command register I 2 ₃₁-D ₂₆) output terminal is connected with the command information input end of command decoder I 3; The R of the indirect addressing storage unit of described command register I 2 outputs _i_ 1(D ₂₅-D ₂₁) and R _j_ 1 (D ₂₀-D ₁₆) address value, side-play amount sft_1(D ₁₅~ D ₀) be connected with address tunnel control module a VI as the OPADD signal; When command register I 2 is reset, the command code output terminal all is that " 1 " is (referring to subordinate list two: the command format table of the integrated dual-port memory controller of the present invention's addressing and storage unit);

The order output terminal of described command decoder I 3 is connected with combinational logic circuit module a III; 11 command decoder values of command decoder I 3 output when carrying out any order, have only this order output terminal to be " 0 ", and other order output terminal is " 1 "; When the command code output terminal of command register I 2 all was " 1 ", command decoder I 3 all order output terminals were " 1 ";

The input end of described address register I 4 is connected with AB_1, and output terminal is connected with address tunnel control module a VI;

The input end of described address register II 5 is connected with AB_1, and output terminal is connected with address tunnel control module a VI;

The input end of not gate I 6 is connected with the CS_1 signal wire;

The input end of not gate II 7 is connected with pulsqe distributor a IV; Output terminal be connected with an input end of door I 8;

Be connected with the CS_1 signal wire with another input end of door I 8; Output terminal is connected with the CS_11 signal input part of two-port RAM storage unit I; When the CS_1 signal is " 0 ", the input end of not gate II 7 is " 1 " or during for " 0 ", or the CS_1 of system signal is " 1 ", and when the input end of not gate II 7 was " 1 ", the CS_11 signal input part of two-port RAM storage unit I was " 0 ".

As shown in Figure 5, described pulsqe distributor a IV comprise pulse producer I 9, with the door II 10 or the door I 11 or the door II 12 and with door III 13; The RESET input of described pulse producer I 9 is connected with output terminal with door II 10; The starting impulse signal input part is connected with output terminal with door III 13; Clock pulse input terminal is connected with the system clock line, pulse 9. _ 1 output terminal be connected with an input end of door II 10; Pulse 1. _ 1, pulse 2. _ 1, pulse 3. _ 1, pulse 4. _ 1, pulse 5. _ 1, pulse 6. _ 1, pulse 7. _ 1, pulse 8. _ 1 output terminal be connected with combinational logic circuit module a III; Pulse 1. _ 1, pulse 2. _ 1, pulse 4. _ 1 output terminal also be connected with address tunnel control module a VI; Pulse 2. _ 1 output terminal also is connected with Data Transmission Controlling module a V;

Is connected with addressing function control _ 1 with read-write arbitration circuit module a VII respectively with two input ends of door II 10, other three input ends also respectively and or door XXX III or an XXX IV or an X III be connected;

Or the door I 11 two input ends respectively with WR1_1 be connected with door X VII, output terminal be connected with an input end of door III 13;

Or the door II 12 two input ends respectively with WR2_1 be connected with door X VI, output terminal be connected with an input end of door III 13;

The enabling signal input end of described pulse producer I 9 is changed to " 0 " by " 1 ", and the RESET input is when being " 1 ", the work of starting impulse generator I 9.

As shown in Figure 6: described Data Transmission Controlling module a V comprise data working storage triple gate group a14,32 triple gate group I a15,32 triple gate group II a16 or door III 17 or door IV 18 or door V 19 or door VI 20 or door VII 21 or door VIII 22, with a door IV 23, with door V 24 and with door VI 25;

The data input pin of described data working storage triple gate group a14 is connected with DB_1; Data write pulse input end with or the door III 17 output terminal be connected; Output gating input end and or the output terminal of a V 19 be connected; Data output end is connected with the DB_11 end of two-port RAM storage unit I;

The data input pin of 32 triple gate group I a15 is connected with DB_1; Output gating input end and or the output terminal of a VI 20 be connected; Data output end is connected with the DB_11 end of two-port RAM storage unit I;

The data input pin of 32 triple gate group II a16 is connected with the DB_11 of two-port RAM storage unit I end; Output gating input end is connected with output terminal with door IV 23; Data output end is connected with DB_1;

Or two input ends of door III 17 respectively with the WR2_1 pulse output end of+1 counter 1 be connected with door X VII;

Or two input ends of door IV 18 respectively with door X VII, be connected with an X VI; Output terminal with or the door V 19 an input end be connected;

Or the door V 19 another input end be connected with door X VII;

Or two input ends of door VI 20 are connected with WR_1 with addressing function control _ 1 respectively; Output terminal also with an input end of door V 24 is connected;

Or two input ends of door VII 21 are connected with system RD_1 line with addressing function control _ 1 respectively; Output terminal be connected with an input end of door IV 23;

Or three input ends of door VIII 22 respectively with RD_1, with X IV be connected with door X VI; Output terminal be connected with an input end of door IV 23;

Also with an input end of door VI 25 be connected with the output terminal of door IV 23;

With other four input ends of door V 24 also respectively with or door X IX or door X VIII or door X VII with or a door X VI be connected; Output terminal WR_12 is connected with read-write arbitration circuit module a VII;

With other three input ends of door VI 25 also respectively with pulse 2. _ 1 or door X V with or a door X IV be connected; Output terminal RD_12 is connected with read-write arbitration circuit module a VII.

As shown in Figure 7: the described address tunnel control module of described address tunnel control module a VI a VI comprises 5 alternative selector switch a26,32 three are selected a selector switch I a27,32 alternative selector switch I a28, address arithmetic device I a29,32 alternative selector switch II a30, address output latch I a31, address output latch II a32, address output latch III a33,32 four are selected a selector switch a34, with door VII 35, with door VIII 36, with door IX 37, with door X 38 and with door XI 39;

The R of described 5 alternative selector switch a26 _iThe R of _ 1 address input end and command register I 2 _i_ 1 address output end connects; R _jThe R of _ 1 address input end and command register I 2 _j_ 1 address output end connects; The gating control input end with or the door XX be connected; Output terminal is connected with low 5 of the input end of 32 alternative selector switch I a28;

32 three are selected the input end of a selector switch I a27 to be connected with the DB_11 end of two-port RAM storage unit I; An input end is connected with the address value output terminal of address register I 4; An input end is connected with the address value output terminal of address register II 5; Gating end is connected with output terminal with door VII 35; Gating end with or a door XX III be connected; Output terminal is connected with the input end of 32 alternative selector switch I a28;

High 27 of the input end of 32 alternative selector switch I a28 are connected with " 0 "; The gating end is connected with output terminal with door VIII 36; Address output end is connected with the input end of address arithmetic device I a29 and the input end of 32 alternative selector switch II a30;

Another side-play amount sft_1 input end of address arithmetic device I a29 is connected with the sft_1 output terminal of command register I 2; Address arithmetic output terminal as a result is connected with the input end of 32 alternative selector switch II a30;

The gating input end of 32 alternative selector switch II a30 is connected with the output terminal with door IX 37; Address output end is connected with the address input end of address output latch III a33 with address output latch I a31, address output latch II a32;

The latch pulse input end of address output latch I a31 is connected with the output terminal with door X 38; Output terminal selects the input end of a selector switch a34 to be connected with 32 four;

The latch pulse input end of address output latch II a32 and pulse are 2. _1 connects; Output terminal selects the input end of a selector switch a34 to be connected with 32 four;

The latch pulse input end of address output latch III a33 and pulse are 4. _1 connects; Output terminal selects the input end of a selector switch a34 to be connected with 32 four;

32 four are selected the input end of a selector switch a34 also to be connected with AB_1; A gating end is connected with addressing function control _ 1; Gating end is connected with output terminal with door XI 39; Gating end with or the output terminal of door XX XII be connected; Output terminal is connected with AB_11 input end, the read-write arbitration circuit module b X III of two-port RAM storage unit I;

With two input ends of door VII 35 respectively with or door XX XI or a door X XII be connected;

With two input ends of door VIII 36 respectively with or door XX IV or a door XX V be connected;

With two input ends of door IX 37 respectively with or door XX VI or a door XX VII be connected;

With three input ends of door X 38 respectively with pulse 1. _ 1 or door XX VIII with or a door XX IX be connected;

With three input ends of door XI 39 respectively with door X V or door XXX with or a door XX XI be connected.

As shown in Figure 8: described read-write arbitration circuit module a VII comprise address comparator 40, with door an XII 41, rejection gate I 42, rejection gate II 43 or door IX 44 or door X 45, not gate III 46, not gate IV 47 or door XI 48 or door XII 4 and with door X III 50;

Two address input ends of described address comparator 40 are connected with the AB_11 output terminal of address tunnel control module a VI and the AB_21 output terminal of address tunnel control module b XII respectively, Enable Pin is connected with system master/slave selection line, an input end of output terminal and rejection gate I 42, an input end of rejection gate II 43 connects;

Be connected with the WR_21 of read-write arbitration circuit module b X III and the output terminal of RD_21 respectively with two input ends of door XII 41, an input end of output terminal and rejection gate I 42 is connected;

The output terminal of rejection gate I 42 and or an input end of door IX 44, the input end of not gate IV 47 connects;

Another input end of rejection gate II 43 is connected with the WR_21 output terminal of read-write arbitration circuit module b X III, output terminal and or an input end of door X 45, the input end connection of not gate III 46;

Or the door IX 44 another input end be connected with the WR_12 output terminal of Data Transmission Controlling module a V, output terminal is connected with the WR_11 input end of two-port RAM storage unit I;

Or the door X 45 another input end be connected with the RD_12 output terminal of Data Transmission Controlling module a V, output terminal is connected with the RD_11 input end of two-port RAM storage unit I;

The output terminal of not gate III 46 with or the door XI 48 an input end be connected;

The output terminal of not gate IV 47 with or the door XII 49 an input end be connected;

Or the door XI 48 another input end be connected with the RD_12 output terminal of Data Transmission Controlling module a V, output terminal be connected with an input end of door X III 50;

Or the door XII 49 another input end be connected with the WR_12 output terminal of Data Transmission Controlling module a V, output terminal be connected with an input end of door X III 50;

With the output terminal of door X III 50 and pulsqe distributor a IV with door II 10 OneIndividual input end connects, and output look-at-me _ 1.

Because the present invention's addressing is identical with circuit structure with the integrated sequential control method of storage unit with the addressing of the reading-writing port A of the integrated dual-port memory controller of storage unit and reading-writing port B, the steering logic that is master/slave selection is opposite; Therefore,

The temporary control module b VIII in the command register of formation the present invention's addressing and the reading-writing port B of the integrated dual-port memory controller of storage unit and address, combinational logic circuit module b IX, pulsqe distributor b X, Data Transmission Controlling module b XI, each module concrete structure of address tunnel control module b XII and read-write arbitration circuit module b X III and the temporary control module a II of command register and address of the reading-writing port A of the addressing that constitutes the present invention and the integrated dual-port memory controller of storage unit, combinational logic circuit module a III, pulsqe distributor a IV, Data Transmission Controlling module a V, each module concrete structure of address tunnel control module a VI and read-write arbitration circuit module a VII is identical, repeats no more herein; The characteristics that the steering logic of its master/slave selection is opposite are also expressed in Fig. 3, also are that those skilled in the art can be straightforward according to each several part structure and Fig. 3 of reading-writing port A, also repeat no more herein.

Subordinate list one: the instruction of the integrated dual-port memory controller of the present invention's addressing and storage unit and order numbering corresponding tables

Subordinate list two: the command format table of the integrated dual-port memory controller of the present invention's addressing and storage unit

Subordinate list three: the integrated dual-port memory controller of the present invention's addressing and storage unit with logical combination and order, pulse numbering corresponding tables

Subordinate list four: the integrated dual-port memory controller of the present invention's addressing and storage unit or logical combination and with the corresponding tables of logical combination, order, pulse numbering

Claims

1. an addressing and the integrated dual-port memory controller of storage unit, comprise two-port RAM storage unit (I) and two fully independently reading-writing port A and reading-writing port B, the basic structure of described two-port RAM storage unit (I) is identical with common double port ram storer; It is characterized in that: be provided with as indirect addressing and plot in the described two-port RAM storage unit (I) and add the storage unit R that indexed addressing is used ₀-R ₃₁The addressing of described reading-writing port A and reading-writing port B is identical with circuit structure with the integrated sequential control method of storage unit, the steering logic that is master/slave selection is opposite, namely working as master/slave selection line is " 0 ", and reading-writing port A is master port, and reading-writing port B is from the control port; When master/slave selection line is " 1 ", then reading-writing port A is that reading-writing port B is master port from the control port;

The control circuit of described reading-writing port A comprises the temporary control module a(II of command register and address), combinational logic circuit module a(III), pulsqe distributor a(IV), Data Transmission Controlling module a(V), address tunnel control module a(VI) and read-write arbitration circuit module a(VII), realize the control function of the reading-writing port A of described two-port RAM storage unit (I);

The control circuit of described reading-writing port B comprises the temporary control module b(VIII of command register and address), combinational logic circuit module b(IX), pulsqe distributor b(X), Data Transmission Controlling module b(XI), address tunnel control module b(XII) and read-write arbitration circuit module b(X III), realize the control function of the reading-writing port B of described two-port RAM storage unit (I);

Described two-port RAM storage unit (I) and the temporary control module a(II of command register and address), Data Transmission Controlling module a(V), address tunnel control module a(VI), read-write arbitration circuit module a(VII), control module b(VIII is kept in command register and address), Data Transmission Controlling module b(XI), address tunnel control module b(XII), read-write arbitration circuit module b(X III) connect;

Control module a(II is kept in described command register and address) also with combinational logic circuit module a(III), pulsqe distributor a(IV), Data Transmission Controlling module a(V), address tunnel control module a(VI) connect;

Described combinational logic circuit module a(III) also with pulsqe distributor a(IV), Data Transmission Controlling module a(V), address tunnel control module a(VI) connect;

Described pulsqe distributor a(IV) also with Data Transmission Controlling module a(V), address tunnel control module a(VI), read-write arbitration circuit module a(VII) connect;

Described Data Transmission Controlling module a(V) also with address tunnel control module a(VI), read-write arbitration circuit module a(VII) connect;

Described address tunnel control module a(VI) also with read-write arbitration circuit module b(X III) be connected;

Described read-write arbitration circuit module a(VII) also with read-write arbitration circuit module b(X III), address tunnel control module b(XII) connect;

Control module a(II is kept in described command register and address) when CS_1 is " 0 ", under the effect of the WR_1 of system signal, store instruction codes and decoding, the address value of storage indirect addressing and plot+indexed addressing memory unit address value, side-play amount and directly address is also exported; If also have the address value of the 2nd directly address, then under the effect of second WR_1 signal of system, store the address value of the 2nd directly address and exported; Send WR1_1 or WR2_1 pulse signal as pulsqe distributor a(IV) work the starting impulse signal; When carrying out normal memory read-write function command, reset pulse divider a(IV); Control module a(II is kept in described command register and address) when being reset, all order output terminals are " 1 "; For the data transfer command between two storage unit in the order that writes data or the two-port RAM storage unit (I), when the command parameter of this order writes the temporary control module a(II of described command register and address) after, CS_1 is by " 0 " → " 1 ";

Described combinational logic circuit module a(III) 11 order output terminals temporary control module a(II in input end and command register and address) are connected, also with pulsqe distributor a(IV) pulse output end be connected; Described combinational logic circuit module a(III) output terminal is the logical combination of these input signals, comprising: with logic output and or logic output, described and logic output have by with door X IV～with 6 and a gate output terminal that the X IX constitutes; The output of described or logic have by or door X III～or door XXX IV 22 or gate output terminal constituting;

Described pulsqe distributor a(IV) as inner sequence timer, output pulse 1. _ 1, pulse 2. _ 1, pulse 3. _ 1, pulse 4. _ 1, pulse 5. _ 1, pulse 6. _ 1, pulse 7. _ 1 and pulse 8. _ 1 be combinational logic circuit module a(III), Data Transmission Controlling module a(V), address tunnel control module a(VI) provide the time sequential pulse signal; Described pulsqe distributor a(IV) also to the temporary control module a(II of command register and address) the output reset signal;

Described Data Transmission Controlling module a(V) the temporary control module a(II in addressing function control _ 1 signal, RD_1, WR_1, command register and address) the WR2_1 signal of output, pulsqe distributor a(IV) Shu Chu time sequential pulse, and combinational logic circuit module a(III) under and the effect logic output valve, realizes the DB_11 of two-port RAM storage unit (I) and the Data Transmission Controlling of DB_1 bus; And also in pulsqe distributor a(IV) time sequential pulse and the combinational logic circuit module a(III of output) or the effect of logic output valve under, according to performed order output RD_12 and WR_12 signal;

Described address tunnel control module a(VI) in combinational logic circuit module a(III) output logic value and pulsqe distributor a(IV) under the effect of time sequential pulse of output, according to the temporary control module a(II of command register and address) address value of output and performed instruction and order be to the AB_11 transport address value of two-port RAM storage unit (I);

Described read-write arbitration circuit module a(VII) according to master/slave selection signal, if master/slave selection signal is " 0 ", reading-writing port A is master port, and reading-writing port B is from the control port; Described Data Transmission Controlling module a(V then) the output RD_12 of output and the WR_12 signal RD_11 and the WR_11 signal input part that are transferred to described two-port RAM storage unit (I);

For the RD_12 signal of described Data Transmission Controlling module a output, whether equate whether WR_21 is " 0 " according to the AB_11 of described two-port RAM storage unit and the fiducial value of AB_21, whether arbitration RD_12 signal can be transferred to RD_11; If master port WR_21 is " 0 ", the value of AB_11 and AB_21 equates that described read-write arbitration circuit module a blocks the RD_12 signal, makes RD_11 keep one state, if this moment, the RD_12 signal was " 0 ", sends look-at-me;

For the WR_12 signal of described Data Transmission Controlling module a output, whether equate whether WR_21 or RD_21 are " 0 " according to the AB_11 of described two-port RAM storage unit and the fiducial value of AB_21, whether arbitration WR_12 signal can be transferred to WR_11; If master port WR_21 or RD_21 are " 0 ", the value of AB_11 and AB_21 equates that described read-write arbitration circuit module a blocks the WR_12 signal, makes WR_11 keep one state, if this moment, WR_12 was " 0 ", sends look-at-me.

2. the integrated dual-port memory controller of addressing as claimed in claim 1 and storage unit, it is characterized in that: control module a(II is kept in described command register and address) comprise+1 counter (1), command register I (2), command decoder I (3), address register I (4), address register II (5), not gate I (6), not gate II (7) and with door I (8); The RESET input of described+1 counter (1) is connected with the output terminal of not gate I (6), Enable Pin is connected with the CS_1 signal wire, counting end is connected with the WR_1 signal wire, CS_1 is " 0 ", the RESET input is " 1 ", and under the effect of WR_1 pulse signal ,+1 counter (1) carries out+1 operation, first+1 operation output WR1_1, it is worth from " 1 " → " 0 "; Second WR_1 count pulse makes WR1_1 from " 0 " → " 1 "; WR2_1 is from " 1 " → " 0 "; If CS_1 is " 1 " ,+1 counter (1) is reset, and WR1_1 and WR2_1 are one state; The write signal input end and pulsqe distributor a(IV of the WR1_1 pulse output end of+1 counter (1) and command register I (2), address register I (4)) be connected write signal input end, the pulsqe distributor a(IV of WR2_1 pulse output end and address register II (5)) with Data Transmission Controlling module a(V) be connected;

The Enable Pin of described command register I (2) is connected with the CS_1 signal wire; Reset terminal and pulsqe distributor a(IV) be connected; Data input pin is connected with DB_1; Command code (the D of described command register I (2) ₃₁-D ₂₆) output terminal is connected with the command information input end of command decoder I (3); The R of the indirect addressing storage unit of described command register I (2) output _i_ 1(D ₂₅-D ₂₁) and R _j_ 1(D ₂₀-D ₁₆) address value, side-play amount sft_1 (D ₁₅~ D ₀) as OPADD signal and address tunnel control module a(VI) be connected; When command register I (2) is reset, the command code output terminal all is " 1 ";

Shown in the order output terminal and combinational logic circuit module a(III of command decoder I (3)) be connected; 11 command decoder values of command decoder I (3) output when carrying out any order, have only this order output terminal to be " 0 ", and other order output terminal is " 1 "; When the command code output terminal of command register I (2) all was " 1 ", all order output terminals of command decoder I (3) were " 1 ";

Shown in the input end of address register I (4) be connected output terminal and address tunnel control module a(VI with AB_1) be connected;

Shown in the input end of address register II (5) be connected output terminal and address tunnel control module a(VI with AB_1) be connected;

The input end of not gate I (6) is connected with the CS_1 signal wire;

The input end of not gate II (7) and pulsqe distributor a(IV) be connected; Output terminal be connected with an input end of door I (8);

Be connected with the CS_1 signal wire with another input end of door I (8); Output terminal is connected with the CS_11 signal input part of two-port RAM storage unit (I); When the CS_1 signal is " 0 ", the input end of not gate II (7) is " 1 " or during for " 0 ", or the CS_1 of system signal is " 1 ", and when the input end of not gate II (7) was " 1 ", the CS_11 signal input part of two-port RAM storage unit (I) was " 0 ".

3. the integrated dual-port memory controller of addressing as claimed in claim 1 and storage unit is characterized in that: described pulsqe distributor a(IV) comprise pulse producer I (9), with door II (10) or door I (11) or door II (12) and with door III (13);

The RESET input of described pulse producer I (9) is connected with output terminal with door II (10); The starting impulse signal input part is connected with output terminal with door III (13); Clock pulse input terminal is connected with the system clock line, pulse 9. _ 1 output terminal be connected with an input end of door II (10); Pulse 1. _ 1, pulse 2. _ 1, pulse 3. _ 1, pulse 4. _ 1, pulse 5. _ 1, pulse 6. _ 1, pulse 7. _ 1, pulse 8. _ 1 output terminal and combinational logic circuit module a(III) be connected; Pulse 1. _ 1, pulse 2. _ 1, pulse 4. _ 1 output terminal also with address tunnel control module a(VI) be connected; Pulse 2. _ 1 output terminal also with Data Transmission Controlling module a(V) be connected;

With two input ends of door II (10) respectively with read-write arbitration circuit module a(VII) and addressing function control _ 1 is connected, other three input ends also respectively and or an XXX III or an XXX IV or an X III be connected;

Or the door I (11) two input ends respectively with WR1_1 be connected with door X VII, output terminal be connected with an input end of door III (13);

Or the door II (12) two input ends respectively with WR2_1 be connected with door X VI, output terminal be connected with an input end of door III (13);

The enabling signal input end of described pulse producer I (9) is changed to " 0 " by " 1 ", and the RESET input is when being " 1 ", the work of starting impulse generator I (9).

4. the integrated dual-port memory controller of addressing as claimed in claim 1 and storage unit is characterized in that: described Data Transmission Controlling module a(V) comprise data working storage triple gate group a(14), 32 triple gate group I a(15), 32 triple gate group II a(16) the door III (17) or the door IV (18) the door V (19) or the door VI (20) the door VII (21) or the door VIII (22), with the door IV (23), with the door V (24) and with door VI (25);

Described data working storage triple gate group a(14) data input pin is connected with DB_1; Data write pulse input end with or the door III (17) output terminal be connected; Output gating input end and or the output terminal of a V (19) be connected; Data output end is connected with the DB_11 end of two-port RAM storage unit (I);

32 triple gate group I a(15) data input pin is connected with DB_1; Output gating input end and or the output terminal of a VI (20) be connected; Data output end is connected with the DB_11 end of two-port RAM storage unit (I);

32 triple gate group II a(16) data input pin is connected with the DB_11 of two-port RAM storage unit (I) end; Output gating input end is connected with output terminal with door IV (23); Data output end is connected with DB_1;

Or two input ends of door III (17) respectively with the WR2_1 pulse output end of+1 counter (1) be connected with door X VII;

Or two input ends of door IV (18) respectively with door X VII, be connected with an X VI; Output terminal with or the door V (19) an input end be connected;

Or the door V (19) another input end be connected with door X VII;

Or two input ends of door VI (20) are connected with WR_1 with addressing function control _ 1 respectively; Output terminal also with an input end of door V (24) is connected;

Or two input ends of door VII (21) are connected with system RD_1 line with addressing function control _ 1 respectively; Output terminal be connected with an input end of door IV (23);

Or three input ends of door VIII (22) respectively with RD_1, with X IV be connected with door X VI; Output terminal be connected with an input end of door IV (23);

Also with an input end of door VI (25) be connected with the output terminal of door IV (23);

With other four input ends of door V (24) also respectively with or door X IX or door X VIII or door X VII with or a door X VI be connected; Output terminal WR_12 and read-write arbitration circuit module a(VII) be connected;

With other three input ends of door VI (25) also respectively with pulse 2. _ 1 or door X V with or a door X IV be connected; Output terminal RD_12 and read-write arbitration circuit module a(VII) be connected.

5. the integrated dual-port memory controller of addressing as claimed in claim 1 and storage unit is characterized in that: described address tunnel control module a(VI) comprise 5 alternative selector switch a(26), 32 three are selected a selector switch I a(27), 32 alternative selector switch I a(28), address arithmetic device I a(29), 32 alternative selector switch II a(30), address output latch I a(31), address output latch II a(32), address output latch III a(33), 32 four are selected a selector switch a(34), with door VII (35), with door VIII (36), with door IX (37), with door X (38) and with door XI (39);

Described 5 alternative selector switch a(26) R _iThe R of _ 1 address input end and command register I (2) _i_ 1 address output end connects; R _jThe R of _ 1 address input end and command register I (2) _j_ 1 address output end connects; The gating control input end with or the door XX be connected; Output terminal and 32 alternative selector switch I a(28) low 5 an of input end be connected;

32 three are selected a selector switch I a(27) input end be connected with the DB_11 end of two-port RAM storage unit (I); An input end is connected with the address value output terminal of address register I (4); An input end is connected with the address value output terminal of address register II (5); Gating end is connected with output terminal with door VII (35); Gating end with or a door XX III be connected; Output terminal and 32 alternative selector switch I a(28) an input end be connected;

32 alternative selector switch I a(28) high 27 of a input end are connected with " 0 "; The gating end is connected with output terminal with door VIII (36); Address output end and address arithmetic device I a(29) input end and 32 alternative selector switch II a(30) an input end be connected;

Address arithmetic device I a(29) another side-play amount sft_1 input end is connected with the sft_1 output terminal of command register I (2); Address arithmetic is output terminal and 32 alternative selector switch II a(30 as a result) an input end be connected;

32 alternative selector switch II a(30) gating input end is connected with the output terminal with door IX (37); Address output end and address output latch I a(31), address output latch II a(32) with address output latch III a(33) address input end be connected;

Address output latch I a(31) latch pulse input end is connected with the output terminal with door X (38); Output terminal selects a selector switch a(34 with 32 four) an input end be connected;

Address output latch II a(32) 2. _ 1 latch pulse input end is connected with pulse; Output terminal selects a selector switch a(34 with 32 four) an input end be connected;

Address output latch III a(33) 4. _ 1 latch pulse input end is connected with pulse; Output terminal selects a selector switch a(34 with 32 four) an input end be connected;

32 four are selected a selector switch a(34) an input end also be connected with AB_1; A gating end is connected with addressing function control _ 1; Gating end is connected with output terminal with door XI (39); Gating end with or the output terminal of door XX XII be connected; Output terminal is connected with AB_11 input end, the read-write arbitration circuit module b (X III) of two-port RAM storage unit (I);

With two input ends of door VII (35) respectively with or door XX XI or a door X XII be connected;

With two input ends of door VIII (36) respectively with or door XX IV or a door XX V be connected;

With two input ends of door IX (37) respectively with or door XX VI or a door XX VII be connected;

With three input ends of door X (38) respectively with pulse 1. _ 1 or door XX VIII with or a door XX IX be connected;

With three input ends of door XI (39) respectively with door X V or door XXX with or a door XX XI be connected.

6. the integrated dual-port memory controller of addressing as claimed in claim 1 and storage unit is characterized in that: described read-write arbitration circuit module a(VII) comprise address comparator (40), with a door XII (41), rejection gate I (42), rejection gate II (43) or door IX (44) or door X (45), not gate III (46), not gate IV (47) or door XI (48) or door XII (49) and with door X III (50);

Two address input ends of described address comparator (40) respectively with address tunnel control module a(VI) AB_11 output terminal and address tunnel control module b(XII) the AB_21 output terminal be connected, Enable Pin is connected with system master/slave selection line, an input end of output terminal and rejection gate I (42), an input end of rejection gate II (43) connects;

With two input ends of door XII (41) respectively with read-write arbitration circuit module b(X III) WR_21 and the output terminal of RD_21 be connected, an input end of output terminal and rejection gate I (42) is connected;

The output terminal of rejection gate I (42) and or an input end of door IX (44), the input end of not gate IV (47) connects;

Another input end of rejection gate II (43) and read-write arbitration circuit module b(X III) the WR_21 output terminal is connected, output terminal and or an input end of door X (45), the input end connection of not gate III (46);

Or the door IX (44) another input end and Data Transmission Controlling module a(V) the WR_12 output terminal be connected, output terminal is connected with the WR_11 input end of two-port RAM storage unit (I);

Or the door X (45) another input end and Data Transmission Controlling module a(V) the RD_12 output terminal be connected, output terminal is connected with the RD_11 input end of two-port RAM storage unit (I);

The output terminal of not gate III (46) with or the door XI (48) an input end be connected;

The output terminal of not gate IV (47) with or the door XII (49) an input end be connected;

Or the door XI (48) another input end and Data Transmission Controlling module a(V) the RD_12 output terminal be connected, output terminal be connected with an input end of door X III (50);

Or the door XII (49) another input end and Data Transmission Controlling module a(V) the WR_12 output terminal be connected, output terminal be connected with an input end of door X III (50);

Output terminal and pulsqe distributor a(IV with door X III (50)) be connected with an input end of door II (10), and output look-at-me _ 1.